AMD Vivado In-Depth Tutorials

https://github.com/xilinx/vivado-design-tutorials
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### Install ChipScoPy Examples

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Download the example scripts and pre-built designs.

```bash
chipscopy-get-examples
```

--------------------------------

### Example Address Calculations

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_02_Address_Mapping/README.md

Illustrates the calculation of start addresses for the first few transactions using the provided formula.

```text
Start address of the first transaction = 40_0000_0000 + 0x0000_0000 = 0x40_0000_0000
Start address of the second transaction = 0x40_0000_0000 + 0x0020_0000 = 0x40_0020_0000
Start address of the third transaction = 0x40_0000_0080 + 0x0040_0000 = 0x40_0040_0000
Start address of the fourth transaction = 0x40_0000_0100 + 0x0060_0000 = 0x40_0060_0000
```

--------------------------------

### BIF File Structure Example

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_plm_usb_second/readme.md

Example of a BIF file configuration with USB boot device enabled.

```text
new_bif:
{
 ...
 id = xxx
 boot_device {usb}
 image
 {
  ...
 }
}
```

--------------------------------

### Run example as Jupyter Notebook

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Launches the NoC performance monitor example within a Jupyter Notebook environment.

```bash
jupyter notebook noc_perfmon.ipynb
```

--------------------------------

### Run example as Python script

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the NoC performance monitor example as a standard Python script.

```bash
python noc_perfmon.py
```

--------------------------------

### ChipScoPy Examples Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

The directory structure created after running the example installation command.

```text
chipscopy-examples/
├── designs/
│   ├── vck190/production/chipscopy_ced/    # Pre-built design files (.pdi, .ltx)
│   ├── vek280/production/chipscopy_ced/
│   ├── vhk158/production/chipscopy_ced/
│   └── vmk180/production/chipscopy_ced/
├── noc_perfmon/
│   ├── noc_perfmon.py                      # Full NoC PerfMon example with GUI
│   ├── noc_perfmon.ipynb                   # Jupyter Notebook version
│   ├── noc_perfmon_basic.py                # Basic example (no GUI, console output)
│   ├── noc_perfmon_basic.ipynb
│   ├── sptg_example.py                    # Example using Soft Programmable TG
│   └── sptg_example.ipynb
└── ...
```

--------------------------------

### Setup cores with optional LTX file

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Conditional logic to call discover_and_setup_cores based on whether an LTX file is provided.

```python
if PROBES_FILE:
    versal_device.discover_and_setup_cores(noc_scan=True, ltx_file=PROBES_FILE)
else:
    versal_device.discover_and_setup_cores(noc_scan=True)
```

--------------------------------

### Install ChipScoPy

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Install the ChipScoPy package in the active virtual environment.

```bash
python -m pip install chipscopy
```

--------------------------------

### Prepare and Launch Guided Floorplan

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Disjoint_pblock/README.md

Unplaces the design, sources a Tcl script to guide the floorplan, and then creates the guided floorplan. This is used to resolve routing issues by controlling cell placement within disjoint Pblocks.

```tcl
place_design -unplace
source ./guide_disjoint_floorplan.tcl -notrace
dfx_utils::guided_floorplan::create_guided_floorplan
```

--------------------------------

### Start Hardware Server

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Initiates the Xilinx hardware server, which is necessary for XSDB to connect to the target board.

```shell
xsdb% hw_server
```

--------------------------------

### Create PetaLinux Project Step-by-Step

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Creates a PetaLinux project using the VCK190 BSP. This is the first step in the manual project setup.

```bash
petalinux-create project -n versal-dfx -s ./xilinx-vck190-v2024.1-05230256.bsp
```

--------------------------------

### Generate Original DCMAC Example Project

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_System_Designs/DCMAC_NoC/README.md

Use this command to generate the original 400G DCMAC example project. The Vivado projects will be built in the 'vivado_eg_ref' sub-directory.

```tcl
source create_dcmac_eg_ref_project.tcl
```

--------------------------------

### Sample PLM Boot Log

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_boot_time/README.md

Example output of the Platform Loader and Manager (PLM) log, showing boot stages and timing information.

```text
[4.131]PLM Initialization Time 
[4.195]***********Boot PDI Load: Started***********
[4.272]Loading PDI from QSPI32
[4.334]Monolithic/Master Device
[4.424]FlashID=0x20 0xBB 0x21
[4.590]0.286 ms: PDI initialization time
[4.664]+++Loading Image#: 0x1, Name: lpd, Id: 0x04210002
[4.750]---Loading Partition#: 0x1, Id: 0xC
[30.675]****************************************
[34.881]Xilinx Versal Platform Loader and Manager 
[39.254]Release 2021.1   Oct 14 2021  -  15:41:37
[43.544]Platform Version: v2.0 PMC: v2.0, PS: v2.0
[47.918]BOOTMODE: 0x2, MULTIBOOT: 0x0
[51.197]****************************************
[55.442] 50.582 ms for Partition#: 0x1, Size: 2336 Bytes
[60.280]---Loading Partition#: 0x2, Id: 0x0
[64.616] 0.520 ms for Partition#: 0x2, Size: 48 Bytes
[68.688]---Loading Partition#: 0x3, Id: 0x0
[72.921] 0.415 ms for Partition#: 0x3, Size: 61072 Bytes
[77.352]---Loading Partition#: 0x4, Id: 0x0
[81.202] 0.032 ms for Partition#: 0x4, Size: 2640 Bytes
[85.932]---Loading Partition#: 0x5, Id: 0x0
[89.787] 0.037 ms for Partition#: 0x5, Size: 3440 Bytes
[94.513]---Loading Partition#: 0x6, Id: 0x0
[98.347] 0.015 ms for Partition#: 0x6, Size: 80 Bytes
[108.159]+++Loading Image#: 0x2, Name: pl_cfi, Id: 0x18700000
[113.443]---Loading Partition#: 0x7, Id: 0x3
[121.097]PL supply status good
[124.499]PL POR B status good
[128.411]PL House Clean completed
[719.809] 602.460 ms for Partition#: 0x7, Size: 89410960 Bytes
[722.452]---Loading Partition#: 0x8, Id: 0x5
[753.114] 26.755 ms for Partition#: 0x8, Size: 427312 Bytes
[755.544]+++Loading Image#: 0x3, Name: fpd, Id: 0x0420C003
[760.557]---Loading Partition#: 0x9, Id: 0x8
[764.905] 0.441 ms for Partition#: 0x9, Size: 1104 Bytes
[769.595]+++Loading Image#: 0x4, Name: apu_subsystem, Id: 0x1C000000
[775.210]---Loading Partition#: 0xA, Id: 0x0
[780.207] 1.089 ms for Partition#: 0xA, Size: 163920 Bytes
[784.217]***********Boot PDI Load: Done***********
[788.552]23.528 ms: ROM Time
[791.043]Total PLM Boot Time
```

--------------------------------

### Setup Debug Cores

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/DDRMC_2D_eye_scan/python_code/versal_2d_eye_scan.ipynb

Discovers and sets up the necessary debug cores on the Versal device after programming. This enables debugging and analysis functionalities.

```python
print(f"Discovering debug cores...")
versal_device.discover_and_setup_cores()
print('DONE')
```

--------------------------------

### OSPI Flash Programming Output

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_boot_ospi/README.md

Example output showing the sequential write operations to the OSPI flash memory.

```text
device 0 offset 0xd0000, size 0x10000
SF: 65536 bytes @ 0xd0000 Written: OK                                           
Versal> 50%...sf write FFFC0000 E0000 10000                                     
device 0 offset 0xe0000, size 0x10000
SF: 65536 bytes @ 0xe0000 Written: OK                                           
Versal> sf write FFFC0000 F0000 10000                                           
device 0 offset 0xf0000, size 0x10000
SF: 65536 bytes @ 0xf0000 Written: OK                                           
Versal> sf write FFFC0000 100000 10000                                          
device 0 offset 0x100000, size 0x10000
SF: 65536 bytes @ 0x100000 Written: OK                                          
Versal> 60%...sf write FFFC0000 110000 10000                                    
device 0 offset 0x110000, size 0x10000
SF: 65536 bytes @ 0x110000 Written: OK                                          
Versal> sf write FFFC0000 120000 10000                                          
device 0 offset 0x120000, size 0x10000
SF: 65536 bytes @ 0x120000 Written: OK                                          
Versal> sf write FFFC0000 130000 10000                                          
device 0 offset 0x130000, size 0x10000
SF: 65536 bytes @ 0x130000 Written: OK                                          
Versal> sf write FFFC0000 140000 10000                                          
device 0 offset 0x140000, size 0x10000
SF: 65536 bytes @ 0x140000 Written: OK                                          
Versal> sf write FFFC0000 150000 10000                                          
device 0 offset 0x150000, size 0x10000
SF: 65536 bytes @ 0x150000 Written: OK                                          
Versal> sf write FFFC0000 160000 10000                                          
device 0 offset 0x160000, size 0x10000
SF: 65536 bytes @ 0x160000 Written: OK                                          
Versal> sf write FFFC0000 170000 10000                                          
device 0 offset 0x170000, size 0x10000
SF: 65536 bytes @ 0x170000 Written: OK                                          
Versal> sf write FFFC0000 180000 10000                                          
device 0 offset 0x180000, size 0x10000
SF: 65536 bytes @ 0x180000 Written: OK                                          
Versal> sf write FFFC0000 190000 10000                                          
device 0 offset 0x190000, size 0x10000
SF: 65536 bytes @ 0x190000 Written: OK                                          
Versal> sf write FFFC0000 1A0000 10000                                          
device 0 offset 0x1a0000, size 0x10000
SF: 65536 bytes @ 0x1a0000 Written: OK                                          
Versal> sf write FFFC0000 1B0000 10000                                          
device 0 offset 0x1b0000, size 0x10000
SF: 65536 bytes @ 0x1b0000 Written: OK                                          
Versal> 100%
sf write FFFC0000 1C0000 5D90                                                   
device 0 offset 0x1c0000, size 0x5d90
SF: 23952 bytes @ 0x1c0000 Written: OK                                          
Versal> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 14 sec.

Flash Operation Successful
```

--------------------------------

### Run tutorial script with segmented config

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the tutorial script using both a boot PDI and a PLD PDI.

```bash
python noc_perfmon_tutorial.py --host myserver --pdi boot.pdi --pld-pdi pld.pdi
```

--------------------------------

### Run tutorial script with custom PDI and LTX

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the tutorial script using a custom PDI and LTX file.

```bash
python noc_perfmon_tutorial.py --host myserver --pdi path/to/my_design.pdi --ltx path/to/my_design.ltx
```

--------------------------------

### Install Specific ChipScoPy Version

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Install a specific version of ChipScoPy matching the Vivado installation.

```bash
python -m pip install 'chipscopy==2025.2.*'
```

```bash
python -m pip install chipscopy==2025.2.*
```

--------------------------------

### Start hw_server

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Starts the hw_server process to manage the JTAG connection to the device.

```bash
hw_server
```

--------------------------------

### Start cs_server

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Starts the cs_server process to translate high-level ChipScope debug requests.

```bash
cs_server
```

--------------------------------

### Run tutorial script with custom PDI

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the tutorial script using a custom PDI file.

```bash
python noc_perfmon_tutorial.py --host myserver --pdi path/to/my_design.pdi
```

--------------------------------

### Package Boot Image

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Navigates to the output directory and packages the boot image using U-Boot.

```bash
cd ./images/linux/
petalinux-package boot --u-boot
```

--------------------------------

### Install ChipScoPy Dependencies

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Install additional packages required for plotting and Jupyter Notebook support.

```bash
python -m pip install chipscopy[core-addons]
python -m pip install chipscopy[jupyter]
```

--------------------------------

### Initialize and connect to servers

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Establishes a session with the hardware and ChipScope servers using environment variables or default local addresses.

```python
CS_URL = os.getenv("CS_SERVER_URL", "TCP:localhost:3042")
HW_URL = os.getenv("HW_SERVER_URL", "TCP:localhost:3121")

session = create_session(cs_server_url=CS_URL, hw_server_url=HW_URL)
```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_boot_time/README.md

The directory structure for the VCK190 boot time tutorial, including hardware design files, Vitis software files, and automation scripts.

```text
JTAG_Boot
|___Design.................Contains Design files
  |___Hardware.........................Contains Hardware Design files
    |___constraints....................Contains constraints files
  |___Software/Vitis...................Contains Vitis Design files
    |___bootimage......................Contains bootimage files
    |___src............................Contains Software source files
|___Figures................Contains figures that appear in README.md
  |___add_config_device.png............Add Configuration Memory Device
  |___block.png........................Block Diagram
  |___prog_config_device.png...........Program Configuration Memory Device
  |___time_estimator.png...............Time Estimator
|___Scripts................Contains TCL scripts to generate reference Design, PDI, etc...
  |___project_top.tcl..................Generates the Vivado Design
  |___vck190_bd.tcl....................Generates the VVivado Block Diagram
  |___vck190_vitis.tcl.................Generates the Vitis Design
|___README.md...............Includes tutorial overview, steps to create reference design, and debug resources
```

--------------------------------

### Connect Traffic Generator Start Signal

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/IPI/Module_03_Isochronous_class_with_streaming_traffic/README.md

Connects the traffic generator's start signal to the NoC constant output.

```tcl
connect_bd_net [get_bd_pins perf_axi_tg_0/axi_tg_start] [get_bd_pins xlconstant_0/dout]
```

--------------------------------

### Calculate Transaction Start Address

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_02_Address_Mapping/README.md

Use this formula to calculate the start address of transactions based on base address and offset. Applicable when txn_count is 1.

```text
Start address of the transaction = base_addr + axi_addr_offset
```

--------------------------------

### Set up Design for Simulation using Tcl Commands

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_01_QoS_and_Connectivity/README.md

Automate the simulation setup process using these Tcl commands, including address assignment, design validation, wrapper creation, and simulation settings.

```tcl console
assign_bd_address
validate_bd_design
make_wrapper -files [get_files ./project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse ./project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
set_property -name {xsim.simulate.runtime} -value {2ms} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
```

--------------------------------

### Load Helloworld Secondary Image via dfu-util

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_plm_usb_second/readme.md

Commands to list DFU devices and download the Helloworld secondary binary to the VCK190.

```sh
sudo dfu-util -l
sudo dfu-util -D boot_secondary_helloworld.bin
```

--------------------------------

### Simulation Test Report Example

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Design_Basics/Module_02_Synthesis_and_Implementing_on_VHK158/README.md

This is an example of a test report generated at the end of a simulation run. It details the test status, AXI protocol information, and transaction counts for each test source.

```text
=========================================================
>>>>>> SRC ID 0 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 0 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg.inst.u_top_axi_mst
[INFO] SRC ID = 0 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 0 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 0 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 0 ::: CSV_FILE              = design_1_noc_tg_0_pattern.csv
[INFO] SRC ID = 0 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 0 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 0 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 0 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 1 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 1 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_1.inst.u_top_axi_mst
[INFO] SRC ID = 1 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 1 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 1 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 1 ::: CSV_FILE              = design_1_noc_tg_1_0_pattern.csv
[INFO] SRC ID = 1 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 1 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 1 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 1 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 2 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 2 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_2.inst.u_top_axi_mst
[INFO] SRC ID = 2 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 2 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 2 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 2 ::: CSV_FILE              = design_1_noc_tg_2_0_pattern.csv
[INFO] SRC ID = 2 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 2 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 2 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 2 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 3 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 3 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_3.inst.u_top_axi_mst
[INFO] SRC ID = 3 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 3 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 3 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 3 ::: CSV_FILE              = design_1_noc_tg_3_0_pattern.csv
[INFO] SRC ID = 3 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 3 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 3 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 3 ::: TEST_STATUS           = TEST PASSED
=========================================================

=========================================================
>>>>>> SRC_ID 0 :: AXI_PMON :: BW ANALYSIS >>>>>>
=========================================================
AXI Clock Period = 3334 ps
Min Write Latency = 199 axi clock cycles
Max Write Latency = 1046 axi clock cycles

```

--------------------------------

### Run tutorial script with default CED

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the tutorial script using the default CED design.

```bash
python noc_perfmon_tutorial.py --host myserver
```

--------------------------------

### Navigate to noc_perfmon directory

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Changes the current directory to the location of the NoC performance monitor example.

```bash
cd chipscopy-examples/noc_perfmon
```

--------------------------------

### PLM Performance Log Output

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_boot_time/README.md

Example output showing time breakdown of PL components.

```text
[534.596184]PL supply status good
[574.426137]PL POR B status good
[574.550687]PL House Clean completed
```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_boot_emmc/README.md

An overview of the project directory layout, including hardware design files, software TCL scripts, and configuration files.

```text
vck190_boot_emmc
|___Design.................Contains all the generated hardware and software design for this example
  |___Hardware.................Contains Vivado design 
  |___Software................Contains TCL scripts to generate reference design and PDI, and to read JTAG registers
    |___emmc........Directory that XSA for eMMC project will be written to
    |___sd1................Directory that XSA for SD card project will be written to
    |___user_dtsi...............Contains "system-user.dtsi" for petalinux projects
      |___system-user.dtsi.........................."system-user.dtsi" for petalinux projects
|___Scripts.................Contains TCL scripts to generate reference design, PDI/XSA, and text file with the commands to reconfigure eMMC
  |___cmd_to_reconfigure_emmc....................Contains the text file with the commands to reconfigure eMMC
    |___cmd_to_reconfigure_emmc.txt....................text file with the commands to reconfigure eMMC
  |___project_top_emmc.tcl....................Create vivado project for eMMC
  |___project_top_sd1.tcl.....................Create vivado project for SD card
  |___vck190_emmc_bd.tcl......................Create block design for eMMC
  |___vck190_sd1_bd.tcl..................Create block design for SD card
  |___xsa_generation_for_projects_emmc_and_sd1.tcl..............Top level scripts for eMMC and SD card vivado project, and it also run implement and write XSA for the projects
|___Figures.................Contains images to format eMMC in linux and hardware manager
  |___vck190_image.png...........................Image of vck190 board
  |___fdisk_commands.PNG...........................Image to format eMMC partitions in linux
  |___boot_modes_switch.PNG........................Image to select the boot modes switch
  |___add_config.PNG...............................Image to add configuration memory device
  |___config_mem.PNG...............................Image to add configuration memory device
  |___config_mem_ok.PNG............................Image to program memory device
  |___prog_mem.PNG.................................Image to program memory device
|___README.md...............Includes tutorial overview, steps to create reference design, and instructions to run the design
```

--------------------------------

### Source Vivado Settings Script

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/versal_gen2_boot_modes/ospi_segmented_boot/README.md

Command to initialize the Vivado 2025.2 environment before starting the design process.

```bash
source <Vivado_Install_Path>/2025.2/Vivado/settings64.sh
```

--------------------------------

### Launch the real-time GUI

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Initializes the matplotlib-based GUI to visualize real-time bandwidth measurements.

```python
node_listener = NoCPerfMonNodeListener(...)
plotter = MeasurementPlot(enable_list, mock=False, figsize=(10, 7.5))
node_listener.link_plotter(plotter)
plotter.build_graphs()

while True:
    session.chipscope_view.run_events()
    plotter.fig.canvas.draw()
    if not plotter.alive:
        break
```

--------------------------------

### Run tutorial script skipping programming

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Executes the tutorial script assuming the device is already loaded.

```bash
python noc_perfmon_tutorial.py --host myserver --no-program
```

--------------------------------

### Launch Vivado

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Start the Vivado Design Suite. This command should be run from the project's top directory.

```bash
vivado
```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_tutorials/vck190_post_boot/README.md

Overview of the project file organization, including software source files, Vitis design files, and automation scripts.

```text
Post_Boot
|___Software/Vitis.........Contains Vitis Design files
  |___bootimage......................Contains bootimage files
  |___src............................Contains Software source files
|___Scripts................Contains TCL scripts to generate reference Design, PDI, etc...
  |___postbootrom.tcl................Prints Register Readouts
  |___vitis.tcl......................Generates the Vitis Design
|___README.md..............Includes tutorial overview, steps to create reference design, and debug resources
```

--------------------------------

### Copy the original example script

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_ChipScoPy/README.md

Use this command to copy the base noc_perfmon.py script to a new file for modification.

```bash
cp noc_perfmon.py noc_perfmon_tutorial.py
```

--------------------------------

### Set up PetaLinux Environment

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Source the PetaLinux settings script to prepare the build environment for the specified version.

```bash
$ source <path_to_installed_petalinux>/settings.sh
```
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