### Example Address Calculations

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_02_Address_Mapping/README.md

Illustrates the calculation of start addresses for the first few transactions using the provided formula.

```text
Start address of the first transaction = 40_0000_0000 + 0x0000_0000 = 0x40_0000_0000
Start address of the second transaction = 0x40_0000_0000 + 0x0020_0000 = 0x40_0020_0000
Start address of the third transaction = 0x40_0000_0080 + 0x0040_0000 = 0x40_0040_0000
Start address of the fourth transaction = 0x40_0000_0100 + 0x0060_0000 = 0x40_0060_0000
```

--------------------------------

### Create PetaLinux Project Step-by-Step

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Creates a PetaLinux project using the VCK190 BSP. This is the first step in the manual project setup.

```bash
petalinux-create project -n versal-dfx -s ./xilinx-vck190-v2024.1-05230256.bsp
```

--------------------------------

### Start Hardware Server

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Initiates the Xilinx hardware server, which is necessary for XSDB to connect to the target board.

```shell
xsdb% hw_server
```

--------------------------------

### Prepare and Launch Guided Floorplan

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Disjoint_pblock/README.md

Unplaces the design, sources a Tcl script to guide the floorplan, and then creates the guided floorplan. This is used to resolve routing issues by controlling cell placement within disjoint Pblocks.

```tcl
place_design -unplace
source ./guide_disjoint_floorplan.tcl -notrace
dfx_utils::guided_floorplan::create_guided_floorplan
```

--------------------------------

### Generate Original DCMAC Example Project

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_System_Designs/DCMAC_NoC/README.md

Use this command to generate the original 400G DCMAC example project. The Vivado projects will be built in the 'vivado_eg_ref' sub-directory.

```tcl
source create_dcmac_eg_ref_project.tcl
```

--------------------------------

### Directory Structure Example

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/JTAG_Boot/3QuickStartInstructions.md

This illustrates the expected top-level directory structure for the JTAG Boot tutorial project.

```text
jtag_boot
	|___Design
	    |___pl.xdc
	|___Scripts
	    |___ run.tcl  
	    |___ create_jtag_refdesign.tcl
	    |___ load_jtag_pdi.tcl
	    |___ read_jtag_regs.tcl
```

--------------------------------

### Setup Debug Cores

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/DDRMC_2D_eye_scan/python_code/versal_2d_eye_scan.ipynb

Discovers and sets up the necessary debug cores on the Versal device after programming. This enables debugging and analysis functionalities.

```python
print(f"Discovering debug cores...")
versal_device.discover_and_setup_cores()
print('DONE')
```

--------------------------------

### Set up Design for Simulation using Tcl Commands

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_01_QoS_and_Connectivity/README.md

Automate the simulation setup process using these Tcl commands, including address assignment, design validation, wrapper creation, and simulation settings.

```tcl console
assign_bd_address
validate_bd_design
make_wrapper -files [get_files ./project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top
add_files -norecurse ./project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
set_property -name {xsim.simulate.runtime} -value {2ms} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
```

--------------------------------

### Top-Level TCL Script for Project Setup

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/JTAG_Boot/README.md

This is the main TCL script for project setup, which calls the create_jtag_refdesign.tcl script.

```tcl
run.tcl
```

--------------------------------

### Package Boot Image

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Navigates to the output directory and packages the boot image using U-Boot.

```bash
cd ./images/linux/
petalinux-package boot --u-boot
```

--------------------------------

### Create PetaLinux Project for SD1 Boot

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_boot_emmc/README.md

Create a PetaLinux project for SD1 boot. Ensure the hardware description path is correctly set.

```bash
petalinux-create -t project --template versal --name plnx_vck190_sd1
cd plnx_vck190_sd1/
petalinux-config --get-hw-description=/<directory-to-sd-boot-xsa>
```

--------------------------------

### Loading Secondary Image with dfu-util (A72 Helloworld)

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_plm_usb_second/readme.md

Use these commands to download the A72 helloworld secondary image to the VCK190 board via USB. Ensure the boot_secondary_helloworld.bin file is in the host directory.

```bash
sudo dfu-util -l
sudo dfu-util -D boot_secondary_helloworld.bin
```

--------------------------------

### Connect Traffic Generator Start Signal

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/IPI/Module_03_Isochronous_class_with_streaming_traffic/README.md

Connects the traffic generator's start signal to the NoC constant output.

```tcl
connect_bd_net [get_bd_pins perf_axi_tg_0/axi_tg_start] [get_bd_pins xlconstant_0/dout]
```

--------------------------------

### Calculate Transaction Start Address

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Performance_Tuning/Module_02_Address_Mapping/README.md

Use this formula to calculate the start address of transactions based on base address and offset. Applicable when txn_count is 1.

```text
Start address of the transaction = base_addr + axi_addr_offset
```

--------------------------------

### Create PetaLinux Project for eMMC Boot

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_boot_emmc/README.md

Create a PetaLinux project for eMMC boot. Ensure the hardware description path is correctly set.

```bash
petalinux-create -t project --template versal --name plnx_vck190_emmc
cd plnx_vck190_emmc/
petalinux-config --get-hw-description=/<directory-to-emmc-boot-xsa>
```

--------------------------------

### Simulation Test Report Example

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_HBM/Design_Basics/Module_02_Synthesis_and_Implementing_on_VHK158/README.md

This is an example of a test report generated at the end of a simulation run. It details the test status, AXI protocol information, and transaction counts for each test source.

```text
=========================================================
>>>>>> SRC ID 0 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 0 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg.inst.u_top_axi_mst
[INFO] SRC ID = 0 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 0 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 0 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 0 ::: CSV_FILE              = design_1_noc_tg_0_pattern.csv
[INFO] SRC ID = 0 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 0 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 0 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 0 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 1 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 1 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_1.inst.u_top_axi_mst
[INFO] SRC ID = 1 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 1 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 1 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 1 ::: CSV_FILE              = design_1_noc_tg_1_0_pattern.csv
[INFO] SRC ID = 1 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 1 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 1 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 1 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 2 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 2 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_2.inst.u_top_axi_mst
[INFO] SRC ID = 2 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 2 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 2 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 2 ::: CSV_FILE              = design_1_noc_tg_2_0_pattern.csv
[INFO] SRC ID = 2 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 2 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 2 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 2 ::: TEST_STATUS           = TEST PASSED
=========================================================

Executing Axi4 End Of Simulation checks
=========================================================
>>>>>> SRC ID 3 :: TEST REPORT >>>>>>
=========================================================
[INFO] SRC ID = 3 ::: TG_HIERARCHY          = design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg_3.inst.u_top_axi_mst
[INFO] SRC ID = 3 ::: AXI_PROTOCOL          = AXI4
[INFO] SRC ID = 3 ::: AXI_CLK_PERIOD        = 3334ps, AXI_DATAWIDTH  = 256bit
[INFO] SRC ID = 3 ::: TEST_NAME             = user_defined_pattern
[INFO] SRC ID = 3 ::: CSV_FILE              = design_1_noc_tg_3_0_pattern.csv
[INFO] SRC ID = 3 ::: TOTAL_WRITE_REQ_SENT  = 100, TOTAL_WRITE_RESP_RECEIVED  = 100
[INFO] SRC ID = 3 ::: TOTAL_READ_REQ_SENT   = 100, TOTAL_READ_RESP_RECEIVED   = 100
[INFO] SRC ID = 3 ::: DATA_INTEGRITY_CHECK  = DISABLED
[INFO] SRC ID = 3 ::: TEST_STATUS           = TEST PASSED
=========================================================

=========================================================
>>>>>> SRC_ID 0 :: AXI_PMON :: BW ANALYSIS >>>>>>
=========================================================
AXI Clock Period = 3334 ps
Min Write Latency = 199 axi clock cycles
Max Write Latency = 1046 axi clock cycles

```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_post_boot/README.md

Overview of the directory layout for the Versal Post BootROM tutorial, including locations for software, scripts, and documentation.

```text
Post_Boot
|___Software/Vitis.........Contains Vitis Design files
  |___bootimage......................Contains bootimage files
  |___src............................Contains Software source files
|___Scripts................Contains TCL scripts to generate reference Design, PDI, etc...
  |___postbootrom.tcl................Prints Register Readouts
  |___vitis.tcl......................Generates the Vitis Design
|___README.md..............Includes tutorial overview, steps to create reference design, and debug resources
```

--------------------------------

### Launch Vivado

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Start the Vivado Design Suite. This command should be run from the project's top directory.

```bash
vivado
```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_plm_usb_second/readme.md

Overview of the directory structure for the Versal USB boot tutorial, detailing the organization of hardware, software, boot image format (BIF) files, source code, and scripts.

```text
USB_Boot
|___Design.................Contains Design files
  |___Hardware.........................Contains Hardware Design files
  |___Software...................Contains Software Design files
    |__Petalinux.................Contains Vitis projects
    |__Vitis.....................Contains Petalinux projects
    |__bif............................Contains boot image format files
      |__a72_primary.bif...............For primary PDI
      |__a72_secondary_helloworld.bif..For secondary PDI
      |__a72_secondary_u-boot.bif......For secondary PDI
    |___src............................Contains Software source files
      |__helloworld.c..................Source Code for A72 #0
|___Figures................Contains figures that appear in README.md
  |___block.png........................Block Diagram
|___Scripts................Contains TCL scripts to generate reference Design, PDI, etc...
  |___create_vivado_project.tcl.........Generates the Vivado Design
  |___deisgn_bd.tcl.....................Generates the Vivado Block Diagram
  |___vck190_vitis_app.tcl..............Generates the Vitis application project
  |___vck190_vitis_plm.tcl..............Generates the Vitis plm project
|___README.md...............Includes tutorial overview, steps to create reference design, and debug resources
```

--------------------------------

### Monitor Uartlite Input

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Start monitoring the input of ttyUL0 to observe data received by the Uartlite in the static region.

```bash
cat /dev/ttyUL0 &
```

--------------------------------

### Tutorial Directory Structure

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_boot_ospi/README.md

Details the directory structure for the OSPI Boot tutorial, including locations for design files, Vitis projects, figures, and TCL scripts.

```markdown
OSPI_Boot
|___Design.................Contains Design files
  |___Software/Vitis...................Contains Vitis Design files
                |___bootimage......................Contains bootimage files
                |___src............................Contains Software source files
|___Figures................Contains figures that appear in README.md
  |___Block.PNG........................Block Diagram
  |___Board_interface.PNG...........OSPI Configurations
|___Scripts................Contains TCL scripts to generate reference Design, PDI, etc...
  |___project_top.tcl..................Generates the Vivado Design
  |___vck190_bd.tcl....................Generates the VVivado Block Diagram
  |___vck190_vitis.tcl.................Generates the Vitis Design
|___README.md...............Includes tutorial overview, steps to create reference design, and debug resources
```

--------------------------------

### Enter Sudo Shell

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Starts a sudo shell session, which is required for running commands that need elevated privileges.

```bash
sudo -s
```

--------------------------------

### Set up PetaLinux Environment

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Source the PetaLinux settings script to prepare the build environment for the specified version.

```bash
$ source <path_to_installed_petalinux>/settings.sh
```

--------------------------------

### Launch All Project Creation

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/General/Revision_Control/Foundational/README.md

Execute `make all` to launch the project creation process in both project mode and non-project mode.

```makefile
make all
```

--------------------------------

### Build Images and Package Boot Binary

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Build the PetaLinux images and then package the boot binary, including PLM, PSMFW, U-Boot, and DTB. The --force option overwrites existing files.

```bash
$ petalinux-build
$ petalinux-package --boot --format BIN --plm --psmfw --u-boot --dtb --force
```

--------------------------------

### Get Help for PLM Log Command

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/JTAG_Boot/6CustomBoardBringupResources.md

Display the help information for the 'plm log' command in xsct to understand its options and usage.

```xsct
xsct% plm log -help
```

--------------------------------

### Configure PetaLinux with Hardware Description

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_plm_usb_second/readme.md

Import the generated XSA file into the PetaLinux project for configuration.

```bash
cd vck190_plnx
petalinux-config --get-hw-description=../../../Hardware/vck190_ddr4/ --silentconfig
```

--------------------------------

### Enable DDRMC Main Channel Counters

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/Performance_Measurement_Using_NoC_DDRMC_Performance_Monitors/README.md

Enable the counters for both channels' performance monitors. This starts the counting process for various DDR commands.

```TCL
mwr -force DDRMC_Main1_Mon0_PerfMon 0x3F; 
mwr -force DDRMC_Main1_Mon1_PerfMon 0x3F;
```

--------------------------------

### Get Versal Device

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/DDRMC_2D_eye_scan/python_code/versal_2d_eye_scan.ipynb

Retrieves the Versal device object from the established session. This is necessary for subsequent operations on the device. It checks if any devices were detected.

```python
if len(session.devices) == 0:
    print('
No devices detected')
else:
    versal_device = session.devices[acap_INDEX]
    print(f"Versal device found at device index number {acap_INDEX}")
```

--------------------------------

### Associate Configuration with Implementation

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/UltraScalePlus/DFX/Abstract_Shell_Per_SLR_Compilation/README.md

Link the created DFX configuration ('config_1') with the implementation run ('impl_1'). This ensures the implementation uses the specified DFX setup.

```tcl
#Associate the configuration with the implementation impl_1
set_property PR_CONFIGURATION config_1 [get_runs impl_1]
```

--------------------------------

### Save Block Design to Tcl

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/JTAG_Boot/4BuildingHardwareDesign.md

Saves the current block design configuration to a Tcl file. This allows for the reuse of the IP setup in other projects targeting the same board.

```tcl
write_bd_tcl ./mycustom_bd1.tcl
```

--------------------------------

### Get Available NoC Interfaces

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/RTL/Foundational/README.md

Retrieves a list of all available NoC interfaces within the design. This is a preliminary step for creating NoC constraints for specific topologies.

```bash
join [get_noc_interfaces] \n
```

--------------------------------

### Build and Package PetaLinux for SD1

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_boot_emmc/README.md

Build the PetaLinux project for SD1 and package the boot components.

```bash
petalinux-build
petalinux-package --boot --uboot
```

--------------------------------

### Create PLD Firmware App

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Create a PetaLinux application template for DFX DTG Versal full, enabling it and specifying the source URI for the XSA. Ensure the app name does not contain underscores.

```bash
$ petalinux-create -t apps --template dfx_dtg_versal_full --enable -n <pld-firmware-app-name> --srcuri "../vck190_seg_cfg_pl_demo.xsa"
```

--------------------------------

### Source Vivado and PetaLinux Settings

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/DFX/Linux_based_partial_image_delivery/README.md

Source these scripts to set up your environment for Vivado and PetaLinux 2024.1 commands. Ensure you replace '<xilinx_install>' with your actual installation path.

```bash
source <xilinx_install>/Vivado/2024.1/settings64.sh
source <xilinx_install>/Petalinux/2024.1/settings.sh
```

--------------------------------

### Configure ILA Trigger

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/RTL/Multiphase/README.md

Configure the hw_ila_1 trigger setup by adding the 'S_AXIS_TVALID' net and setting its value. This allows the ILA to capture specific events during hardware validation.

```bash
add the net 'S_AXIS_TVALID' and set the "Value" for the signal to R.
```

--------------------------------

### Program Boot PDI using XSDB

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/Segmented_Configuration/README.md

Downloads and programs the boot PDI file to the Versal device via XSDB.

```bash
xsdb% device program project_1.runs/impl_1/<design>_boot.pdi
```

--------------------------------

### Configure ILA Trigger for RM2

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/RTL/DFX_Foundational/README.md

Add the net ending in _awvalid to the hw_ila_2 Trigger setup and set its Value to 'R' for hardware validation of the second reconfigurable module.

```text
Add the net ending in _awvalid to the hw_ila_2 Trigger setup, and set the Value to 'R'
```

--------------------------------

### PSMFW Loading and Initialization Time

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_boot_time/README.md

This snippet displays the log output for loading and initializing the PSMFW (PSM firmware). It breaks down the time spent on individual partitions and their sizes.

```log
[60.280]---Loading Partition#: 0x2, Id: 0x0
[64.616] 0.520 ms for Partition#: 0x2, Size: 48 Bytes
[68.688]---Loading Partition#: 0x3, Id: 0x0
[72.921] 0.415 ms for Partition#: 0x3, Size: 61072 Bytes
[77.352]---Loading Partition#: 0x4, Id: 0x0
[81.202] 0.032 ms for Partition#: 0x4, Size: 2640 Bytes
[85.932]---Loading Partition#: 0x5, Id: 0x0
[89.787] 0.037 ms for Partition#: 0x5, Size: 3440 Bytes
[94.513]---Loading Partition#: 0x6, Id: 0x0
[98.347] 0.015 ms for Partition#: 0x6, Size: 80 Bytes
```

--------------------------------

### BIF Configuration for USB Boot

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Boot_and_Config/vck190_plm_usb_second/readme.md

Example snippet showing how to add 'boot_device {usb}' to a new BIF file for PLM to recognize USB as a secondary boot device.

```plaintext
new_bif:
{
 ...
 id = xxx
 boot_device {usb}
 image
 {
  ...
 }
}
```

--------------------------------

### Launch Implementation and Write Device Image

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_Design_Flows/RTL/HBM_Foundational/README.md

Launch the implementation runs, including synthesis and implementation, and proceed to the 'write_device_image' step. This command is used to generate the final device image for the design.

```tcl
###Launch Synthesis/Implementation and WDI. 
launch_runs impl_1 -to_step write_device_image -jobs 16
```

--------------------------------

### Create Session and Report Versions

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/Versal/Memory_and_NoC/NoC_DDRMC/DDRMC_2D_eye_scan/python_code/versal_2d_eye_scan.ipynb

Establishes a connection session with the ChipScope server and hardware server, then reports the versions of the connected components. Ensure the CS_URL and HW_URL are correctly configured.

```python
session = create_session(cs_server_url=CS_URL, hw_server_url=HW_URL, bypass_version_check=True)
report_versions(session)
```

--------------------------------

### Get VLNV Property of a Block Design Cell

Source: https://github.com/xilinx/vivado-design-tutorials/blob/2025.2/UltraScalePlus/DFX/Abstract_Shell_Per_SLR_Compilation/README.md

Retrieve the VLNV (Vendor, Library, Name, Version) property of a specific block design cell using Tcl.

```tcl
get_property VLNV [get_bd_cells /static_region/axi_bram_ctrl_2]
xilinx.com:ip:axi_bram_ctrl:4.1
```