NEORV32

https://github.com/stnolting/neorv32
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NEORV32 is a customizable microcontroller-like system on chip built around a RISC-V CPU written in...
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### Check NEORV32 Toolchain Setup

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/sw_toolchain_setup.adoc

Navigate to an example project directory and run `make check` to verify that all necessary tools for generating NEORV32 executables are correctly configured and accessible.

```bash
neorv32/sw/example/demo_blink_led$ make check
```

--------------------------------

### Build and Simulate Hello World Example

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/simulating_the_processor.adoc

Run this command in the 'sw/example/hello_world' directory to clean, install, and simulate the application. The USER_FLAGS+=-DUART0_SIM_MODE flag enables simulation mode for UART0, directing output to the simulator console.

```bash
neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE clean install sim
```

--------------------------------

### NEORV32 Test Setup Ports

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/general_hw_setup.adoc

Example ports for the `neorv32_test_setup_bootloader.vhd` entity, including clock, reset, GPIO, and UART signals.

```vhdl
port (
  -- Global control --
  clk_i       : in  std_ulogic; -- global clock, rising edge
  rstn_i      : in  std_ulogic; -- global reset, low-active, async
  -- GPIO --
  gpio_o      : out std_ulogic_vector(7 downto 0); -- parallel output
  -- UART0 --
  uart0_txd_o : out std_ulogic; -- UART0 send data
  uart0_rxd_i : in  std_ulogic  -- UART0 receive data
);
```

--------------------------------

### System Configuration Information Example

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_bootloader.adoc

Example output of the 'i' command in the NEORV32 bootloader, showing hardware version, clock frequency, and CPU configuration details.

```text
CMD:> i
HWV:  0x01120101 <1>
CLK:  0x05f5e100 <2>
MISA: 0x40901107 <3>
XISA: 0x00000000:0x0fc06fd3 <4>
SOC:  0x38efc87b <5>
MISC: 0x0a010d00 <6>
CMD:>
```

--------------------------------

### Generate and Install IMEM Initialization File

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/installing_an_executable.adoc

Use the `make` command to clean, regenerate the image, and install the application firmware into the IMEM initialization file. This process also shows the memory utilization of the compiled application.

```bash
neorv32/sw/example/demo_blink_led$ make clean_all image install
Memory utilization:
   text    data     bss     dec     hex filename
  22192    1352    4216   27760    6c70 main.elf
Compiling image generator...
Generating neorv32_imem_image.vhd
Installing application image to ../../../rtl/core/neorv32_imem_image.vhd
```

--------------------------------

### Setup NEORV32 Runtime Environment and Interrupts

Source: https://context7.com/stnolting/neorv32/llms.txt

Initializes the runtime environment for trap handling and installs a custom handler for machine timer interrupts. Ensure global interrupts are enabled.

```c
#include <neorv32.h>

// Custom interrupt handler function
void my_timer_handler(void) {
    // Handle timer interrupt
    neorv32_clint_mtimecmp_set(neorv32_clint_mtimecmp_get() + neorv32_sysinfo_get_clk());
    neorv32_uart0_puts("Timer interrupt!\n");
}

int main() {
    // Initialize runtime environment - captures all exceptions
    neorv32_rte_setup();

    // Install custom handler for machine timer interrupt
    neorv32_rte_handler_install(TRAP_CODE_MTI, my_timer_handler);

    // Enable timer interrupt and global interrupts
    neorv32_cpu_csr_set(CSR_MIE, 1 << CSR_MIE_MTIE);
    neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE);

    // Uninstall handler when no longer needed
    neorv32_rte_handler_uninstall(TRAP_CODE_MTI);

    return 0;
}
```

--------------------------------

### Start NEORV32 Simulation

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/litex_support.adoc

Use this command to initiate a simulation of the NEORV32 processor with LiteX. This command starts the LiteX simulator with the NEORV32 as the target CPU.

```bash
$ litex_sim --cpu-type=neorv32
```

--------------------------------

### Using Tracer Commands in GDB

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/soc_tracer.adoc

Example of compiling, loading, running, sourcing the tracer script, and retrieving trace data using GDB.

```gdb
(gdb) make clean elf <1>
...
(gdb) load <2>
...
(gdb) c <3>
...
(gdb) source neorv32_tracer.gdb <4>
(gdb) tracer_get <5>
[0] SRC: 0x3b0 -> DST: 0x2cc <TRACE_START> 
Line 128 of "main.c" starts at address 0x3b0 <main+212> and ends at 0x3b4 <main+216>. 
Line 68 of "main.c" starts at address 0x2cc <test_code> and ends at 0x2d0 <test_code+4>. 
...
```

--------------------------------

### Start GDB Debug Session

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/using_ocd.adoc

Use this makefile target to start a pre-configured GDB debug session. It assumes 'main.elf' is the executable and connects to localhost:3333.

```bash
make gdb
```

--------------------------------

### Setup NEORV32 Runtime Environment

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_rte.adoc

Call this function at the beginning of your main function to initialize the NEORV32 runtime environment. For SMP systems, call this on each core that uses the RTE.

```c
int main() {

  neorv32_rte_setup(); // setup NEORV32 runtime environment

  ...

```

--------------------------------

### Configure JTAG Interface and Target

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/on_chip_debugger.adoc

These commands source configuration scripts to set up the JTAG interface, target, authentication, and start the NEORV32 processor. Replace custom adapter setups as needed.

```tcl
source [file join $PATH lib/interface.cfg]
source [file join $PATH lib/target.cfg]
source [file join $PATH lib/authenticate.cfg]
source [file join $PATH lib/start.cfg]
```

--------------------------------

### Simulate NEORV32 Verilog with Verilator

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/neorv32_in_verilog.adoc

Start the simulation of the Verilog design using Verilator. The simulation checks for the bootloader intro string.

```bash
neorv32/rtl/verilog$ make SIMULATOR=verilator sim
```

--------------------------------

### Process File-List Files in TCL Script

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/overview.adoc

This example demonstrates how to process the NEORV32 file-list files using a TCL script. It reads the file content and substitutes the path placeholder with the actual NEORV32 installation path.

```tcl
set file_list_file [read [open "$neorv32_home/rtl/file_list_soc.f" r]]
set file_list [string map [list "NEORV32_RTL_PATH_PLACEHOLDER" "$neorv32_home/rtl"] $file_list_file]
puts "NEORV32 source files:"
puts $file_list
```

--------------------------------

### Build Documentation Using Docker

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/building_the_documentation.adoc

If asciidoctor or asciidoctor-pdf are not installed, use the 'container' target with the makefile to build all documentation via a Docker container.

```bash
make container
```

--------------------------------

### Start NEORV32 Program Execution

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/using_ocd.adoc

Initiates the execution of the uploaded program on the NEORV32 processor. You can halt execution at any time using CTRL+c to inspect variables, set breakpoints, or step through the code.

```bash
(gdb) c <5>
```

--------------------------------

### Setup and Use Watchdog Timer (WDT)

Source: https://context7.com/stnolting/neorv32/llms.txt

Initializes the WDT, checks the cause of the last reset, and sets a timeout period. The watchdog must be fed periodically to prevent a system reset. Ensure the WDT is available before use.

```c
#include <neorv32.h>

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    if (neorv32_wdt_available() == 0) {
        return -1;
    }

    // Check cause of last reset
    int cause = neorv32_wdt_get_cause();
    switch (cause) {
        case WDT_RCAUSE_EXT:
            neorv32_uart0_puts("Last reset: External\n");
            break;
        case WDT_RCAUSE_OCD:
            neorv32_uart0_puts("Last reset: Debugger\n");
            break;
        case WDT_RCAUSE_TMO:
            neorv32_uart0_puts("Last reset: WDT Timeout\n");
            break;
        case WDT_RCAUSE_ACC:
            neorv32_uart0_puts("Last reset: WDT Invalid Access\n");
            break;
    }

    // Calculate timeout: WDT runs at f_main/4096
    // For 8 second timeout:
    uint32_t timeout = 8 * (neorv32_sysinfo_get_clk() / 4096);

    // Setup watchdog: timeout value, no lock (0)
    // Lock=1 prevents further configuration changes
    neorv32_wdt_setup(timeout, 0);

    // Main application loop
    while (1) {
        // Application processing...
        neorv32_aux_delay_ms(neorv32_sysinfo_get_clk(), 500);

        // Feed watchdog to prevent reset (use password)
        neorv32_wdt_feed(WDT_PASSWORD);
        neorv32_uart0_puts("WDT fed.\n");
    }

    // Force immediate hardware reset
    // neorv32_wdt_force_hwreset();

    // Disable watchdog (only if not locked)
    // neorv32_wdt_disable();

    return 0;
}

```

--------------------------------

### Simulate NEORV32 Verilog with Icarus Verilog

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/neorv32_in_verilog.adoc

Start the simulation of the Verilog design using Icarus Verilog. The simulation checks for the bootloader intro string.

```bash
neorv32/rtl/verilog$ make SIMULATOR=iverilog sim
```

--------------------------------

### Install Custom Trap Handlers

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_rte.adoc

Installs custom handlers for machine timer interrupts, machine environment calls, and SLINK receive interrupts. Ensure the handler functions are defined elsewhere.

```c
neorv32_rte_handler_install(RTE_TRAP_MTI, machine_timer_irq_handler); // handler for machine timer interrupt
neorv32_rte_handler_install(RTE_TRAP_MENV_CALL, environment_call_handler); // handler for machine environment call exception
neorv32_rte_handler_install(SLINK_RX_RTE_ID, slink_rx_handler); // handler for SLINK receive interrupt
```

--------------------------------

### Configure Application Makefile

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software.adoc

Override default build configurations such as CPU ISA, GCC prefix, optimization level, and debug symbols. This example also shows how to define processor memory sizes and base addresses, and heap size using linker flags.

```makefile
# Override the default CPU ISA
MARCH = rv32imc_zicsr_zifencei

# Override the default RISC-V GCC prefix
RISCV_PREFIX ?= riscv-none-elf-

# Override default optimization goal
EFFORT = -Os

# Add extended debug symbols for Eclipse
USER_FLAGS += -ggdb -gdwarf-3

# Additional sources
APP_SRC += $(wildcard ./*.c)
APP_INC += -I .

# Adjust processor IMEM size and base address
USER_FLAGS += -Wl,--defsym,__neorv32_rom_size=16k
USER_FLAGS += -Wl,--defsym,__neorv32_rom_base=0x00000000

# Adjust processor DMEM size and base address
USER_FLAGS += -Wl,--defsym,__neorv32_ram_size=8k
USER_FLAGS += -Wl,--defsym,__neorv32_ram_base=0x80000000

# Adjust maximum heap size
USER_FLAGS += -Wl,--defsym,__neorv32_heap_size=2k

# Set path to NEORV32 root directory
NEORV32_HOME ?= ../../..
```

--------------------------------

### Start GHDL Simulation from Application Makefile

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/simulating_the_processor.adoc

Initiate the GHDL simulation directly from an application's Makefile. This command also allows setting user flags, such as enabling UART0 simulation mode.

```bash
sw/example/demo_blink_led$ make USER_FLAGS+=-DUART0_SIM_MODE clean_all install sim
```

--------------------------------

### Compile and Run Arith Instruction Test

Source: https://github.com/stnolting/neorv32/blob/main/sw/example/performance_tests/I/README.md

Example command to compile and run the Arith instruction performance test suite using the NEORV32 build system.

```bash
make USER_FLAGS+=-DRUN_CHECK USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-Drv32I_arith clean_all exe
make sim
```

--------------------------------

### Process File-List Files in Makefile

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/overview.adoc

This example shows how to process the NEORV32 file-list files within a Makefile. It demonstrates setting the NEORV32 home directory, loading the file list content, and substituting path placeholders.

```makefile
NEORV32_HOME = path/to/neorv32 <1>
NEORV32_SOC_FILE = $(shell cat $(NEORV32_HOME)/rtl/file_list_soc.f) <2>
NEORV32_SOC_SRCS = $(subst NEORV32_RTL_PATH_PLACEHOLDER, $(NEORV32_HOME)/rtl, $(NEORV32_SOC_FILE)) <3>
```

--------------------------------

### Default Authentication Process Example

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/on_chip_debugger.adoc

This Tcl script demonstrates the default authentication process using openOCD, including reading a challenge, computing a response, and sending it back to the authenticator module.

```tcl
# read challenge
set CHALLENGE [authenticator_read]
# compute response (default authenticator module)
set RESPONSE [expr {$CHALLENGE | 1}]
# send response
authenticator_write $RESPONSE
```

--------------------------------

### VHDL Tristate Driver Example for TWD Module

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/soc_twd.adoc

Example VHDL code demonstrating how to implement the tristate driver for the SDA line required by the TWD module. The SCL line only requires an input.

```VHDL
-- IO ports / bus lines --
sda_io : inout std_logic;
scl_io : in    std_logic;

-- tristate driver --
sda_io <= '0' when (twd_sda_o = '0') else 'Z';

-- sense --
twd_sda_i <= std_ulogic(sda_io);
twd_scl_i <= std_ulogic(scl_io);
```

--------------------------------

### Exemplary Bootloader Executable Header Dump

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_bootloader.adoc

An example of a raw binary dump of the bootloader executable header, showing the signature, base address, size, and checksum.

```bash
neorv32/sw/example/processor_check$ xxd -e -l 32 neorv32_exe.bin
00000000: 214f454e 00000000 00007078 2af7f9c6   NEO!....xp.....*

```

--------------------------------

### Start GDB on Linux (Ubuntu on Windows)

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/using_ocd.adoc

Launch the RISC-V GNU debugger to begin the debugging session. This command should be run from the application's directory after compilation.

```bash
.../neorv32/sw/example/demo_blink_led$ riscv32-unknown-elf-gdb
GNU gdb (GDB) 10.1
Copyright (C) 2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
```

--------------------------------

### TWI VHDL Tristate Driver Example

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/soc_twi.adoc

Example VHDL code for implementing tristate drivers for the SDA and SCL lines required by the TWI module. Ensure `sda_io` and `scl_io` are correctly connected to the actual I2C bus lines.

```vhdl
sda_io    <= '0' when (twi_sda_o = '0') else 'Z'; -- drive
scl_io    <= '0' when (twi_scl_o = '0') else 'Z'; -- drive
twi_sda_i <= std_ulogic(sda_io); -- sense
twi_scl_i <= std_ulogic(scl_io); -- sense
```

--------------------------------

### Icarus Verilog Simulation Output

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/neorv32_in_verilog.adoc

Example output from an Icarus Verilog simulation, showing successful completion after receiving the NEORV32 bootloader string.

```text
Running simulation with Icarus Verilog

NEORV32 Verilog testbench



NEORV32
Simulation successful!
testbench.v:83: $finish called at 81865950 (100ps)

```

--------------------------------

### Configure and Use SPI Master Controller

Source: https://context7.com/stnolting/neorv32/llms.txt

Sets up the SPI master controller with specified parameters and demonstrates basic data transfer operations, including single byte, non-blocking, and multi-byte transfers. Ensure SPI is available before setup.

```c
#include <neorv32.h>

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    if (neorv32_spi_available() == 0) {
        neorv32_uart0_puts("SPI not available!\n");
        return -1;
    }

    // Setup SPI: prescaler=CLK_PRSC_64, divider=0, phase=0, polarity=0
    neorv32_spi_setup(CLK_PRSC_64, 0, 0, 0);

    // Get actual SPI clock speed
    uint32_t spi_clk = neorv32_spi_get_clock_speed();
    neorv32_uart0_printf("SPI clock: %u Hz\n", spi_clk);

    // Enable chip select line 0
    neorv32_spi_cs_en(0);

    // Transfer single byte (write and read simultaneously)
    uint8_t tx_data = 0xAB;
    uint8_t rx_data = neorv32_spi_transfer(tx_data);

    // Non-blocking transfer
    neorv32_spi_put_nonblocking(0xCD);
    while (neorv32_spi_busy()); // Wait for completion
    rx_data = neorv32_spi_get_nonblocking();

    // Multiple byte transfer
    uint8_t buffer[4] = {0x01, 0x02, 0x03, 0x04};
    for (int i = 0; i < 4; i++) {
        buffer[i] = neorv32_spi_transfer(buffer[i]);
    }

    // Disable chip select
    neorv32_spi_cs_dis();

    // Check FIFO status
    int fifo_depth = neorv32_spi_get_fifo_depth();
    int tx_empty = neorv32_spi_tx_empty();
    int rx_avail = neorv32_spi_rx_avail();

    return 0;
}

```

--------------------------------

### Install Application-Specific Trap Handler

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_rte.adoc

Use this function to install a custom trap handler. The `id` specifies the trap to handle, and `handler` is a pointer to your custom function. Custom handlers must not use the `((interrupt))` attribute.

```c
int neorv32_rte_handler_install(uint8_t id, void (*handler)(void));
```

--------------------------------

### Connect via OpenOCD on Windows

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/using_ocd.adoc

Start OpenOCD with the provided configuration file to enable JTAG debugging. Ensure the interface configuration is adapted to your JTAG adapter and OS.

```bash
neorv32\sw\openocd>openocd.exe -f openocd_neorv32.cfg
xPack Open On-Chip Debugger 0.12.0+dev-01850-geb6f2745b-dirty (2025-02-07-10:08)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
*****************************************
NEORV32 single-core openOCD configuration
*****************************************
Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND
Info : clock speed 2000 kHz
Info : JTAG tap: neorv32.cpu tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
Error: Debugger is not authenticated to target Debug Module. (dmstatus=0x3). Use `riscv authdata_read` and `riscv authdata_write` commands to authenticate.
Info : [neorv32.cpu] Examination succeed
Info : [neorv32.cpu] starting gdb server on 3333
Info : Listening on port 3333 for gdb connections
Info : authdata_write resulted in successful authentication
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 2 harts
Info :  hart 0: XLEN=32, misa=0x40901107
Authentication passed.
Info : JTAG tap: neorv32.cpu tap/device found: 0x00000001 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
Target RESET and HALTED. Ready for remote connections.
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
```

--------------------------------

### NEORV32 Test Setup Entity Generics

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/general_hw_setup.adoc

Configure these generics to match your FPGA and board specifications, including clock frequency and memory sizes.

```vhdl
generic (
  -- adapt these for your setup --
  CLOCK_FREQUENCY : natural := 100000000; <1>
  IMEM_SIZE       : natural := 16*1024;   <2>
  DMEM_SIZE       : natural := 8*1024     <3>
);
```

--------------------------------

### Get NEORV32 Machine Info

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/micropython_port.adoc

The `machine.info()` function provides details about the NEORV32 processor, such as version, clock speed, and MISA/MXISA/SoC values.

```python
>>> import machine
>>> machine.info()
NEORV32 version 1.11.2.9
Clock: 150000000 Hz
MISA:  0x40901105
MXISA: 0x66006cd3
SoC:   0x480ba97b
```

--------------------------------

### Configure and Control PWM Channels

Source: https://context7.com/stnolting/neorv32/llms.txt

Set up PWM channels with specific resolution, polarity, and alignment. Enables channels and sets duty cycles for PWM output. Includes an example for LED fading.

```c
#include <neorv32.h>

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    if (neorv32_pwm_available() == 0) {
        return -1;
    }

    int num_channels = neorv32_pmw_get_num_channels();
    neorv32_uart0_printf("PWM channels: %d\n", num_channels);

    // Set global clock prescaler
    neorv32_pwm_set_clock(CLK_PRSC_64);

    // Configure channel 0: top value, polarity, mode
    // top=255 gives 8-bit resolution
    // polarity: 0=active high, 1=active low
    // mode: 0=edge-aligned, 1=center-aligned
    neorv32_pwm_ch_setup(0, 255, 0, 0);

    // Configure channel 1 with different settings
    neorv32_pwm_ch_setup(1, 1000, 0, 1); // 10-bit resolution, center-aligned

    // Enable channels
    neorv32_pwm_ch_enable_single(0);
    neorv32_pwm_ch_enable_single(1);

    // Or enable multiple channels with mask
    neorv32_pwm_ch_enable_mask(0x03); // Enable channels 0 and 1

    // Set duty cycle (0 to TOP value)
    neorv32_pwm_ch_set_duty(0, 128);  // 50% duty on channel 0
    neorv32_pwm_ch_set_duty(1, 250);  // 25% duty on channel 1

    // LED fading example
    int brightness = 0;
    int direction = 1;
    while (1) {
        neorv32_pwm_ch_set_duty(0, brightness);

        brightness += direction;
        if (brightness >= 255) direction = -1;
        if (brightness <= 0) direction = 1;

        neorv32_aux_delay_ms(neorv32_sysinfo_get_clk(), 10);
    }

    // Disable channels
    neorv32_pwm_ch_disable_single(0);
    neorv32_pwm_ch_disable_mask(0xFFFFFFFF); // Disable all

    return 0;
}

```

--------------------------------

### Example Zfinx Performance Test Output

Source: https://github.com/stnolting/neorv32/blob/main/sw/example/performance_tests/Zfinx/README.md

This output shows the cycle counts for various Zfinx instructions, including total cycles and cycles for specific paths like 'exception', 'min', and 'max'. It also provides the average instruction execution cycles.

```text
<<< Zfinx performance test >>>

perform: for (i=0;i<1,i++) {256 instructions}

fadd.s tot. 3507 cyc

total 3507 cyc

fadd.s rd,rs1,rs2 exception path inst. 13 cyc

fadd.s tot. 5123 cyc

total 8630 cyc

fadd.s rd,rs1,rs2 min. inst. 20 cyc

fadd.s tot. 11779 cyc

total 20409 cyc

fadd.s rd,rs1,rs2 max. inst. 46 cyc

fsub.s tot. 3507 cyc

total 23916 cyc

fsub.s rd,rs1,rs2 exception path inst. 13 cyc

fsub.s tot. 5412 cyc

total 29328 cyc

fsub.s rd,rs1,rs2 min. inst. 21 cyc

fsub.s tot. 12291 cyc

total 41619 cyc

fsub.s rd,rs1,rs2 max. inst. 48 cyc

fmul.s tot. 3059 cyc

total 44678 cyc

fmul.s rd,rs1,rs2 exception path inst. 11 cyc

fmul.s tot. 4403 cyc

total 49081 cyc

fmul.s rd,rs1,rs2 inst. 17 cyc

instructions tested: 8

total 49081 cycles

avg. inst. execute cyles 23.965
```

--------------------------------

### Customizing Memory Sizes in Makefile

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software.adoc

Example of overriding default memory sizes for IMEM (ROM) and DMEM (RAM) using USER_FLAGS in a makefile.

```makefile
USER_FLAGS += "-Wl,--defsym,__neorv32_rom_size=64k -Wl,--defsym,__neorv32_ram_size=32k"
```

--------------------------------

### CFS Software Access Example

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/soc_cfs.adoc

Demonstrates how to access the CFS memory-mapped registers from C code using the provided aliases. Ensure the NEORV32_CFS structure is correctly defined and accessible.

```c
// C-code CFS usage example
NEORV32_CFS->REG[0] = (uint32_t)some_data_array(i); // write to CFS register 0
int temp = (int)NEORV32_CFS->REG[20]; // read from CFS register 20

```

--------------------------------

### Configure and Use TWI (I2C) Master Controller

Source: https://context7.com/stnolting/neorv32/llms.txt

Initializes the TWI master controller and demonstrates scanning the I2C bus for devices, writing data to a device, and reading data from a device. Clock stretching is enabled during setup.

```c
#include <neorv32.h>

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    if (neorv32_twi_available() == 0) {
        return -1;
    }

    // Setup TWI: prescaler, divider, clock stretching enabled
    neorv32_twi_setup(CLK_PRSC_2048, 15, 1);

    // Scan for I2C devices on the bus
    neorv32_uart0_puts("Scanning I2C bus...\n");
    for (int addr = 0; addr < 128; addr++) {
        neorv32_twi_generate_start();
        uint8_t data = (addr << 1) | 1; // Read address
        int ack = neorv32_twi_transfer(&data, 0);
        neorv32_twi_generate_stop();

        if (ack == 0) {
            neorv32_uart0_printf("Device found at 0x%x\n", addr);
        }
    }

    // Write to I2C device at address 0x50
    uint8_t dev_addr = 0x50;
    neorv32_twi_generate_start();

    // Send device address with write bit
    uint8_t addr_byte = (dev_addr << 1) | 0;
    neorv32_twi_transfer(&addr_byte, 0);

    // Send register address
    uint8_t reg = 0x00;
    neorv32_twi_transfer(&reg, 0);

    // Send data byte
    uint8_t tx_data = 0xAB;
    neorv32_twi_transfer(&tx_data, 0);

    neorv32_twi_generate_stop();

    // Read from I2C device
    neorv32_twi_generate_start();
    addr_byte = (dev_addr << 1) | 1; // Read bit set
    neorv32_twi_transfer(&addr_byte, 0);

    uint8_t rx_data = 0xFF;
    neorv32_twi_transfer(&rx_data, 1); // 1 = master ACK
    neorv32_twi_generate_stop();

    // Check bus lines
    int scl = neorv32_twi_sense_scl();
    int sda = neorv32_twi_sense_sda();

    return 0;
}

```

--------------------------------

### LiteX BIOS Output

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/litex_support.adoc

This is the typical output from the LiteX BIOS when starting a simulation. It displays system information, boot status, and available console commands.

```text
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jul 19 2022 12:21:36
 BIOS CRC passed (6f76f1e8)

 LiteX git sha1: 0654279a

--=============== SoC ==================
CPU:            NEORV32-standard @ 1MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128KiB
SRAM:           8KiB


--============== Boot ==================
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================

litex> help

LiteX BIOS, available commands:

flush_cpu_dcache         - Flush CPU data cache
crc                      - Compute CRC32 of a part of the address space
ident                    - Identifier of the system
help                     - Print this help

serialboot               - Boot from Serial (SFL)
reboot                   - Reboot
boot                     - Boot from Memory

mem_cmp                  - Compare memory content
mem_speed                - Test memory speed
mem_test                 - Test memory access
mem_copy                 - Copy address space
mem_write                - Write address space
mem_read                 - Read address space
mem_list                 - List available memory regions


litex>
```

--------------------------------

### Define and Use CFU Instructions in C

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/cpu_cfu.adoc

Example of defining and using custom instructions with the NEORV32 processor's CFU in C. It shows how to pass runtime data via register addresses.

```c
uint32_t foo = 12345;
uint32_t res = RISCV_INSTR_I_TYPE(RISCV_OPCODE_CUSTOM1, 0b001, foo, 0xABC);
res = RISCV_INSTR_R_TYPE(RISCV_OPCODE_CUSTOM0, 0b101, 0b1100110, res, foo);
```

--------------------------------

### RTE Context Access Functions Examples

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_rte.adoc

Demonstrates reading register 'x9' into a temporary variable and writing that variable's content to register 'x28'. These functions are useful for emulating unsupported CPU features within trap handlers.

```c
// Examples
uint32_t tmp = neorv32_rte_context_get(9); // read register 'x9'
neorv32_rte_context_put(28, tmp); // write 'tmp' to register 'x28'
```

--------------------------------

### Configure CLINT Timer and Software Interrupts

Source: https://context7.com/stnolting/neorv32/llms.txt

Sets up the Core-Local Interruptor (CLINT) for machine timer (MTIMER) and software interrupts. It includes installing interrupt handlers, setting Unix time, and triggering a software interrupt. Ensure CLINT is available before proceeding.

```c
#include <neorv32.h>

void timer_irq_handler(void) {
    // Schedule next interrupt in 1 second
    neorv32_clint_mtimecmp_set(neorv32_clint_mtimecmp_get() + neorv32_sysinfo_get_clk());
    neorv32_gpio_pin_toggle(0); // Toggle LED
}

void software_irq_handler(void) {
    neorv32_clint_msi_clr(neorv32_cpu_csr_read(CSR_MHARTID));
    neorv32_uart0_puts("Software interrupt!\n");
}

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    if (neorv32_clint_available() == 0) {
        return -1;
    }

    // Set Unix time
    date_t date = {
        .year = 2025, .month = 1, .day = 15,
        .hours = 12, .minutes = 30, .seconds = 0
    };
    neorv32_clint_unixtime_set(neorv32_aux_date2unixtime(&date));

    // Get current Unix time
    uint64_t unix_time = neorv32_clint_unixtime_get();
    neorv32_uart0_printf("Unix time: %u\n", (uint32_t)unix_time);

    // Convert back to date
    neorv32_aux_unixtime2date(unix_time, &date);
    neorv32_uart0_printf("Date: %u/%u/%u\n", date.day, date.month, date.year);

    // Install interrupt handlers
    neorv32_rte_handler_install(TRAP_CODE_MTI, timer_irq_handler);
    neorv32_rte_handler_install(TRAP_CODE_MSI, software_irq_handler);

    // Configure timer compare (first interrupt in 1 second)
    neorv32_clint_mtimecmp_set(neorv32_clint_time_get() + neorv32_sysinfo_get_clk());

    // Enable interrupts
    neorv32_cpu_csr_set(CSR_MIE, (1 << CSR_MIE_MTIE) | (1 << CSR_MIE_MSIE));
    neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE);

    // Trigger software interrupt
    neorv32_clint_msi_set(neorv32_cpu_csr_read(CSR_MHARTID));

    // Sleep until interrupt
    while (1) {
        neorv32_cpu_sleep();
    }

    return 0;
}

```

--------------------------------

### Show Makefile Help

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/building_the_documentation.adoc

Run the 'help' target in the makefile to see all available build options and their outputs.

```bash
neorv32/docs$ make help
```

--------------------------------

### NEORV32 Bootloader Help Menu

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_bootloader.adoc

Displays the available commands in the NEORV32 bootloader, including options for system information, uploading firmware, and managing flash memory.

```text
CMD:> h
Available CMDs:
h: Help                <1>
i: System info         <2>
r: Restart             <3>
u: Upload via UART     <4>
t: TWI flash - load    <5>
w: TWI flash - program <6>
l: SPI flash - load    <7>
s: SPI flash - program <8>
c: SD card - load      <9>
e: Start executable    <10>
x: Exit                <11>
CMD:>
```

--------------------------------

### Verify Yosys and GHDL Plugin Installation

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/litex_support.adoc

Run this command in your terminal to check if yosys is installed and recognizes the GHDL plugin. This is crucial for VHDL synthesis within the LiteX build flow.

```bash
yosys -H
```

--------------------------------

### Compile and Run Zfinx Performance Tests

Source: https://github.com/stnolting/neorv32/blob/main/sw/example/performance_tests/Zfinx/README.md

Use these make commands to clean, build, and simulate the Zfinx instruction performance tests. Ensure USER_FLAGS are set appropriately for your desired test suite.

```bash
make USER_FLAGS+=-DRUN_CHECK USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-Drv32Zfinx_arith clean_all exe
make sim
```

--------------------------------

### Machine Counter Setup CSRs

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/cpu_csr.adoc

Configuration registers for machine-level performance counters.

```APIDOC
## `mcountinhibit`

### Description
Machine counter-inhibit register. Used to halt specific counter CSRs.

### Method
N/A (CSR Register)

### Endpoint
N/A

### Parameters
#### Path Parameters
N/A

#### Query Parameters
N/A

#### Request Body
N/A

### Request Example
N/A

### Response
#### Success Response (200)
N/A

#### Response Example
N/A

## `mcountinhibit` CSR Bits

### Description
Defines which bits control the halting of specific counters.

### Method
N/A (CSR Register Bits)

### Endpoint
N/A

### Parameters
N/A

### Request Example
N/A

### Response
N/A

## `mcyclecfg[h]`

### Description
Machine cycle counter privilege mode filtering. Controls when the cycle counter is halted based on the CPU's privilege mode. `mcyclecfg` is hardwired to all-zero.

### Method
N/A (CSR Register)

### Endpoint
N/A

### Parameters
N/A

### Request Example
N/A

### Response
N/A

## `mcyclecfgh` CSR Bits

### Description
Defines which bits control the halting of the `mcycle[h]` counter based on privilege mode.

### Method
N/A (CSR Register Bits)

### Endpoint
N/A

### Parameters
N/A

### Request Example
N/A

### Response
N/A

## `minstretcfg[h]`

### Description
Machine instruction-retired counter privilege mode filtering. Controls when the instruction-retired counter is halted based on the CPU's privilege mode. `minstretcfg` is hardwired to all-zero.

### Method
N/A (CSR Register)

### Endpoint
N/A

### Parameters
N/A

### Request Example
N/A

### Response
N/A

## `minstretcfgh` CSR Bits

### Description
Defines which bits control the halting of the `minstret[h]` counter based on privilege mode.

### Method
N/A (CSR Register Bits)

### Endpoint
N/A

### Parameters
N/A

### Request Example
N/A

### Response
N/A
```

--------------------------------

### RTE Default Trap Handler UART0 Output Examples

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/software_rte.adoc

Examples of messages output by the default RTE trap handler to UART0, providing debug information for various trap types. These messages indicate the trap cause, program counter (MEPC), instruction details (MTINST), and trap value (MTVAL).

```text
<NEORV32-RTE-PANIC> [cpu0|M] Illegal instruction MEPC=0x000002d6 MTINST=0x000000FF MTVAL=0x00000000 </NEORV32-RTE-PANIC> <1>
<NEORV32-RTE-PANIC> [cpu0|U] Illegal instruction MEPC=0x00000302 MTINST=0x00000000 MTVAL=0x00000000 </NEORV32-RTE-PANIC> <2>
<NEORV32-RTE-PANIC> [cpu0|U] Load address misaligned MEPC=0x00000440 MTINST=0x01052603 MTVAL=0x80000101 </NEORV32-RTE-PANIC> <3>
<NEORV32-RTE-PANIC> [cpu1|M] FIRQ channel 0x00000003 MEPC=0x00000820 MTINST=0x00000000 MTVAL=0x00000000 </NEORV32-RTE-PANIC> <4>
<NEORV32-RTE-PANIC> [cpu1|M] Instruction access fault MEPC=0x90000000 MTINST=0x42078b63 MTVAL=0x00000000 FATAL! HALTING CPU </NEORV32-RTE-PANIC>
 <5>
```

--------------------------------

### Machine Trap Setup CSRs

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/cpu_csr.adoc

CSRs for configuring machine-mode trap and interrupt behavior.

```APIDOC
## Machine Trap Setup CSRs

### `mstatus`

- **Name**: Machine status register - low word
- **Address**: `0x300`
- **Reset value**: `0x00000000`
- **ISA**: `Zicsr`
- **Description**: The `mstatus` CSR is used to configure general machine environment parameters.

#### `mstatus` CSR bits

| Bit | Name [C] | R/W | Function |
|---|---|---|---|
| 3     | `CSR_MSTATUS_MIE`  | r/w | **MIE**: Machine-mode interrupt enable flag |
```

--------------------------------

### Launch Secondary CPU Core (Core 1) - NEORV32 SMP

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/cpu_dual_core.adoc

Use this function prototype to launch the secondary CPU core (core 1) from the primary core (core 0). It requires the entry point function, stack memory, and stack size for core 1. This function can only be executed on core 0.

```c
int neorv32_smp_launch(int (*entry_point)(void), uint8_t* stack_memory, size_t stack_size_bytes);
```

--------------------------------

### Get Current Local Time

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/micropython_port.adoc

The `time.localtime()` function returns the current local time as a tuple.

```python
>>> import time
>>> time.localtime()
(2025, 4, 20, 19, 52, 46, 6, 110)
```

--------------------------------

### Import NEORV32 Tracer GDB Script

Source: https://github.com/stnolting/neorv32/blob/main/docs/datasheet/soc_tracer.adoc

Source this GDB script to enable tracer commands like `tracer_get` and `tracer_start`.

```gdb
(gdb) source path/to/neorv32/sw/example/demo_tracer/neorv32_tracer.gdb
```

--------------------------------

### Print NEORV32 Hardware Configuration and System Info

Source: https://context7.com/stnolting/neorv32/llms.txt

This C code snippet initializes the NEORV32 system, prints the full hardware configuration, retrieves and prints CPU clock frequency, memory sizes, number of CPU cores, boot mode, and checks for simulation environment. It also lists the availability of various peripherals.

```c
#include <neorv32.h>

int main() {
    neorv32_rte_setup();
    neorv32_uart0_setup(19200, 0);

    // Print full hardware configuration
    neorv32_aux_print_hw_config();

    // Get processor clock frequency
    uint32_t clk = neorv32_sysinfo_get_clk();
    neorv32_uart0_printf("CPU Clock: %u Hz\n", clk);

    // Get memory sizes
    uint32_t imem = neorv32_sysinfo_get_imemsize();
    uint32_t dmem = neorv32_sysinfo_get_dmemsize();
    neorv32_uart0_printf("IMEM: %u bytes\n", imem);
    neorv32_uart0_printf("DMEM: %u bytes\n", dmem);

    // Get number of CPU cores
    uint32_t cores = neorv32_sysinfo_get_numcores();
    neorv32_uart0_printf("CPU cores: %u\n", cores);

    // Get boot mode
    uint32_t boot = neorv32_sysinfo_get_bootmode();
    neorv32_uart0_printf("Boot mode: %u\n", boot);

    // Check if running in simulation
    if (neorv32_sysinfo_is_sim()) {
        neorv32_uart0_puts("Running in simulation!\n");
    }

    // Check peripheral availability
    neorv32_uart0_puts("\nPeripherals:\n");
    neorv32_uart0_printf(" UART0:  %s\n", neorv32_uart0_available() ? "yes" : "no");
    neorv32_uart0_printf(" GPIO:   %s\n", neorv32_gpio_available() ? "yes" : "no");
    neorv32_uart0_printf(" SPI:    %s\n", neorv32_spi_available() ? "yes" : "no");
    neorv32_uart0_printf(" TWI:    %s\n", neorv32_twi_available() ? "yes" : "no");
    neorv32_uart0_printf(" CLINT:  %s\n", neorv32_clint_available() ? "yes" : "no");
    neorv32_uart0_printf(" WDT:    %s\n", neorv32_wdt_available() ? "yes" : "no");
    neorv32_uart0_printf(" TRNG:   %s\n", neorv32_trng_available() ? "yes" : "no");
    neorv32_uart0_printf(" NEOLED: %s\n", neorv32_neoled_available() ? "yes" : "no");
    neorv32_uart0_printf(" DMA:    %s\n", neorv32_dma_available() ? "yes" : "no");
    neorv32_uart0_printf(" PWM:    %s\n", neorv32_pwm_available() ? "yes" : "no");
    neorv32_uart0_printf(" GPTMR:  %s\n", neorv32_gptmr_available() ? "yes" : "no");

    // Print NEORV32 logo and version
    neorv32_aux_print_logo();
    neorv32_aux_print_about();

    return 0;
}

```

--------------------------------

### Compile Test Application

Source: https://github.com/stnolting/neorv32/blob/main/docs/userguide/using_ocd.adoc

Clean and compile the 'demo_blink_led' application to generate the 'main.elf' file required for debugging. This command should be run from the application's directory.

```bash
neorv32/sw/example/demo_blink_led$ make clean_all all
```
Tokens:
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