Icarus Verilog

https://github.com/steveicarus/iverilog
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Icarus Verilog is a compiler for the Verilog Hardware Description Language, supporting a subset of...
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### iverilog command line examples

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/reporting_issues.rst

Example command lines to include in an issue report, showing how to invoke the compiler with different options and file extensions.

```none
iverilog -o foo.out -tvvp foo.v
iverilog foo.vl -s starthere
```

--------------------------------

### Install Icarus Verilog with sudo make install

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Install the compiled Icarus Verilog build using sudo. Run this after a successful make.

```console
% sudo make install
```

--------------------------------

### Configure output showing dependency checks

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Example output from the configure script, showing checks for required tools and libraries. The inline comments indicate which are required or recommended.

```none
checking build system type... x86_64-pc-linux-gnu
checking host system type... x86_64-pc-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
...
checking for gperf... gperf       # required for git builds
checking for man... man           # you likely want manual pages
checking for ps2pdf... ps2pdf
checking for groff... groff
checking for git... git           # required for git builds
checking for flex... flex         # required
checking for bison... bison       # required
...
checking for tputs in -ltermcap... yes
checking for readline in -lreadline... yes
checking for add_history in -lreadline... yes
checking for readline/readline.h... yes
checking for readline/history.h... yes           # you likely want this
...
checking for pthread_create in -lpthread... yes
checking for gzwrite in -lz... yes
checking for gzwrite in -lz... (cached) yes
checking for BZ2_bzdopen in -lbz2... yes
checking for BZ2_bzdopen in -lbz2... (cached) yes     # you want these for fst dumping
...
<Create all the parameterized Makefile and header files>
```

--------------------------------

### Example `line directive

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/ivlpp_flags.rst

Example of a line directive and the following comment, showing that the parser changes the filename and line number so the next line is line 6 in foo.vl.

```none
`line 6 "foo.vl" 0
// I am on line 6 in file foo.vl.
```

--------------------------------

### Expected last lines of make.log

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Indicates the build and check succeeded, showing the 'Hello, World' output from the example test.

```none
...
driver/iverilog -B. -BMvpi -BPivlpp -tcheck -ocheck.vvp ../iverilog/examples/hello.vl
vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
Hello, World
```

--------------------------------

### System Function Table (SFT) declaration example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Shows the format of an SFT file for Icarus Verilog versions prior to v11. Lines either start with '#' as comments or contain a declaration of a system function name (with leading '$') and its return type. Supported types are vpiSysFuncInt, vpiSysFuncReal, and vpiSysFuncSized <wid> <signed|unsigned>; unspecified functions default to vpiSysFuncSized 32 unsigned. Provide this file as an ordinary source file to the iverilog command line (e.g., example.sft).

```none
# Example sft declarations of some common functions
$random      vpiSysFuncInt
$bitstoreal  vpiSysFuncReal
$realtobits  vpiSysFuncSized 64 unsigned
```

--------------------------------

### Install and uninstall Solaris package

Source: https://github.com/steveicarus/iverilog/blob/master/solaris/README-solaris_pkg.txt

These commands handle installation and uninstallation of the prebuilt Solaris package. First, copy the compressed package to /tmpabile, unpack it, then install with pkgadd. To remove the package, use pkgrm with the registered name 'IVLver'.

```shell
cp package_name.gz /tmp
cd /tmp
gunzip package_name.gz

```

```shell
cd /tmp
pkgadd -d package_name

```

```shell
pkgrm IVLver

```

--------------------------------

### hello.c VPI module source

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Complete working example to place in the file hello.c. Defines a compile-time function hello_compiletf that takes a user_data argument and casts it to void to suppress unused-parameter warnings.

```c
# include  <vpi_user.h>

static int hello_compiletf(char*user_data)
{
      (void)user_data; // Avoid warning for unused parameter.
      return 0;
}

```

--------------------------------

### Build Icarus Verilog with makepkg-mingw

Source: https://github.com/steveicarus/iverilog/blob/master/msys2/README.md

This sequence installs development tools, clones the repository, and executes the build process using makepkg-mingw.

```sh
# Install the base development tools
pacman -S base-devel

# Retrieve the Icarus Verilog sources. Optionally, retrieve a tarball, or a
# specific branch/version.
git clone https://github.com/steveicarus/iverilog
cd iverilog

# Call makepkg-mingw from the directory 'msys2'. It will install dependencies,
# build, check, and package Icarus Verilog.
cd msys2
makepkg-mingw --noconfirm --noprogressbar -sCLf

# Optionally, install the tarball(s)/package(s). Or just distribute it/them.
pacman -U --noconfirm *.zst
```

--------------------------------

### Install compile-time prerequisites with apt

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Installs the packages needed to compile Icarus Verilog from source on a Debian/Ubuntu-like system: autoconf, gperf, make, gcc, g++, bison, and flex.

```bash
apt install -y autoconf gperf make gcc g++ bison flex
```

--------------------------------

### iverilog -E preprocessor-only example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_line_flags.rst

Runs only the preprocessor on src1.v and src2.v, producing a single output file foo.v with all preprocessing (header includes and ifdefs) resolved. Useful for preprocessing for other tools.

```none
% iverilog -E -ofoo.v -DKEY=10 src1.v src2.v
```

--------------------------------

### Complete command file example with comments, library search, plusargs, and file names

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

A sample command file demonstrating major syntactic elements: comments, variable substitution, library search directory (-y), plusarg (+libext+.v+.vl), and file names including one with blanks. It shows how command files can describe a project concisely.

```none
# This is a comment in a command file.
# The -y statement declares a library
# search directory
-y $(PROJ_LIBRARY)/prims
#
# This plusarg tells the compiler that
# files in libraries may have .v or .vl
# extensions.
+libext+.v+.vl
#
main.v // This is a source file
#
# This is a file name with blanks.
C:/Project Directory/file name.vl
```

--------------------------------

### Verilog Example Module: top

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-stub.rst

A simple top module that displays a greeting on simulation. This example is used to demonstrate what the stub code generator produces for a basic design with an initial block.

```verilog
module top;
    initial $display("Hello World!");
endmodule
```

--------------------------------

### Plusarg example: +libext+.v+.V+.ver

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

Shows the syntax for a plusarg line in a command file, where the '+' character separates tokens. This example declares file extensions for library search.

```none
+libext+.v+.V+.ver
```

--------------------------------

### Source file x.v instantiating library module

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_quirks.rst

Example source file that instantiates module b from a library. When listed on the command line or in the command file, its macro definitions (here MACRO_A) are passed to library modules.

```verilog
module main;
  reg foo;
  b dut(foo);
endmodule
`define MACRO_A
```

--------------------------------

### Example module for XNF and EDIF port generation

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

A simple Verilog module with a single-bit output and a 3-bit input vector, used as the example for both XNF and EDIF root port generation.

```verilog
module main(out, in);
    output out;
    input [2:0] in;
    [...]
endmodule
```

--------------------------------

### Example branch name with GitHub ID

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Example of a branch name that includes a GitHub ID, as recommended for pull requests.

```console
% git checkout -b steveicarus/foo-feature
```

--------------------------------

### VVP statement with comment - Label .functor and

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/vvp/vvp.rst

Shows the general statement format for the VVP assembly-like source: a label, an opcode, operands, and a required terminating semicolon that also starts a comment. The label in this example is not required for all opcodes. The semicolon is mandatory even without a comment.

```none
Label .functor and, 0x5a, x, y  ; This is a comment.
```

--------------------------------

### Library directory structure example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vhdlpp_flags.rst

Shows the directory layout for VHDL libraries. The directory name (in lower case) is the library name used in the 'import' statement, and packages are stored in files named <foo>.pkg.

```none
<directory>/...
   sample/...
     test1.pkg
     test2.pkg
   bar/...
     test3.pkg
```

--------------------------------

### Using $readmemh without search path

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_extensions.rst

Basic example of reading a memory file from the current working directory using $readmemh.

```verilog
reg [7:0] mem [0:7];
initial begin
  $readmemh("datafile.txt", mem);
end
```

--------------------------------

### VHDL library and package access example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vhdlpp_flags.rst

Shows how to access VHDL libraries and packages in VHDL code. Use the '+vhdl-libdir+<directory>' record in a config file to tell Icarus Verilog where to look for libraries, then use 'library' and 'use' statements to access packages.

```none
library sample;
library bar;
use sample.test1.all;
use bar.test3.all;
```

--------------------------------

### Error output when autoconf or gperf are missing

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Shows the error messages produced by autoconf.sh when autoconf or gperf are not installed. You must install these tools before continuing.

```none
Autoconf in root...
autoconf.sh: 10: autoconf: not found
Precompiling lexor_keyword.gperf
autoconf.sh: 13: gperf: not found.
```

--------------------------------

### Using $readmempath to specify search path

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_extensions.rst

Example showing how to set a search path with $readmempath so that $readmemh searches multiple directories. The first located file is used.

```verilog
reg [7:0] mem [0:7];
initial begin
  $readmempath(".:alternative:/global/defaults");
  $readmemh("datafile.txt", mem);
end
```

--------------------------------

### Example line in regress-vvp.list

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/regression_tests.rst

Shows the format of a line in the regress-vvp.list file: the test name followed by the path to the JSON description file, relative to the ivtest directory.

```console
macro_str_esc  vvp_tests/macro_str_esc.json
```

--------------------------------

### Example Verilog module for sizer analysis

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-sizer.rst

A simple top module with a clock, reset, and blink output. It contains a flip-flop and combinational logic that the sizer will analyze.

```verilog
module top (
    input clock,
    input reset,
    output blink
);
    reg out;

    always @(posedge clock) begin
        if (reset) begin
            out = 1'b0;
        end else begin
            out <= !out;
        end
    end

    assign blink = out;

endmodule

```

--------------------------------

### sizer.txt output

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-sizer.rst

Output of the sizer target for the example module. It reports flip-flops, logic gates, MUX slices, and unaccounted LOG entries for the module and totals.

```none
**** module/scope: top
     Flip-Flops   : 1
     Logic Gates  : 3
     MUX[2]: 1 slices
     LOG[13]: 1 unaccounted
     LOG[14]: 1 unaccounted
**** TOTALS
     Flip-Flops   : 1
     Logic Gates  : 3
     MUX[2]: 1 slices
     LOG[13]: 1 unaccounted
     LOG[14]: 1 unaccounted
```

--------------------------------

### Uninstall Icarus Verilog with make uninstall

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Uninstall the software using make uninstall. The sudo prefix may be skipped if not needed, as described in the install description.

```none
% sudo make uninstall

```

--------------------------------

### Stub Output for Top Module

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-stub.rst

The resulting stub.txt contents for the given Verilog example. Shows the root module, scope details, time units, and the initial block with its $display call and parameter details.

```none
root module = top
scope: top (0 parameters, 0 signals, 0 logic) module top time units = 1e0
 time precision = 1e0
end scope top
# There are 0 constants detected
initial
    Call $display(1 parameters); /* hello_world.v:2 */
        <string="Hello World!", width=96, type=bool>
```

--------------------------------

### Run autoconf.sh with success and missing-tool errors

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Run the autoconf.sh script to generate configuration files. The first block shows successful execution; the second shows failure when autoconf or gperf is not installed. Requires autoconf and gperf tools.

```console
% sh autoconf.sh
Autoconf in root...
Precompiling lexor_keyword.gperf
Precompiling vhdlpp/lexor_keyword.gperf
```

```console
% sh autoconf.sh
Autoconf in root...
autoconf.sh: 10: autoconf: not found
Precompiling lexor_keyword.gperf
autoconf.sh: 13: gperf: not found.
```

--------------------------------

### Valid extended net declarations

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_extensions.rst

Examples of valid net declarations using extended data types: real, logic, and bool.

```none
wire real foo = 1.0;
tri logic bus[31:0];
wire bool addr[23:0];
... and so on.
```

--------------------------------

### Compile VPI module with gcc

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Compiles and links a VPI module as a shared object using gcc with the -fpic flag and the vpi library. Requires vpi_user.h and libvpi.a installed so gcc can find them.

```none
% gcc -c -fpic hello.c
% gcc -shared -o hello.vpi hello.o -lvpi
```

--------------------------------

### iverilog -Y and -y flags example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_line_flags.rst

Shows how to use the -Y flag to add a file extension and the -y flag to add a library search directory. The compiler will look for undefined modules in the 'sources' directory, checking for files named m.v or m.sv.

```none
% iverilog -Y .sv -y sources src.v
```

--------------------------------

### Multi-file counter design with test bench (counter.v and counter_tb.v)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

A complete multi-file example: counter.v defines a parameterized up counter with an asynchronous reset, and counter_tb.v instantiates it as the test bench. The test bench drives a pulsing reset, a 10-time-unit clock, and monitors the counter value. These files are compiled together with iverilog -o my_design counter_tb.v counter.v.

```verilog
module counter(out, clk, reset);

  parameter WIDTH = 8;

  output [WIDTH-1 : 0] out;
  input              clk, reset;

  reg [WIDTH-1 : 0]   out;
  wire               clk, reset;

  always @(posedge clk or posedge reset)
    if (reset)
      out <= 0;
    else
      out <= out + 1;

endmodule // counter
```

```verilog
module test;

  /* Make a reset that pulses once. */
  reg reset = 0;
  initial begin
     # 17 reset = 1;
     # 11 reset = 0;
     # 29 reset = 1;
     # 11 reset = 0;
     # 100 $stop;
  end

  /* Make a regular pulsing clock. */
  reg clk = 0;
  always #5 clk = !clk;

  wire [7:0] value;
  counter c1 (value, clk, reset);

  initial
     $monitor("At time %t, value = %h (%0d)",
              $time, value, value);
endmodule // test
```

--------------------------------

### Library module a.v with macro definition

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_quirks.rst

Example library module that defines a macro MACRO_A. This module is loaded via the -y mechanism and its macro definitions do not escape to other library modules.

```verilog
`define MACRO_A 1
module a(input x);
  always @(x) $display("x=",x);
endmodule
```

--------------------------------

### Example JSON test description file

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/regression_tests.rst

A simple test description file in JSON format, containing the required keys 'type' and 'source', and an optional 'gold' key. This file is used by the vvp_reg.py script to run the regression test.

```java
{
  "type"   : "normal",
  "source" : "macro_str_esc.v",
  "gold"   : "macro_str_esc"
}
```

--------------------------------

### Compile Icarus Verilog on Linux with configure and make

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Standard Linux build sequence: configure the source tree, then compile with make. Requires bison, flex, g++ and gcc installed. The output shows typical checks and compilation commands.

```console
% ./configure
configure: loading site script /usr/share/site/x86_64-unknown-linux-gnu
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
[...and so on...]

% make
mkdir dep
Using git-describe for VERSION_TAG
g++ -DHAVE_CONFIG_H -I. -Ilibmisc  -Wall -Wextra -Wshadow   -g -O2 -MD -c main.cc -o main.o
mv main.d dep/main.d
g++ -DHAVE_CONFIG_H -I. -Ilibmisc  -Wall -Wextra -Wshadow   -g -O2 -MD -c async.cc -o async.o
mv async.d dep/async.d
g++ -DHAVE_CONFIG_H -I. -Ilibmisc  -Wall -Wextra -Wshadow   -g -O2 -MD -c design_dump.cc -o design_dump.o
mv design_dump.d dep/design_dump.d
g++ -DHAVE_CONFIG_H -I. -Ilibmisc  -Wall -Wextra -Wshadow   -g -O2 -MD -c discipline.cc -o discipline.o
[...and so on...]
```

--------------------------------

### Automating array word dumping with a loop

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_quirks.rst

Shows how to automate dumping array words using a loop with an integer index. This produces the same results as the previous example but is easier to specify/change which elements to dump. Note that $dumpvars uses the current index value to create a constant array selection, avoiding the issue of all callbacks using the same index.

```verilog
integer idx;
```

```verilog
for (idx = 0; idx < 2; idx = idx + 1) $dumpvars(0, array[idx]);
```

--------------------------------

### Configure option: --enable-libveriuser

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Builds the libveriuser library and cadpli module for PLI version 1 (ACC and TF routines), deprecated in IEEE 1364-2005. Starting with V13, these are only built if this option is used.

```none
--enable-libveriuser
```

--------------------------------

### VCD $dumpoff section for real variables: Verilog-XL example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/misc/ieee1364-notes.rst

Shows the $dumpoff section as produced by Verilog-XL, which dumps r0 ! for real variables. This contrasts with Icarus Verilog's NaN approach.

```vcd
$dumpoff
r0 !
r0 "
$end
```

--------------------------------

### Variable substitution in command file: -y $(VENDOR)/verilog/library

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

Use $(name) to reference environment variables in command file paths. This example imports a vendor library using the VENDOR variable, allowing the command file to be shared without editing. Always use forward slashes as directory separators, even on Windows.

```none
-y $(VENDOR)/verilog/library
```

--------------------------------

### Create build directory and navigate to it

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Shows how to create a separate build directory for multiple variants or use the source directory for a single build. The 'or' indicates alternative commands.

```none
% mkdir gcc
% cd gcc
or
% cd iverilog
```

--------------------------------

### Verilog example showing %g format specifier behavior

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_quirks.rst

This Verilog module demonstrates the difference between %g and %e/%f format specifiers. It assigns different real values to rval and uses $display with %10.3g, %10.3e, and %10.3f. The output shows that %g produces one less significant digit than %e and only matches %f for certain values.

```verilog
module top_level;
  real rval;
  initial begin
    rval = 1234567890;
    $display("This is g and e: %10.3g, %10.3e.", rval, rval);
    rval = 0.1234567890;
    $display("This is g and f: %10.3g, %10.3f.", rval, rval);
    rval = 1.234567890;
    $display("This is more g and f: %10.3g, %10.3f.", rval, rval);
  end
endmodule // top_level
```

```verilog
This is g and e:   1.23e+09,  1.235e+09.
This is g and f:      0.123,      0.123.
This is more g and f:       1.23,      1.235.
```

--------------------------------

### PAD attribute pin assignment example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Shows the PAD attribute syntax for assigning module ports to pins. The value is a comma-separated list of locations, one per bit of the signal. A pin number of 0 lets the back end tools choose a pin when the architecture supports it. Ports assigned to a pin are not connected to a port of the EDIF file.

```Verilog
module main( (* PAD = "P10" *)         output out,
             (* PAD = "P20,P21,P22" *) input [2:0] in);
    [...]
endmodule
```

--------------------------------

### Run configure with gcc and optimization flags

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Configures the build with gcc, optimization flags, and a suffix to distinguish the build. Adjust the prefix if you lack sudo permission.

```none
% env CFLAGS=-O2 CXXFLAGS=-O2 LDFLAGS=-s CC=gcc CXX=g++ ../iverilog/configure --enable-suffix=-gcc --prefix=/usr/local
```

--------------------------------

### iverilog -o top.vvp -s top hello_world.v

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-vvp.rst

Compiles hello_world.v into the vvp simulation file top.vvp, using the default target. The -s top option selects the top module.

```none
%  iverilog -o top.vvp -s top hello_world.v
```

--------------------------------

### Build configure script and hash files with autoconf.sh

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Runs autoconf.sh to generate the configure script and hash files, then changes to the parent directory. This is only needed after cloning, not for released tar/zip files. Requires autoconf and gperf tools; the script fails if they are missing.

```none
% sh autoconf.sh
% cd ..
```

--------------------------------

### iverilog -o top.vvp -tvvp -s top hello_world.v

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-vvp.rst

Equivalent command that explicitly selects the vvp code generator with the -tvvp flag.

```none
%  iverilog -o top.vvp -tvvp -s top hello_world.v
```

--------------------------------

### Configure option: --enable-libvvp

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Builds vvp as a small stub linked to a shared library, libvvp.so, which can be linked with other programs to host a vvp simulation.

```none
--enable-libvvp
```

--------------------------------

### Install Bison 3 and update PATH on macOS

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

For macOS versions newer than 10.3, the GNU Bison tool packaged with Xcode needs to be updated to version 3. These commands install Bison via Homebrew and add its bin directory to the shell PATH.

```none
brew install bison
echo 'export PATH="/usr/local/opt/bison/bin:$PATH"' >> ~/.bash_profile
```

--------------------------------

### Load a VPI module with vvp -m

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Command to load a VPI module (sample.vpi) into the vvp runtime before simulation execution.

```none
% vvp -msample foo.vvp
```

--------------------------------

### Compile and run a Hello World Verilog module

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

Creates a minimal Verilog module that prints "Hello, World" and calls $finish. Compile with $iverilog -o hello hello.v, then run with vvp to see the output. Shows the standard two-step compile-and-run flow for Icarus Verilog.

```verilog
module hello;
  initial
    begin
      $display("Hello, World");
      $finish ;
    end
endmodule
```

```none
% iverilog -o hello hello.v
```

```none
% vvp hello
Hello, World
```

--------------------------------

### Typical vvp command line usage

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vvp_flags.rst

Shows the general syntax for invoking vvp: flags, input file, and extended arguments. The extended arguments must appear after the input file name.

```none
% vvp <flags> foo.vvp <extended arguments>
```

--------------------------------

### Compile and run multi-file design (iverilog -o my_design counter_tb.v counter.v)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

Command lines to compile two Verilog source files with iverilog into my_design, then run the compiled design with vvp. This is the simplest way to handle multi-file designs.

```none
% iverilog -o my_design  counter_tb.v counter.v
% vvp my_design
```

--------------------------------

### iverilog and vvp command sequence with output

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Commands to compile and run the simulation with iverilog and vvp, followed by the expected output showing the computed square roots for each input value.

```none
% iverilog -osqrt_readmem.vvp sqrt_readmem.vl sqrt.vl
% vvp sqrt_readmem.vvp
y=    9
y=    5
y=    5
y=    4
y=    1
```

--------------------------------

### Example benign warnings from bison output

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Common benign warnings that may appear in make.log, related to bison-generated code. Different compilers may produce other warnings.

```none
From: ./parse.cc
parse.cc:9462:18: warning: missing initializer for member ‘vlltype::lexical_pos’ [-Wmissing-field-initializers]
 9462 |   = { 1, 1, 1, 1 }
      |                  ^
parse.cc:9462:18: warning: missing initializer for member ‘vlltype::text’ [-Wmissing-field-initializers]
```

```none
From: ./vvp/parse.cc
parse.cc:3242: warning: suspicious sequence in the output: m4_type [-Wother]
parse.cc:3248: warning: suspicious sequence in the output: m4_type [-Wother]
```

--------------------------------

### Compile with SWIFT wrappers using +libdir+

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/misc/swift.rst

Add this +libdir+ statement to your command file to include the Verilog wrappers for your SWIFT model. The wrappers are located in the smartmodel directory and invoke the $lm_model system tasks.

```none
+libdir+.../smartmodel/sol/wrappers/verilogxl
```

--------------------------------

### Define vlog_startup_routines table

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

C definition of a null-terminated array of function pointers that the simulator calls to register system tasks and functions.

```c
void (*vlog_startup_routines[])(void) = {
   hello_register,
   0
};
```

--------------------------------

### Flags file key-value format

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/ivlpp_flags.rst

The general format for a line in a flags file. Blank lines and lines starting with '#' are ignored; leading and trailing whitespace is removed before interpretation.

```none
<key>:<value>
```

--------------------------------

### Compile, run, and view waveforms with GTKWave

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/waveform_viewer.rst

These commands compile the design and testbench with iverilog, run the simulation with vvp, and open the resulting VCD file in GTKWave. The ampersand backgrounds the GTKWave process.

```console
% iverilog -o dsn counter_tb.v counter.v
% vvp dsn
% gtkwave test.vcd &
```

--------------------------------

### Hello World Verilog module

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

A minimal Verilog module that prints "Hello World" and calls $finish. Save it as hello.vl and compile with iverilog hello.vl, then run the generated program with ./a.out.

```verilog
// ------------------------ hello.vl ----------------------------

module main();

initial
  begin
    $display("Hello World");
    $finish ;
  end

endmodule

// --------------------------------------------------------------
```

--------------------------------

### Compile hello.vl with iverilog

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Compiles the hello.vl Verilog source file using the iverilog command. Presumes /usr/local/include and /usr/local/lib are part of the compiler search path, which is usually the case for gcc.

```bash
	iverilog hello.vl
```

--------------------------------

### Explanation of vvp command line options

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/misc/swift.rst

Breakdown of the vvp command line options: -mcadpli includes the cadpli compatibility module, a.out is the compiled vvp file, and -cadpli loads the swiftpli.so shared object and boots it.

```none
-mcadpli
   Include the cadpli compatibility module

a.out
   This is your compiled vvp file

-cadpli=$LMC_HOME/lib/x86_linux.lib/swiftpli.so:swift_boot
   This tells the cadpli module to load the swiftpli.so
   shared object, and boot it. This is code that comes with
   your SWIFT modules, and provides the generic SWIFT
   capabilities (lm_* system tasks) needed by the module
   itself.
```

--------------------------------

### Compile with command file using iverilog -c

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Use this command to compile a design from a command file. The command file lists the source files and options for the design.

```none
% iverilog -c example.cf
```

--------------------------------

### Compile VPI module with iverilog-vpi

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Preferred method that works on all supported systems. Takes source files as command arguments, compiles them with proper compiler flags, and links them into a VPI module with any system-specific libraries and linker flags required.

```none
% iverilog-vpi hello.c
```

--------------------------------

### XNF SIG records for root ports

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Generated SIG records for the example module when targeting XNF. Vector bits are mapped to numbered pins (in2, in1, in0) because XNF requires mangled names.

```none
SIG, main/out, PIN=out
SIG, main/in<2>, PIN=in2
SIG, main/in<1>, PIN=in1
SIG, main/in<0>, PIN=in0
```

--------------------------------

### Compile and run sqrt_plusargs with single input

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Commands to compile the test bench and sqrt32 module with iverilog, then run the simulation with vvp passing +x=81. The output shows y=9.

```none
% iverilog -osqrt_plusargs.vvp sqrt_plusargs.v sqrt.v
% vvp sqrt_plusargs.vvp +x=81
y=    9
```

--------------------------------

### Configure git and clone the Icarus Verilog repository

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Sets up git user identity and clones the Icarus Verilog repository from GitHub. The first two commands are optional but recommended for submitting patches. The clone creates a directory named iverilog with the latest source from the HEAD.

```none
% git config --global user.name "Your Name Goes Here"
% git config --global user.email you@yourpublicemail.example.com
% git clone https://github.com/steveicarus/iverilog.git
```

--------------------------------

### Library module b.v checking macro definition

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/icarus_verilog_quirks.rst

Example library module that checks if MACRO_A is defined. Because macros from other library modules do not escape, MACRO_A will not be defined here unless it is defined on the command line or in the command file.

```verilog
 module b(input y);
 `ifdef MACRO_A
   always @(y) $display("MACRO_A is defined",,y);
`else
   always @(y) $display("MACRO_A is NOT defined",,y);
 `endif
 endmodule
```

--------------------------------

### Generated `line directive format

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/ivlpp_flags.rst

Directive generated by the preprocessor to update the compiler's file and line counters. It is emitted every time the preprocessor switches files, including when starting an included file or returning to the including file.

```none
`line <num> <name> <level>
```

--------------------------------

### Run a PLI1 module with vvp and cadpli

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/cadpli/cadpli.rst

Command to load a PLI1 module (product.so) with bootstrap function my_boot using the cadpli module. The -mcadpli argument loads the cadpli.vpl library, and the -cadpli=<module>:<boot_func> argument specifies the shared object and bootstrap function.

```none
vvp -mcadpli a.out -cadpli=./product.so:my_boot
```

--------------------------------

### VCD $dumpoff section for real variables: Icarus Verilog example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/misc/ieee1364-notes.rst

Shows the $dumpoff section in a VCD file. Icarus Verilog dumps NaN values for real variables in the dead-zone, unlike Verilog-XL which dumps r0 ! and ModelTech which ignores them.

```vcd
$dumpoff
rNaN !
rNaN "
$end
```

--------------------------------

### EDIF port definitions for root ports

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Generated EDIF interface port definitions for the example module. Port names use the signal base name with vector bit numbers in brackets (in[0], in[1], in[2]) and include direction marks.

```none
out   OUTPUT
in[0] INPUT
in[1] INPUT
in[2] INPUT
```

--------------------------------

### Generate PCB and netlist files with iverilog -tpcb

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-pcb.rst

Invokes iverilog with the PCB target to generate foo.pcb and, because the -pnetlist flag is set, also writes a netlist file to foo.net.

```none
% iverilog -tpcb -ofoo.pcb -pnetlist=foo.net foo.v
```

--------------------------------

### Compile and run sqrt_plusargs with two inputs

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Commands to compile and run the two-input test bench, passing +x=81 and +z=64. The output shows y1=9 and y2=8.

```none
% iverilog -osqrt_plusargs.vvp sqrt_plusargs.v sqrt.v
% vvp sqrt_plusargs.vvp +x=81 +z=64
y1=    9
y2=    8
```

--------------------------------

### Run simulation with vvp and cadpli

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/misc/swift.rst

Run the compiled simulation with the vvp command, including the cadpli module and specifying the SWIFT PLI shared object. The -cadpli option loads swiftpli.so and boots it, providing the generic SWIFT capabilities.

```none
% vvp -mcadpli a.out -cadpli=$LMC_HOME/lib/x86_linux.lib/swiftpli.so:swift_boot
```

--------------------------------

### cellref attribute example for clock buffer

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Shows how to attach the cellref attribute to a logic device to force generation of a specific device type. The value syntax is <cell type>:<pin name>,... where the cell type is the library part name and the pin names are the library pin names in the order the logic device pins are connected.

```Verilog
buf my_gbuf(out, in);
$attribute(my_buf, "cellref", "GBUF:O,I");
```

--------------------------------

### Clean build directory with make clean or make distclean

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Clean up the compile directory. 'make clean' removes compiled files, while 'make distclean' also removes files generated during the configure phase.

```none
% make clean
or
% make distclean

```

--------------------------------

### Multi-file compilation using command file (-c file_list.txt)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

Uses a command file named file_list.txt that lists input files one per line Particular -c flag tells iverilog to read that command file as the list of Verilog inputs. This scales to larger designs than listing files on the command line.

```none
counter.v
counter_tb.v
```

```none
% iverilog -o my_design -c file_list.txt
% vvp my_design
```

--------------------------------

### Run compiler/VVP tests with vvp_reg.py

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Run the new test script to execute compiler/VVP tests. The output shows a summary of test results, with a total of 3018 tests, 3013 passed, 0 failed, 2 not implemented, and 3 expected failures.

```none
Running compiler/VVP tests for Icarus Verilog version: 13, suffix: -gcc.
----------------------------------------------------------------------------
            macro_with_args: Passed.
                       mcl1: Passed.
                      pr622: Passed.
                      pr639: Passed.
                         ...
                   ssetclr2: Passed.
                   ssetclr3: Passed.
           synth_if_no_else: Passed.
                ufuncsynth1: Passed.
============================================================================
Test results:
  Total=3018, Passed=3013, Failed=0, Not Implemented=2, Expected Fail=3

```

```none
% ./vvp_reg.py --suffix=-gcc

```

```none
Running compiler/VVP tests for Icarus Verilog version: 13, suffix: -gcc
Using list(s): regress-vvp.list
----------------------------------------------------------------------------
                    always4A: Passed - CE.
                    always4B: Passed - CE.
                     analog1: Not Implemented.
                     analog2: Not Implemented.
                          ...
              vvp_quiet_mode: Passed.
             warn_opt_sys_tf: Passed - EF.
                       wreal: Passed.
            writemem-invalid: Passed - EF.
============================================================================
Test results: Ran 284, Failed 0.

```

--------------------------------

### Compile single-file design with Xilinx Foundation tools

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Use this command sequence to compile a Verilog design for a Xilinx Virtex device. The commands generate an EDIF file, convert it to NGD, map, and place-and-route.

```none
% iverilog -parch=virtex -o foo.edf foo.vl
% edif2ngd foo.edf foo.ngo
% ngdbuild -p v50-pq240 foo.ngo foo.ngd
% map -o map.ncd foo.ngd
% par -w map.ncd foo.ncd
```

--------------------------------

### Convert design to .blif using iverilog -tblif

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-blif.rst

Use this command to convert a structural Verilog design to a .blif file. The source files must be structural and the design must have a single root module, which becomes the .model name in the output.

```none
% iverilog -tblif -o<path>.blif  <source files>...
```

--------------------------------

### Compile Icarus Verilog with make

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

After configuring for cross-compilation, run make to compile Icarus Verilog using the cross compiler flags generated by the configure script.

```none
$ make
```

--------------------------------

### General library directory plusarg: +libdir+<path>...

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

Shows the more general '+libdir' plusarg syntax, which is equivalent to the '-y' argument but allows multiple paths.

```none
+libdir+<path>...
```

--------------------------------

### Configure option: --with-valgrind

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Adds extra memory cleanup and pool management code for better memory leak checking with valgrind. Not needed for basic error checking and should not be used if you only intend to use iverilog as a simulator.

```none
--with-valgrind
```

--------------------------------

### Run VPI tests with vpi_reg.pl

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Run the VPI regression test script to verify VPI functionality. The output shows a summary with a total of 77 tests, all passed, and no failures.

```none
% ./vpi_reg.pl --suffix=-gcc

```

```none
Running VPI tests for Icarus Verilog version: 13, suffix: -gcc.
----------------------------------------------------------------------------
          br_gh59: Passed.
         br_gh73a: Passed.
         br_gh73b: Passed.
         br_gh117: Passed.
               ...
 value_change_cb2: Passed.
 value_change_cb3: Passed.
 value_change_cb4: Passed.
      vpi_control: Passed.
============================================================================
Test results: Total=77, Passed=77, Failed=0, Not Implemented=0

```

--------------------------------

### Stub target config file (stub.conf)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/ivl/ivl_target.rst

Configuration file for the stub target that invokes basic optimization steps (cprop and nodangle) and specifies the target module stub.tgt. It is used when the -S flag is not given.

```none
functor:cprop
functor:nodangle
-t:dll
flag:DLL=stub.tgt

```

--------------------------------

### Create and compile an empty loadable target module (empty.c, empty.tgt)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/ivl/ivl_target.rst

A minimal loadable target module that defines target_design and returns 0, compiled into a shared object with gcc using -fpic and -shared. Compile with the command shown to create empty.tgt.

```c
# include  <ivl_target.h>

int target_design(ivl_design_t des)
{
     return 0;
}

```

```shell
% gcc -o empty.tgt -fpic -shared empty.c

```

--------------------------------

### Run make check and redirect output to make.log

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Compiles the code and runs checks, redirecting output to make.log. The redirection syntax shown is for tcsh/csh; bash/fish/zsh use '&>' instead of '>&'.

```none
% make check >& make.log
```

--------------------------------

### Change into the iverilog directory

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Changes the current directory to the cloned iverilog source tree.

```none
% cd iverilog
```

--------------------------------

### Standard Verilog-A math functions list

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/vpi/va_math.rst

List of all standard Verilog-A math functions implemented as Verilog-D system functions, prefixed with '$'. Arguments must be numbers, not constant strings; all functions return a real result. Underlying C library controls argument limits, typically returning +-Inf or NaN for unrepresentable results.

```none
$ln(x)       --  Natural logarithm
$log10(x)    --  Decimal logarithm
$exp(x)      --  Exponential
$sqrt(x)     --  Square root
$min(x,y)    --  Minimum
$max(x,y)    --  Maximum
$abs(x)      --  Absolute value
$floor(x)    --  Floor
$ceil(x)     --  Ceiling
$pow(x,y)    --  Power (x**y)
$sin(x)      --  Sine
$cos(x)      --  Cosine
$tan(x)      --  Tangent
$asin(x)     --  Arc-sine
$acos(x)     --  Arc-cosine
$atan(x)     --  Arc-tangent
$atan2(y,x)  --  Arc-tangent of y/x
$hypot(x,y)  --  Hypotenuse (sqrt(x**2 + y**2))
$sinh(x)     --  Hyperbolic sine
$cosh(x)     --  Hyperbolic cosine
$tanh(x)     --  Hyperbolic tangent
$asinh(x)    --  Arc-hyperbolic sine
$acosh(x)    --  Arc-hyperbolic cosine
$atanh(x)    --  Arc-hyperbolic tangent
```

--------------------------------

### Run regression test suite

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Runs the original regression test script with the configured suffix. Should give no failures.

```none
% cd ../iverilog/ivtest
% ./vvp_reg.pl --suffix=-gcc
```

--------------------------------

### Library directory argument: -y <path>

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

Shows the '-y' argument syntax for declaring a library directory in a command file. It works exactly like the compiler's '-y' option.

```none
-y <path>
```

--------------------------------

### Enable waveform dumping with $dumpfile and $dumpvars

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/waveform_viewer.rst

Place this initial block in your test bench to enable waveform dumping. It writes all signals in and below the 'test' module to 'test.vcd'. If $dumpfile is omitted, the output file defaults to dump.vcd, dump.lxt, dump.lxt2, or dump.fst depending on runtime flags.

```verilog
// Do this in your test bench

initial
begin
   $dumpfile("test.vcd");
   $dumpvars(0,test);
end
```
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