### Install Icarus Verilog

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Command to install the compiled version of Icarus Verilog after building from source.

```console
% sudo make install
```

--------------------------------

### Compiling and Installing on Linux/Unix

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Standard commands to configure, compile, and install Icarus Verilog on Linux/Unix-like systems.

```bash
./configure
make
(su to root)
# make install
```

--------------------------------

### Icarus Verilog Configuration Options

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Specific configuration options for Icarus Verilog build process.

```bash
--enable-suffix[=suffix]
--with-valgrind
--enable-libvvp
```

--------------------------------

### Build Configuration Script

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Script to generate configuration files required for building Icarus Verilog from source.

```bash
sh autoconf.sh
```

--------------------------------

### Git Cloning and Configuration

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Steps to clone the Icarus Verilog repository using Git and configure user information for potential patch submissions.

```bash
git config --global user.name "Your Name Goes Here"
git config --global user.email you@yourpublicemail.example.com
git clone https://github.com/steveicarus/iverilog.git
```

--------------------------------

### Compile and Run 'Hello, World!'

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

This snippet demonstrates the basic compilation and execution of a simple 'Hello, World!' Verilog program using Icarus Verilog. It shows the source code, the compilation command, and the execution command.

```verilog
module hello;
  initial
    begin
      $display("Hello, World");
      $finish ;
    end
endmodule
```

```bash
% iverilog -o hello hello.v
% vvp hello
```

--------------------------------

### Multi-file Design Compilation

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

This snippet shows two methods for compiling multi-file Verilog designs with Icarus Verilog. The first lists all source files on the command line, and the second uses a command file to list the source files.

```bash
# Method 1: Listing files on command line
% iverilog -o my_design  counter_tb.v counter.v
% vvp my_design

# Method 2: Using a command file
# Create file_list.txt with:
# counter.v
# counter_tb.v

% iverilog -o my_design -c file_list.txt
% vvp my_design
```

--------------------------------

### Branch Checkout

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Command to checkout the 'v11-branch' for working with the latest stable patches of Icarus Verilog.

```bash
git checkout --track -b v11-branch origin/v11-branch
```

--------------------------------

### Worked Example: Hello World VPI Module (Verilog Code)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

The Verilog code for the 'Hello, World!' example, which instantiates the '$hello' system task provided by the VPI module.

```Verilog
module main;
    initial $hello;
  endmodule
```

--------------------------------

### Configure Icarus Verilog Build

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Initiates the configuration process for compiling Icarus Verilog. This step checks for necessary dependencies like gcc and prepares the build environment. Requires bison, flex, g++, and gcc to be installed.

```console
./configure
configure: loading site script /usr/share/site/x86_64-unknown-linux-gnu
checking build system type... x86_64-unknown-linux-gnu
checking host system type... x86_64-unknown-linux-gnu
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
[...and so on...]
```

--------------------------------

### Configure Icarus Verilog Installation Prefix

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Specifies the installation directory for Icarus Verilog. The default is often '/usr/local', but can be changed using the --prefix option during the configure step.

```shell
./configure --prefix=/my/special/directory
```

--------------------------------

### Generate Configuration Files

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Generates configuration files using autoconf and gperf. This step is necessary after cloning the repository and requires autoconf and gperf to be installed.

```console
% sh autoconf.sh
Autoconf in root...
Precompiling lexor_keyword.gperf
Precompiling vhdlpp/lexor_keyword.gperf
```

--------------------------------

### Verilog Counter Module

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

This snippet defines a Verilog counter module with a specified width and includes a reset and clock input. It's a common example for demonstrating hierarchical designs.

```verilog
module counter(out, clk, reset);

  parameter WIDTH = 8;

  output [WIDTH-1 : 0] out;
  input	       clk, reset;

  reg [WIDTH-1 : 0]   out;
  wire	       clk, reset;

  always @(posedge clk or posedge reset)
    if (reset)
      out <= 0;
    else
      out <= out + 1;

endmodule // counter
```

--------------------------------

### Updating Source Code

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Command to synchronize the local Icarus Verilog source code with the remote repository.

```bash
git pull
```

--------------------------------

### Install Solaris Package

Source: https://github.com/steveicarus/iverilog/blob/master/solaris/README-solaris_pkg.txt

Instructions for installing a prebuilt Solaris package for Iverilog. This involves uncompressing the package and then using the 'pkgadd' command.

```bash
cp package_name.gz /tmp
cd /tmp
gunzip package_name.gz
cd /tmp
pkgadd -d package_name
```

--------------------------------

### Icarus Verilog Counter Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/gtkwave.rst

A Verilog example demonstrating a counter module and a test bench. The test bench includes waveform dumping setup, clock and reset generation, and monitoring of the counter's output. The example shows how to compile, run simulation, and view waveforms.

```verilog
module counter(out, clk, reset);

  parameter WIDTH = 8;

  output [WIDTH-1 : 0] out;
  input            clk, reset;

  reg [WIDTH-1 : 0]   out;
  wire            clk, reset;

  always @(posedge clk)
    out <= out + 1;

  always @reset
    if (reset)
      assign out = 0;
    else
      deassign out;

endmodule // counter
```

```verilog
module test;

  /* Make a reset that pulses once. */
  reg reset = 0;
  initial begin
     $dumpfile("test.vcd");
     $dumpvars(0,test);

     # 17 reset = 1;
     # 11 reset = 0;
     # 29 reset = 1;
     # 5  reset =0;
     # 513 $finish;
  end

  /* Make a regular pulsing clock. */
  reg clk = 0;
  always #1 clk = !clk;

  wire [7:0] value;
  counter c1 (value, clk, reset);

  initial
     $monitor("At time %t, value = %h (%0d)",
              $time, value, value);
endmodule // test
```

```console
% iverilog -o dsn counter_tb.v counter.v
% vvp dsn
% gtkwave test.vcd &
```

--------------------------------

### Iverilog Command File Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/command_files.rst

A comprehensive example illustrating the use of comments, library paths, plus-arguments, and source file declarations in an Iverilog command file.

```English
# This is a comment in a command file.
# The -y statement declares a library
# search directory
-y $(PROJ_LIBRARY)/prims
#
# This plusarg tells the compiler that
# files in libraries may have .v or .vl
# extensions.
+libext+.v+.vl
#
main.v // This is a source file
#
# This is a file name with blanks.
C:/Project Directory/file name.vl
```

--------------------------------

### Standard Compilation Command

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

The standard command to compile source code after the configure script has been run. This command initiates the build process.

```shell
make
```

--------------------------------

### Hello World Example Compilation

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Provides a simple 'Hello World' Verilog program and the bash commands to compile and run it using the iverilog compiler.

```Verilog
// ------------------------ hello.vl ----------------------------

module main();

initial
  begin
    $display("Hello World");
    $finish ;
  end

endmodule

// --------------------------------------------------------------
```

```bash
	iverilog hello.vl
	./a.out
```

--------------------------------

### Install Icarus Verilog

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Command to install the compiled Icarus Verilog files. By default, it installs to /usr/local, but this can be changed using the --prefix flag during configuration.

```bash
make install
```

--------------------------------

### Install Icarus Verilog Prerequisites

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Installs the necessary development tools for compiling Icarus Verilog from source on Debian-based systems. This includes autoconf, gperf, make, gcc, g++, bison, and flex.

```bash
apt install -y autoconf gperf make gcc g++ bison flex
```

--------------------------------

### MSYS2 Build and Install Iverilog

Source: https://github.com/steveicarus/iverilog/blob/master/msys2/README.md

This snippet demonstrates the process of building and installing Iverilog on MSYS2. It covers installing the necessary toolchain, cloning the Iverilog repository, and using `makepkg-mingw` to build and package the software. Finally, it shows how to install the generated package.

```sh
# Install the toolchain
pacman -S mingw-w64-x86_64-toolchain
# and/or mingw-w64-i686-toolchain

# Retrieve iverilog sources. Optionally, retrieve a tarball, or an specific branch/version.
git clone https://github.com/steveicarus/iverilog
cd iverilog

# Call makepkg-mingw from subdir 'msys2'. It will build, check and package iverilog.
cd msys2
MINGW_INSTALLS=mingw64 makepkg-mingw --noconfirm --noprogressbar -sCLf
# or, set the envvar to 'mingw32', or unset it for building both packages at the same time

# Optionally, install the tarball(s)/package(s). Or just distribute it/them.
pacman -U --noconfirm *.zst
```

--------------------------------

### Verilog Test Bench for Counter

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

This snippet provides a Verilog test bench for the counter module. It includes logic to generate reset pulses and a clock signal, and uses $monitor to display the counter's output.

```verilog
module test;

  /* Make a reset that pulses once. */
  reg reset = 0;
  initial begin
     # 17 reset = 1;
     # 11 reset = 0;
     # 29 reset = 1;
     # 11 reset = 0;
     # 100 $stop;
  end

  /* Make a regular pulsing clock. */
  reg clk = 0;
  always #5 clk = !clk;

  wire [7:0] value;
  counter c1 (value, clk, reset);

  initial
     $monitor("At time %t, value = %h (%0d)",
              $time, value, value);
endmodule // test
```

--------------------------------

### Icarus Verilog Configuration Options

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Describes Icarus Verilog specific configuration options. '--enable-suffix' allows tagging programs and directories with a specified suffix, ensuring version compatibility.

```none
--enable-suffix[=suffix]

This option allows the user to build Icarus with a default suffix or when
provided a user defined suffix. All programs or directories are tagged with
this suffix. e.g.(iverilog-0.8, vvp-0.8, etc.). The output of iverilog will
reference the correct run time files and directories. The run time will check
that it is running a file with a compatible version e.g.(you can not run a
V0.9 file with the V0.8 run time).
```

--------------------------------

### Specify Root Module with -s Switch

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/getting_started.rst

Demonstrates how to use the '-s' flag with the iverilog compiler to specify a root module for elaboration. This is useful when the compiler cannot automatically determine the root or when you need to control which modules are elaborated.

```bash
% iverilog -s main -o hello hello.v
```

--------------------------------

### Build Solaris Package from Source

Source: https://github.com/steveicarus/iverilog/blob/master/solaris/README-solaris_pkg.txt

Steps to build a Solaris package from Iverilog sources. This includes configuring the build, editing package information files ('pkginfo', 'prototype'), and using 'mksolpkg'.

```bash
# Configure the build with a specific prefix
./configure --prefix=/path/to/install

# Edit pkginfo to update version and BASEDIR
# Edit prototype to manage installed files

# Create the Solaris package
mksolpkg
```

--------------------------------

### macOS Bison Update and Path Configuration

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Instructions for updating the Bison tool on macOS versions newer than 10.3 and configuring the system's PATH environment variable to include the updated Bison binary.

```shell
brew install bison
echo 'export PATH="/usr/local/opt/bison/bin:$PATH"' >> ~/.bash_profile
```

--------------------------------

### Verilog Example for Sizer Analysis

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-sizer.rst

A simple Verilog module used as an example input for the Icarus Verilog sizer. It demonstrates a basic flip-flop.

```verilog
module top (
    input clock,
    input reset,
    output blink
);
    reg out;

    always @(posedge clock) begin
        if (reset) begin
            out = 1'b0;
        end else begin
            out <= !out;
        end
    end

    assign blink = out;

endmodule
```

--------------------------------

### Compile Icarus Verilog

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Compiles the Icarus Verilog source code after the configuration step. This command builds the executable files and necessary object files for the project.

```console
make
mkdir dep
Using git-describe for VERSION_TAG
g++ -DHAVE_CONFIG_H -I. -Ilibmisc  -Wall -Wextra -Wshadow   -g -O2 -MD -c main.cc -o main.o
mv main.d dep/main.d
```

--------------------------------

### Worked Example: Compiling and Executing VPI Module

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

The sequence of shell commands to compile the C VPI source, compile the Verilog design, and then run the simulation with the loaded VPI module.

```Shell
% iverilog-vpi hello.c
% iverilog -ohello.vvp hello.v
% vvp -M. -mhello hello.vvp
```

--------------------------------

### Icarus Verilog Sizer Output Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-sizer.rst

Example output from the Icarus Verilog sizer after analyzing the provided Verilog code. It shows statistics for a module and overall totals.

```text
**** module/scope: top
     Flip-Flops   : 1
     Logic Gates  : 3
     MUX[2]: 1 slices
     LOG[13]: 1 unaccounted
     LOG[14]: 1 unaccounted
**** TOTALS
     Flip-Flops   : 1
     Logic Gates  : 3
     MUX[2]: 1 slices
     LOG[13]: 1 unaccounted
     LOG[14]: 1 unaccounted
```

--------------------------------

### Icarus Verilog Sizer Command Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-sizer.rst

Example command to invoke the Icarus Verilog sizer target. It synthesizes the Verilog code and outputs statistics to a file.

```bash
% iverilog -o sizer.txt -tsizer -S -s top input.v
```

--------------------------------

### Icarus Verilog Simulation Commands

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Provides the command-line instructions to compile and run a Verilog simulation using Icarus Verilog, specifically for the $readmemh example.

```bash
iverilog -osqrt_readmem.vvp sqrt_readmem.vl sqrt.vl
vvp sqrt_readmem.vvp
```

--------------------------------

### Icarus Verilog Core Compiler Process

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/index.rst

Explains the internal process of the Icarus Verilog core compiler ('ivl'), from lexical analysis and parsing to elaboration and code generation.

```Documentation
Abstract Process:
1. Lexical Analysis & Parsing: Generates an internal "pform" (decorated parse tree).
2. Elaboration: Transforms pform to "netlist" form (scope, parameter, signal, statement/expression elaboration).
3. Netlist Processing: Optimizations and optional synthesis.
4. Translation: Converts to "ivl_target" internal form.
5. Code Generation: Passes ivl_target form via ivl_target.h API to target generators.
```

--------------------------------

### Run Icarus Verilog Tests

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Command to execute a simple test suite for Icarus Verilog before installation, which can also provide guidance for running the tool on custom Verilog sources.

```bash
make check
```

--------------------------------

### Iverilog Test Configuration Example

Source: https://github.com/steveicarus/iverilog/blob/master/ivtest/vvp_tests/README.txt

An example of a JSON configuration file used to define a test case for the iverilog compiler. It specifies the test type, the Verilog source file, and the expected output file (gold file).

```JSON
{
    "type"   : "normal",
    "source" : "macro_str_esc.v",
    "gold"   : "macro_str_esc"
}
```

--------------------------------

### Verilog Module for Stub Generation Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-stub.rst

A simple Verilog module named 'top' that uses the $display system task to print 'Hello World!'. This module is used as an example input for the Icarus Verilog stub code generator.

```verilog
module top;
    initial $display("Hello World!");
endmodule
```

--------------------------------

### Icarus Verilog Compiler Components Overview

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/index.rst

Describes the main components of the Icarus Verilog compiler, including the driver, preprocessor, core compiler, and loadable code generators.

```Documentation
- The compiler driver (driver/)
  - Installs as "iverilog", handles command line arguments and orchestrates subcommands.
- The preprocessor (ivlpp/)
  - Implements Verilog preprocessor directives like `define, `include, `ifdef.
- The core compiler (root directory)
  - The "ivl" program, handles main Verilog compilation processing.
- The loadable code generators (tgt-*/)
  - Emit code for supported targets after parsing and semantic analysis.
  - tgt-vvp/ generates code for the vvp runtime.
```

--------------------------------

### Icarus Verilog Parsing Details

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/index.rst

Details the parsing phase of the Icarus Verilog core compiler, including the tools, input files, and the generated 'pform' structure.

```Documentation
Tools Used:
- bison: Parses "parse.y" to generate the parser.
- flex: Provides tokens to bison.
Output:
- Generates the "pform" (decorated parse tree).
Internal Structures:
- Parser functions in parse*.h, parse*.cc.
- pform.h, pform*.cc define the pform structure.
- Classes like PScope.h, Module.h, PGenerate.h, Statement.h, PExpr.h define pform elements.
```

--------------------------------

### Checkout Specific Branch

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Checks out a specific branch from the origin repository and sets up local tracking. This is useful for working on a particular version of the Icarus Verilog codebase.

```console
% git checkout --track -b v11-branch origin/v11-branch
```

--------------------------------

### Icarus Verilog Configure Script Options

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Details common flags for the configure script, such as setting the installation prefix, enabling/disabling suffixes for co-existence, and specifying the host platform for cross-compilation.

```text
	--prefix=<root>
		The default is /usr/local, which causes the tool suite to
		be compiled for install in /usr/local/bin,
		/usr/local/share/ivl, etc.

		I recommend that if you are configuring for precompiled
		binaries, use --prefix=/usr.  On Solaris systems, it is
		common to use --prefix=/opt.  You can configure for a non-root
		install with --prefix=$HOME.

	--enable-suffix
	--enable-suffix=<your-suffix>
	--disable-suffix
		Enable/disable changing the names of install files to use
		a suffix string so that this version or install can co-
		exist with other versions. This renames the installed
		commands (iverilog, iverilog-vpi, vvp) and the installed
		library files and include directory so that installations
		with the same prefix but different suffix are guaranteed
		to not interfere with each other.

	--host=<host-type>
		Compile iverilog for a different platform. You can use:
				x64_64-w64-mingw32 for building 64-bit Windows executables
				i686-w64-mingw32 for building 32-bit Windows executables
			Both options require installing the required mingw-w64 packages.
```

--------------------------------

### Example Compiler Invocation

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/reporting_issues.rst

Demonstrates common command-line invocations for the Icarus Verilog compiler, including output file specification and source file handling.

```bash
iverilog -o foo.out -tvvp foo.v
iverilog foo.vl -s starthere
```

--------------------------------

### Clone Icarus Verilog Repository

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Clones the Icarus Verilog source code from GitHub using the SSH method. This command assumes you have a GitHub account and have set up SSH authentication.

```console
% git clone git@github.com:steveicarus/iverilog.git
```

--------------------------------

### Icarus Verilog Runtime Components Overview

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/index.rst

Details the runtime components of Icarus Verilog, including the vvp runtime, system task implementations (VPI), PLI-1 compatibility, and Cadence PLI module compatibility.

```Documentation
- The vvp runtime (vvp/)
  - Implements the "vvp" command for runtime execution.
- The system tasks implementations (vpi/)
  - Implements standard Verilog system tasks using VPI (PLI-2).
- The PLI-1 compatibility library (libveriuser/)
  - Emulates deprecated PLI-1 using builtin PLI-2 support.
- The Cadence PLI module compatibility module (cadpli/)
  - Provides Cadence PLI interface for specialized situations (e.g., Verilog-XL code).
```

--------------------------------

### Push Branch to GitHub for Pull Request

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Pushes the local development branch to your GitHub fork. This makes the branch available on GitHub for creating a pull request against the upstream repository.

```git
% git push -u origin my-github-id/branch-name
```

--------------------------------

### Create a Git Branch for Contributions

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/getting_started.rst

Creates a new Git branch for development, following a naming convention that includes your GitHub ID and the feature name. This is a prerequisite for submitting pull requests.

```git
% git checkout -b my-github-id/branch-name
```

--------------------------------

### Worked Example: Hello World VPI Module (C Code)

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

The C source code for a simple VPI module that prints 'Hello, World!' to the simulation console. It includes the system task registration and the startup routines table.

```C
# include  <vpi_user.h>

  static int hello_compiletf(char*user_data)
  {
        (void)user_data; // Avoid a warning since user_data is not used.
        return 0;
  }

  static int hello_calltf(char*user_data)
  {
        (void)user_data; // Avoid a warning since user_data is not used.
        vpi_printf("Hello, World!\n");
        return 0;
  }

  void hello_register(void)
  {
        s_vpi_systf_data tf_data;

        tf_data.type      = vpiSysTask;
        tf_data.tfname    = "$hello";
        tf_data.calltf    = hello_calltf;
        tf_data.compiletf = hello_compiletf;
        tf_data.sizetf    = 0;
        tf_data.user_data = 0;
        vpi_register_systf(&tf_data);
  }

  void (*vlog_startup_routines[])(void) = {
      hello_register,
      0
  };
```

--------------------------------

### Loading VPI Modules with vvp

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

Demonstrates how to load a VPI module named 'sample.vpi' using the 'vvp' command with the '-m' switch.

```Shell
% vvp -msample foo.vvp
```

--------------------------------

### Windows Cross-Compilation Configuration

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/installation.rst

Configures the build process for cross-compiling Icarus Verilog for Windows using a mingw64 cross-compiler on a Linux system. It sets the host target for the configure script.

```shell
./configure --host=x86_64-w64-mingw32
```

--------------------------------

### Verilog Example and Generated vvp Output

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-vvp.rst

Provides a simple Verilog module 'top' that displays 'Hello World!' and shows the corresponding generated vvp code, including directives like ivl_version, timescale, and vpi_call for the $display system task.

```verilog
module top;
    initial $display("Hello World!");
endmodule
```

```vvp
#! /usr/local/bin/vvp
:ivl_version "13.0 (devel)" "(s20221226-119-g8cb2e1a05-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/local/lib/ivl/system.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/lib/ivl/va_math.vpi";
S_0x563c3c5d1540 .scope module, "top" "top" 2 1;
 .timescale 0 0;
        .scope S_0x563c3c5d1540;
T_0 ;
        %vpi_call 2 2 "$display", "Hello World!" {0 0 0};
        %end;
        .thread T_0;
# The file index is used to find the file name in the following table.
:file_names 3;
        "N/A";
        "<interactive>";
        "hello_world.v";
```

--------------------------------

### Compile Icarus Verilog from Release

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Instructions for compiling Icarus Verilog by unpacking a release tarball and running the configure and make commands.

```bash
tar -xf verilog-*.tar.gz
cd verilog-*
./configure
make
```

--------------------------------

### Uninstall Icarus Verilog

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Command to remove all files installed by the 'make install' target, ensuring a clean uninstallation.

```bash
make uninstall
```

--------------------------------

### Compile Icarus Verilog from GitHub

Source: https://github.com/steveicarus/iverilog/blob/master/README.md

Steps to compile Icarus Verilog from its GitHub repository, including generating the configure script before compilation.

```bash
sh autoconf.sh
./configure
make
```

--------------------------------

### Icarus Verilog Command Line Options

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/simulation.rst

Demonstrates command-line switches for the iverilog compiler, specifically for including directories in the preprocessor's search path and for specifying library directories.

```bash
% iverilog -I/directory/to/search example.v
% iverilog -y/library/to/search example.v
```

--------------------------------

### IVLPP Command Line Usage

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/ivlpp_flags.rst

Describes the basic usage of the ivlpp command, including the required file parameter and the redirection of output to standard output. It also lists and explains the available command-line options.

```bash
ivlpp [options] <file>
```

--------------------------------

### Verilog Module with EDIF Root Ports Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-fpga.rst

Presents a Verilog module with output and input ports, similar to the XNF example, to demonstrate EDIF port generation.

```verilog
module main(out, in);
    output out;
    input [2:0] in;
    [...]
endmodule
```

--------------------------------

### VVP Labels and Symbols

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/vvp/vvp.rst

Details the allowed characters for labels and symbols (alphanumeric plus .$_<>) and the rules for their formation, including restrictions on starting characters and the distinction between labels (statement start) and symbols (operands).

```vvp
Labels and symbols consist of the characters::
	a-z
	A-Z
	0-9
	.$_<>
```

```vvp
Labels and symbols may not start with a digit or a '.', so that they are easily distinguished from keywords and numbers.
```

```vvp
A Label is a symbol that starts a statement. If a label is present in a statement, it must start in the first text column.
```

```vvp
If a symbol is present in a statement, it is in the operand. Opcodes of statements must be a keyword.
```

```vvp
Special symbols like "C<0>", "C<1>", "C<x>" and "C<z>" represent constant drivers.
```

--------------------------------

### VPI Startup Routines Table Definition

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/usage/vpi.rst

A C code snippet showing the definition of the 'vlog_startup_routines' table, which is a null-terminated array of function pointers used by the simulator to discover VPI module functions.

```C
void (*vlog_startup_routines[])(void) = {
     hello_register,
     0
  };
```

--------------------------------

### Stub Code Generator Output Example

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/targets/tgt-stub.rst

The expected text dump of the elaborated design generated by the Icarus Verilog stub code generator for the provided example Verilog module. It details the module structure, scope, and the initial block's execution.

```text
root module = top
scope: top (0 parameters, 0 signals, 0 logic) module top time units = 1e0
 time precision = 1e0
end scope top
# There are 0 constants detected
initial
    Call $display(1 parameters); /* hello_world.v:2 */
        <string="Hello World!", width=96, type=bool>
```

--------------------------------

### Uninstall Solaris Package

Source: https://github.com/steveicarus/iverilog/blob/master/solaris/README-solaris_pkg.txt

Instructions for uninstalling an Iverilog Solaris package using the 'pkgrm' command.

```bash
pkgrm IVLver
```

--------------------------------

### Iverilog String Loading

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/guide/vvp/opcodes.rst

Gets a string from a string variable and pushes it onto the string stack. Related to %store/str.

```iverilog
%load/str <var-label>
```

--------------------------------

### Regression Test List Entry

Source: https://github.com/steveicarus/iverilog/blob/master/Documentation/developer/regression_tests.rst

An example of a line in the regress-vvp.list file, specifying a test name and its corresponding description file.

```console
macro_str_esc  vvp_tests/macro_str_esc.json
```