PicoRV32

https://github.com/yosyshq/picorv32
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PicoRV32 is a size-optimized CPU core implementing the RISC-V RV32IMC instruction set, primarily...
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### Timer Instruction Format

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Instruction format and example for the PicoRV32 timer.

```text
0000101 ----- XXXXX --- XXXXX 0001011
f7      rs2   rs    f3  rd    opcode
```

```text
timer x1, x2
```

--------------------------------

### Custom Instruction Encoding and Usage

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Shows the bit-field encoding for custom instructions and an example of the getq instruction usage.

```text
0000000 ----- 000XX --- XXXXX 0001011
f7      rs2   qs    f3  rd    opcode
```

```asm
getq x5, q2
```

--------------------------------

### Build Toolchain Commands

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Commands to download and build the complete toolchain.

```bash
make download-tools
make -j$(nproc) build-tools
```

--------------------------------

### Build LED-blinking firmware and timing report

Source: https://github.com/yosyshq/picorv32/blob/main/scripts/icestorm/readme.md

Compiles the firmware for the HX8K Breakout Board and generates a timing report based on the 12MHz oscillator.

```bash
$ make clean example.bin timing
```

--------------------------------

### PicoRV32 Makefile Targets

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Available make targets for building specific RV32 toolchains.

```bash
make -j$(nproc) build-riscv32i-tools
make -j$(nproc) build-riscv32ic-tools
make -j$(nproc) build-riscv32im-tools
make -j$(nproc) build-riscv32imc-tools
```

```bash
make -j$(nproc) build-tools
```

```bash
make download-tools
```

--------------------------------

### Build Pure RV32I Toolchain

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Detailed steps to build the RISC-V GNU toolchain for a pure RV32I target.

```bash
# Ubuntu packages needed:
sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
        libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
	    gperf libtool patchutils bc zlib1g-dev git libexpat1-dev

sudo mkdir /opt/riscv32i
sudo chown $USER /opt/riscv32i

git clone https://github.com/riscv-collab/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
cd riscv-gnu-toolchain-rv32i
git checkout 411d134
git submodule update --init --recursive

mkdir build; cd build
../configure --with-arch=rv32i --prefix=/opt/riscv32i
make -j$(nproc)
```

--------------------------------

### Navigate Tcl Console Directories

Source: https://github.com/yosyshq/picorv32/wiki/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board

Use standard Tcl commands to manage the working directory within the Vivado Tcl console.

```tcl
cd
```

```tcl
pwd
```

--------------------------------

### Run simulation tests

Source: https://github.com/yosyshq/picorv32/blob/main/scripts/icestorm/readme.md

Executes simulation tests with a specified counter bit parameter. The clean target is required to ensure the firmware is rebuilt correctly for simulation.

```bash
$ make clean example_sim synth_sim route_sim FIRMWARE_COUNTER_BITS=4
```

--------------------------------

### Pico Co-Processor Interface (PCPI) Signals

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Lists the input and output signals required to implement non-branching instructions in external co-processor cores.

```verilog
output        pcpi_valid
output [31:0] pcpi_insn
output [31:0] pcpi_rs1
output [31:0] pcpi_rs2
input         pcpi_wr
input  [31:0] pcpi_rd
input         pcpi_wait
input         pcpi_ready
```

--------------------------------

### PicoRV32 Native Memory Interface Signals

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

The native memory interface uses a valid-ready handshake protocol for memory transfers.

```verilog
    output        mem_valid
    output        mem_instr
    input         mem_ready

    output [31:0] mem_addr
    output [31:0] mem_wdata
    output [ 3:0] mem_wstrb
    input  [31:0] mem_rdata
```

--------------------------------

### setq qd, rs

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Copies the value from a general-purpose register to a q-register.

```APIDOC
## setq qd, rs

### Description
Copies the value from a general-purpose register to a q-register.

### Example
setq q2, x5
```

--------------------------------

### Set Q-Register Instruction

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Copies a value from a general-purpose register to a q-register.

```assembly
setq q2, x5
```

--------------------------------

### Configure XDC Constraints for Nexys 4 DDR

Source: https://github.com/yosyshq/picorv32/wiki/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board

Define pin assignments and clock constraints for the Nexys 4 DDR board in the XDC file.

```xdc
# XDC File for Nexys 4 DDR Board
###########################

set_property PACKAGE_PIN D5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.00 [get_ports clk]

# Pmod Header JA (JA0..JA7)
set_property PACKAGE_PIN K1 [get_ports {out_byte[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
set_property PACKAGE_PIN J3 [get_ports {out_byte[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]

# Pmod Header JB (JB0..JB2)
set_property PACKAGE_PIN A14 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
set_property PACKAGE_PIN A16 [get_ports {trap}]
set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
set_property PACKAGE_PIN B14 [get_ports {out_byte_en}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
```

--------------------------------

### Look-Ahead Memory Interface Signals

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Defines the output signals for the Look-Ahead Memory Interface, which provides memory transfer information one clock cycle early.

```verilog
output        mem_la_read
output        mem_la_write
output [31:0] mem_la_addr
output [31:0] mem_la_wdata
output [ 3:0] mem_la_wstrb
```

--------------------------------

### Return from Interrupt Instruction

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Copies the value from q0 to the program counter and re-enables interrupts.

```assembly
retirq
```

--------------------------------

### Update Vivado Synthesis Target Device

Source: https://github.com/yosyshq/picorv32/wiki/Programming-the-Nexys-4-DDR-Artix-7-FPGA-Trainer-Board

Modify the synth_design command in the Tcl script to match the specific FPGA part on the Nexys 4 DDR board.

```tcl
synth_design -part xc7k70t-fbg676 -top system
```

```tcl
synth_design -part xc7a100tcsg324-1 -top system
```

--------------------------------

### retirq

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Return from interrupt. Copies the value from q0 to the program counter and re-enables interrupts.

```APIDOC
## retirq

### Description
Return from interrupt. This instruction copies the value from q0 to the program counter and re-enables interrupts.

### Example
retirq
```

--------------------------------

### Wait for Interrupt Instruction

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Pauses execution until an interrupt becomes pending, writing the pending IRQ bitmask to the destination register.

```assembly
waitirq x1
```

--------------------------------

### waitirq rd

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Pause execution until an interrupt becomes pending. The bitmask of pending IRQs is written to rd.

```APIDOC
## waitirq rd

### Description
Pause execution until an interrupt becomes pending. The bitmask of pending IRQs is written to rd.

### Example
waitirq x1
```

--------------------------------

### maskirq rd, rs

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Writes a new value to the IRQ mask register and reads the old value.

```APIDOC
## maskirq rd, rs

### Description
The IRQ Mask register contains a bitmask of masked (disabled) interrupts. This instruction writes a new value to the irq mask register and reads the old value.

### Example
maskirq x1, x2
```

--------------------------------

### Mask Interrupts Instruction

Source: https://github.com/yosyshq/picorv32/blob/main/README.md

Writes a new value to the IRQ mask register and reads the previous value.

```assembly
maskirq x1, x2
```
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