Project Apicula

https://github.com/yosyshq/apicula
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Project Apicula provides open-source tools and documentation for the Gowin FPGA bitstream format,...
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### Example: Write to Flash on Tang Nano 9K

Source: https://github.com/yosyshq/apicula/wiki/OpenFPGALoader

Example of writing a design to flash on a Tang Nano 9K board using the -f flag.

```bash
openFPGALoader -b tangnano9k -f your_design.fs
```

--------------------------------

### Install apycula with pip

Source: https://github.com/yosyshq/apicula/blob/master/readme.md

Install the apycula package using pip. This is the standard installation method.

```bash
pip install apycula
```

--------------------------------

### OPEN_DRAIN=ON example (ON fuse)

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for OPEN_DRAIN=ON with the ON fuse on GW1N-1. The key is [10, 55, 70, ...] and the fuses list is [3273, -1, ...].

```text
[10, 55, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3273, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### Example: Write to SRAM on Tang Nano 9K

Source: https://github.com/yosyshq/apicula/wiki/OpenFPGALoader

Example of writing a design to SRAM on a Tang Nano 9K board using the board flag 'tangnano9k'.

```bash
openFPGALoader -b tangnano9k your_design.fs
```

--------------------------------

### nextpnr-himbaechel for standard devices

Source: https://github.com/yosyshq/apicula/wiki/Nextpnr‐Himbaechel-Gowin

Example for standard devices that do not require the family option, such as Tang Nano, Tang Nano 1K, Tang Nano 4K, and Runber.

```bash
nextpnr-himbaechel --json design.json \
                   --write output.json \
                   --device $DEVICE \
                   --vopt cst=$BOARD.cst
```

--------------------------------

### OPEN_DRAIN=ON example (NOISE fuse)

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for OPEN_DRAIN=ON with the NOISE fuse on GW1N-1. The key is [7, 55, 72, ...] and the fuses list is [3238, 3263, 3273, 3281, -1, ...].

```text
[7, 55, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3238, 3263, 3273, 3281, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### DCS Verilog Instantiation

Source: https://github.com/yosyshq/apicula/wiki/DCS

Verilog instantiation example for the Gowin DCS primitive, showing how to connect the clock inputs, clock output, and control signals.

```APIDOC
## DCS Primitive

### Description
The Gowin DCS (Dynamic Clock Selector) primitive dynamically switches between four clock inputs (GCLK0-GCLK3) using a CRU. It supports two switching modes: Non-glitchless and Glitchless.

### Ports
- **CLK0** (1-bit input) - Clock input 0
- **CLK1** (1-bit input) - Clock input 1
- **CLK2** (1-bit input) - Clock input 2
- **CLK3** (1-bit input) - Clock input 3
- **CLKOUT** (1-bit output) - Selected clock output
- **CLKSEL** (4-bit input) - Clock select signal
- **SELFORCE** (1-bit input) - Force selection signal

### Parameters
- **DCS_MODE** (default: RISING) - Sets the clock switching mode (e.g., Non-glitchless or Glitchless).

### Verilog Instantiation
```verilog
DCS #(
    .DCS_MODE(DCS_MODE)
) dcs_inst (
    .CLK0(CLK0),
    .CLK1(CLK1),
    .CLK2(CLK2),
    .CLK3(CLK3),
    .CLKOUT(CLKOUT),
    .CLKSEL(CLKSEL),
    .SELFORCE(SELFORCE)
);
```
```

--------------------------------

### Check and add installed binaries to PATH

Source: https://github.com/yosyshq/apicula/blob/master/readme.md

Commands to verify that the installed binaries are on the PATH and to add them if necessary. Running the source files directly will lead to import errors.

```bash
which gowin_pack # check if binaries are on the path
python -m site --user-base # find the site packages base directory
ls $HOME/.local/bin # confirm the binaries are installed in this folder
export PATH="$HOME/.local/bin:$PATH" # add binaries to the path
```

--------------------------------

### Run fuzzers with pip install and make

Source: https://github.com/yosyshq/apicula/blob/master/readme.md

Run the fuzzers and build the ChipDB in a checkout of this repo. Requires Gowin vendor tools version 1.9.10.03 (newer versions may work but are untested) and sets GOWINHOME to the Gowin installation directory.

```bash
pip install -e .
export GOWINHOME=/gowin/installation
make
```

--------------------------------

### Install apycula with pure Python alternatives

Source: https://github.com/yosyshq/apicula/blob/master/readme.md

Use this command on platforms where the default C extension dependencies are not available. It installs apycula without dependencies and adds msgpack and cattrs as pure Python alternatives.

```bash
pip install --no-deps apycula msgpack cattrs
```

--------------------------------

### Build blinky for Tangnano9k with family flag

Source: https://github.com/yosyshq/apicula/blob/master/readme.md

For the Tangnano9k board, nextpnr and gowin_pack must be called with the chip family GW1N-9C. The device variable is assumed to be set as in the previous example.

```bash
nextpnr-himbaechel --json blinky.json \
                   --write pnrblinky.json \
                   --device $DEVICE \
                   --vopt family=GW1N-9C \
                   --vopt cst=$BOARD.cst
gowin_pack -d GW1N-9C -o pack.fs pnrblinky.json
```

--------------------------------

### Basic Gowin FPGA flow: synthesize, place and route, pack, and program

Source: https://github.com/yosyshq/apicula/wiki/Home

Commands to run the complete open source FPGA development flow for Gowin FPGAs: synthesize Verilog to JSON with Yosys, place and route with nextpnr-himbaechel, generate bitstream with gowin_pack, and program with openFPGALoader. The example uses a Tang Nano 9K board and a GW1NR-LV9QN88PC6/I5 device.

```bash
# 1. Synthesize Verilog to JSON netlist
yosys -p "read_verilog design.v; synth_gowin -json design.json"

# 2. Place and route the design
nextpnr-himbaechel --json design.json --write placed.json \
                   --device GW1NR-LV9QN88PC6/I5 \
                   --vopt cst=constraints.cst

# 3. Generate bitstream
gowin_pack -d GW1N-9C -o final.fs placed.json

# 4. Program the FPGA
openFPGALoader -b tangnano9k final.fs
```

--------------------------------

### SLEW_RATE=FAST example

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for SLEW_RATE=FAST on GW1N-1. The key is [42, 0, ...] and the fuses list is [3377, -1, ...].

```text
[42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3377, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### PULL_MODE=DOWN example

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for PULL_MODE=DOWN on GW1N-1. The key is [43, 0, ...] and the fuses list is [3342, 3357, -1, ...].

```text
[43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3342, 3357, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### Instantiate SDP36KE primitive with all parameters and ports

Source: https://github.com/yosyshq/apicula/wiki/SDP

Use this Verilog instantiation to include the SDP36KE dual-port RAM primitive in a design. It lists all configuration parameters (BLK_SEL_A/B, ECC_READ_EN, ECC_WRITE_EN, INITP_RAM_*, INIT_FILE, INIT_RAM_*, READ_MODE, RESET_MODE) and all ports (ADA, ADB, BLKSELA, BLKSELB, CEA, CEB, CLKA, CLKB, DECCI, DECCO, DI, DIP, DO, DOP). The instance name is sdp36ke_inst.

```verilog
SDP36KE #(
    .BLK_SEL_A(BLK_SEL_A),
    .BLK_SEL_B(BLK_SEL_B),
    .ECC_READ_EN(ECC_READ_EN),
    .ECC_WRITE_EN(ECC_WRITE_EN),
    .INITP_RAM_00(INITP_RAM_00),
    .INITP_RAM_01(INITP_RAM_01),
    .INITP_RAM_02(INITP_RAM_02),
    .INITP_RAM_03(INITP_RAM_03),
    .INITP_RAM_04(INITP_RAM_04),
    .INITP_RAM_05(INITP_RAM_05),
    .INITP_RAM_06(INITP_RAM_06),
    .INITP_RAM_07(INITP_RAM_07),
    .INITP_RAM_08(INITP_RAM_08),
    .INITP_RAM_09(INITP_RAM_09),
    .INITP_RAM_0A(INITP_RAM_0A),
    .INITP_RAM_0B(INITP_RAM_0B),
    .INITP_RAM_0C(INITP_RAM_0C),
    .INITP_RAM_0D(INITP_RAM_0D),
    .INITP_RAM_0E(INITP_RAM_0E),
    .INITP_RAM_0F(INITP_RAM_0F),
    .INIT_FILE(INIT_FILE),
    .INIT_RAM_00(INIT_RAM_00),
    .INIT_RAM_01(INIT_RAM_01),
    .INIT_RAM_02(INIT_RAM_02),
    .INIT_RAM_03(INIT_RAM_03),
    .INIT_RAM_04(INIT_RAM_04),
    .INIT_RAM_05(INIT_RAM_05),
    .INIT_RAM_06(INIT_RAM_06),
    .INIT_RAM_07(INIT_RAM_07),
    .INIT_RAM_08(INIT_RAM_08),
    .INIT_RAM_09(INIT_RAM_09),
    .INIT_RAM_0A(INIT_RAM_0A),
    .INIT_RAM_0B(INIT_RAM_0B),
    .INIT_RAM_0C(INIT_RAM_0C),
    .INIT_RAM_0D(INIT_RAM_0D),
    .INIT_RAM_0E(INIT_RAM_0E),
    .INIT_RAM_0F(INIT_RAM_0F),
    .INIT_RAM_10(INIT_RAM_10),
    .INIT_RAM_11(INIT_RAM_11),
    .INIT_RAM_12(INIT_RAM_12),
    .INIT_RAM_13(INIT_RAM_13),
    .INIT_RAM_14(INIT_RAM_14),
    .INIT_RAM_15(INIT_RAM_15),
    .INIT_RAM_16(INIT_RAM_16),
    .INIT_RAM_17(INIT_RAM_17),
    .INIT_RAM_18(INIT_RAM_18),
    .INIT_RAM_19(INIT_RAM_19),
    .INIT_RAM_1A(INIT_RAM_1A),
    .INIT_RAM_1B(INIT_RAM_1B),
    .INIT_RAM_1C(INIT_RAM_1C),
    .INIT_RAM_1D(INIT_RAM_1D),
    .INIT_RAM_1E(INIT_RAM_1E),
    .INIT_RAM_1F(INIT_RAM_1F),
    .INIT_RAM_20(INIT_RAM_20),
    .INIT_RAM_21(INIT_RAM_21),
    .INIT_RAM_22(INIT_RAM_22),
    .INIT_RAM_23(INIT_RAM_23),
    .INIT_RAM_24(INIT_RAM_24),
    .INIT_RAM_25(INIT_RAM_25),
    .INIT_RAM_26(INIT_RAM_26),
    .INIT_RAM_27(INIT_RAM_27),
    .INIT_RAM_28(INIT_RAM_28),
    .INIT_RAM_29(INIT_RAM_29),
    .INIT_RAM_2A(INIT_RAM_2A),
    .INIT_RAM_2B(INIT_RAM_2B),
    .INIT_RAM_2C(INIT_RAM_2C),
    .INIT_RAM_2D(INIT_RAM_2D),
    .INIT_RAM_2E(INIT_RAM_2E),
    .INIT_RAM_2F(INIT_RAM_2F),
    .INIT_RAM_30(INIT_RAM_30),
    .INIT_RAM_31(INIT_RAM_31),
    .INIT_RAM_32(INIT_RAM_32),
    .INIT_RAM_33(INIT_RAM_33),
    .INIT_RAM_34(INIT_RAM_34),
    .INIT_RAM_35(INIT_RAM_35),
    .INIT_RAM_36(INIT_RAM_36),
    .INIT_RAM_37(INIT_RAM_37),
    .INIT_RAM_38(INIT_RAM_38),
    .INIT_RAM_39(INIT_RAM_39),
    .INIT_RAM_3A(INIT_RAM_3A),
    .INIT_RAM_3B(INIT_RAM_3B),
    .INIT_RAM_3C(INIT_RAM_3C),
    .INIT_RAM_3D(INIT_RAM_3D),
    .INIT_RAM_3E(INIT_RAM_3E),
    .INIT_RAM_3F(INIT_RAM_3F),
    .INIT_RAM_40(INIT_RAM_40),
    .INIT_RAM_41(INIT_RAM_41),
    .INIT_RAM_42(INIT_RAM_42),
    .INIT_RAM_43(INIT_RAM_43),
    .INIT_RAM_44(INIT_RAM_44),
    .INIT_RAM_45(INIT_RAM_45),
    .INIT_RAM_46(INIT_RAM_46),
    .INIT_RAM_47(INIT_RAM_47),
    .INIT_RAM_48(INIT_RAM_48),
    .INIT_RAM_49(INIT_RAM_49),
    .INIT_RAM_4A(INIT_RAM_4A),
    .INIT_RAM_4B(INIT_RAM_4B),
    .INIT_RAM_4C(INIT_RAM_4C),
    .INIT_RAM_4D(INIT_RAM_4D),
    .INIT_RAM_4E(INIT_RAM_4E),
    .INIT_RAM_4F(INIT_RAM_4F),
    .INIT_RAM_50(INIT_RAM_50),
    .INIT_RAM_51(INIT_RAM_51),
    .INIT_RAM_52(INIT_RAM_52),
    .INIT_RAM_53(INIT_RAM_53),
    .INIT_RAM_54(INIT_RAM_54),
    .INIT_RAM_55(INIT_RAM_55),
    .INIT_RAM_56(INIT_RAM_56),
    .INIT_RAM_57(INIT_RAM_57),
    .INIT_RAM_58(INIT_RAM_58),
    .INIT_RAM_59(INIT_RAM_59),
    .INIT_RAM_5A(INIT_RAM_5A),
    .INIT_RAM_5B(INIT_RAM_5B),
    .INIT_RAM_5C(INIT_RAM_5C),
    .INIT_RAM_5D(INIT_RAM_5D),
    .INIT_RAM_5E(INIT_RAM_5E),
    .INIT_RAM_5F(INIT_RAM_5F),
    .INIT_RAM_60(INIT_RAM_60),
    .INIT_RAM_61(INIT_RAM_61),
    .INIT_RAM_62(INIT_RAM_62),
    .INIT_RAM_63(INIT_RAM_63),
    .INIT_RAM_64(INIT_RAM_64),
    .INIT_RAM_65(INIT_RAM_65),
    .INIT_RAM_66(INIT_RAM_66),
    .INIT_RAM_67(INIT_RAM_67),
    .INIT_RAM_68(INIT_RAM_68),
    .INIT_RAM_69(INIT_RAM_69),
    .INIT_RAM_6A(INIT_RAM_6A),
    .INIT_RAM_6B(INIT_RAM_6B),
    .INIT_RAM_6C(INIT_RAM_6C),
    .INIT_RAM_6D(INIT_RAM_6D),
    .INIT_RAM_6E(INIT_RAM_6E),
    .INIT_RAM_6F(INIT_RAM_6F),
    .INIT_RAM_70(INIT_RAM_70),
    .INIT_RAM_71(INIT_RAM_71),
    .INIT_RAM_72(INIT_RAM_72),
    .INIT_RAM_73(INIT_RAM_73),
    .INIT_RAM_74(INIT_RAM_74),
    .INIT_RAM_75(INIT_RAM_75),
    .INIT_RAM_76(INIT_RAM_76),
    .INIT_RAM_77(INIT_RAM_77),
    .INIT_RAM_78(INIT_RAM_78),
    .INIT_RAM_79(INIT_RAM_79),
    .INIT_RAM_7A(INIT_RAM_7A),
    .INIT_RAM_7B(INIT_RAM_7B),
    .INIT_RAM_7C(INIT_RAM_7C),
    .INIT_RAM_7D(INIT_RAM_7D),
    .INIT_RAM_7E(INIT_RAM_7E),
    .INIT_RAM_7F(INIT_RAM_7F),
    .READ_MODE(READ_MODE),
    .RESET_MODE(RESET_MODE)
) sdp36ke_inst (
    .ADA(ADA),
    .ADB(ADB),
    .BLKSELA(BLKSELA),
    .BLKSELB(BLKSELB),
    .CEA(CEA),
    .CEB(CEB),
    .CLKA(CLKA),
    .CLKB(CLKB),
    .DECCI(DECCI),
    .DECCO(DECCO),
    .DI(DI),
    .DIP(DIP),
    .DO(DO),
    .DOP(DOP),

```

--------------------------------

### Basic nextpnr-himbaechel usage

Source: https://github.com/yosyshq/apicula/wiki/Nextpnr‐Himbaechel-Gowin

Basic command-line invocation for nextpnr-himbaechel with Gowin FPGAs. Requires --json, --write, --device, and --vopt cst=<file> options.

```bash
nextpnr-himbaechel --json input.json --write output.json --device <device-part> --vopt cst=<board>.cst [options]
```

--------------------------------

### HYSTERESIS=HIGH example

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for HYSTERESIS=HIGH on GW1N-1. The key includes the ignored feature code 37, and the fuses list is [3352, 3374, -1, ...].

```text
[37, 57, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3352, 3374, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### Complete Example: Compressed bitstream with GPIO configuration

Source: https://github.com/yosyshq/apicula/wiki/gowin_pack

Generates a compressed bitstream with custom output and configures JTAG, MSPI, DONE, and RECONFIG_N pins as GPIO. Warning: These flags disable programming and reconfiguration functionality; use with caution.

```bash
gowin_pack --device GW1N-9C design.json \
  --output final.fs \
  --compress \
  --jtag_as_gpio \
  --mspi_as_gpio \
  --done_as_gpio
```

--------------------------------

### Instantiate SDPB primitive in Verilog

Source: https://github.com/yosyshq/apicula/wiki/SDP

Verilog instantiation template for the SDPB primitive. It connects all configuration parameters (BIT_WIDTH_0/1, BLK_SEL_0/1, INIT_RAM_00 through INIT_RAM_3F, READ_MODE, RESET_MODE) and all I/O ports (ADA, ADB, BLKSELA, BLKSELB, CEA, CEB, CLKA, CLKB, DI, DO, OCE, RESET). Use this as a starting point for instantiating SDPB in your design.

```verilog
SDPB #(
    .BIT_WIDTH_0(BIT_WIDTH_0),
    .BIT_WIDTH_1(BIT_WIDTH_1),
    .BLK_SEL_0(BLK_SEL_0),
    .BLK_SEL_1(BLK_SEL_1),
    .INIT_RAM_00(INIT_RAM_00),
    .INIT_RAM_01(INIT_RAM_01),
    .INIT_RAM_02(INIT_RAM_02),
    .INIT_RAM_03(INIT_RAM_03),
    .INIT_RAM_04(INIT_RAM_04),
    .INIT_RAM_05(INIT_RAM_05),
    .INIT_RAM_06(INIT_RAM_06),
    .INIT_RAM_07(INIT_RAM_07),
    .INIT_RAM_08(INIT_RAM_08),
    .INIT_RAM_09(INIT_RAM_09),
    .INIT_RAM_0A(INIT_RAM_0A),
    .INIT_RAM_0B(INIT_RAM_0B),
    .INIT_RAM_0C(INIT_RAM_0C),
    .INIT_RAM_0D(INIT_RAM_0D),
    .INIT_RAM_0E(INIT_RAM_0E),
    .INIT_RAM_0F(INIT_RAM_0F),
    .INIT_RAM_10(INIT_RAM_10),
    .INIT_RAM_11(INIT_RAM_11),
    .INIT_RAM_12(INIT_RAM_12),
    .INIT_RAM_13(INIT_RAM_13),
    .INIT_RAM_14(INIT_RAM_14),
    .INIT_RAM_15(INIT_RAM_15),
    .INIT_RAM_16(INIT_RAM_16),
    .INIT_RAM_17(INIT_RAM_17),
    .INIT_RAM_18(INIT_RAM_18),
    .INIT_RAM_19(INIT_RAM_19),
    .INIT_RAM_1A(INIT_RAM_1A),
    .INIT_RAM_1B(INIT_RAM_1B),
    .INIT_RAM_1C(INIT_RAM_1C),
    .INIT_RAM_1D(INIT_RAM_1D),
    .INIT_RAM_1E(INIT_RAM_1E),
    .INIT_RAM_1F(INIT_RAM_1F),
    .INIT_RAM_20(INIT_RAM_20),
    .INIT_RAM_21(INIT_RAM_21),
    .INIT_RAM_22(INIT_RAM_22),
    .INIT_RAM_23(INIT_RAM_23),
    .INIT_RAM_24(INIT_RAM_24),
    .INIT_RAM_25(INIT_RAM_25),
    .INIT_RAM_26(INIT_RAM_26),
    .INIT_RAM_27(INIT_RAM_27),
    .INIT_RAM_28(INIT_RAM_28),
    .INIT_RAM_29(INIT_RAM_29),
    .INIT_RAM_2A(INIT_RAM_2A),
    .INIT_RAM_2B(INIT_RAM_2B),
    .INIT_RAM_2C(INIT_RAM_2C),
    .INIT_RAM_2D(INIT_RAM_2D),
    .INIT_RAM_2E(INIT_RAM_2E),
    .INIT_RAM_2F(INIT_RAM_2F),
    .INIT_RAM_30(INIT_RAM_30),
    .INIT_RAM_31(INIT_RAM_31),
    .INIT_RAM_32(INIT_RAM_32),
    .INIT_RAM_33(INIT_RAM_33),
    .INIT_RAM_34(INIT_RAM_34),
    .INIT_RAM_35(INIT_RAM_35),
    .INIT_RAM_36(INIT_RAM_36),
    .INIT_RAM_37(INIT_RAM_37),
    .INIT_RAM_38(INIT_RAM_38),
    .INIT_RAM_39(INIT_RAM_39),
    .INIT_RAM_3A(INIT_RAM_3A),
    .INIT_RAM_3B(INIT_RAM_3B),
    .INIT_RAM_3C(INIT_RAM_3C),
    .INIT_RAM_3D(INIT_RAM_3D),
    .INIT_RAM_3E(INIT_RAM_3E),
    .INIT_RAM_3F(INIT_RAM_3F),
    .READ_MODE(READ_MODE),
    .RESET_MODE(RESET_MODE)
) sdpb_inst (
    .ADA(ADA),
    .ADB(ADB),
    .BLKSELA(BLKSELA),
    .BLKSELB(BLKSELB),
    .CEA(CEA),
    .CEB(CEB),
    .CLKA(CLKA),
    .CLKB(CLKB),
    .DI(DI),
    .DO(DO),
    .OCE(OCE),
    .RESET(RESET)
);
```

--------------------------------

### IO_TYPE=LVCMOS15 corner tile example

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for IO_TYPE=LVCMOS15 in corner tile table 37 on GW1N-1. The key is [2, 65, ...] and the fuses list is [2797, 2813, -1, ...].

```text
[2, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2797, 2813, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### IO_TYPE=LVCMOS18, DRIVE=8 example

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for IO_TYPE=LVCMOS18 and DRIVE=8 on GW1N-1. The key is [12, 50, 56, 66, ...] and the fuses list is [3356, 3372, 3375, 3379, 3394, 3397, -1, ...].

```text
[12, 50, 56, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3356, 3372, 3375, 3379, 3394, 3397, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### IO_TYPE=SSTL15 corner tile example (Fuse 79)

Source: https://github.com/yosyshq/apicula/blob/master/doc/longval-tables.md

Example table entry for IO_TYPE=SSTL15 in corner tile table 37, showing the fuse 79 part. The key is [3, 79, ...] and the fuses list is [2229, -1, ...].

```text
[3, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2229, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
```

--------------------------------

### Instantiate DP primitive with all parameters and ports

Source: https://github.com/yosyshq/apicula/wiki/DP

Use this Verilog instantiation to connect the DP primitive in your design. All parameters and ports are listed; replace the placeholder signals with your actual nets. The INIT_RAM_00 through INIT_RAM_3F parameters initialize the RAM contents.

```verilog
DP #(
    .BIT_WIDTH_0(BIT_WIDTH_0),
    .BIT_WIDTH_1(BIT_WIDTH_1),
    .BLK_SEL(BLK_SEL),
    .INIT_RAM_00(INIT_RAM_00),
    .INIT_RAM_01(INIT_RAM_01),
    .INIT_RAM_02(INIT_RAM_02),
    .INIT_RAM_03(INIT_RAM_03),
    .INIT_RAM_04(INIT_RAM_04),
    .INIT_RAM_05(INIT_RAM_05),
    .INIT_RAM_06(INIT_RAM_06),
    .INIT_RAM_07(INIT_RAM_07),
    .INIT_RAM_08(INIT_RAM_08),
    .INIT_RAM_09(INIT_RAM_09),
    .INIT_RAM_0A(INIT_RAM_0A),
    .INIT_RAM_0B(INIT_RAM_0B),
    .INIT_RAM_0C(INIT_RAM_0C),
    .INIT_RAM_0D(INIT_RAM_0D),
    .INIT_RAM_0E(INIT_RAM_0E),
    .INIT_RAM_0F(INIT_RAM_0F),
    .INIT_RAM_10(INIT_RAM_10),
    .INIT_RAM_11(INIT_RAM_11),
    .INIT_RAM_12(INIT_RAM_12),
    .INIT_RAM_13(INIT_RAM_13),
    .INIT_RAM_14(INIT_RAM_14),
    .INIT_RAM_15(INIT_RAM_15),
    .INIT_RAM_16(INIT_RAM_16),
    .INIT_RAM_17(INIT_RAM_17),
    .INIT_RAM_18(INIT_RAM_18),
    .INIT_RAM_19(INIT_RAM_19),
    .INIT_RAM_1A(INIT_RAM_1A),
    .INIT_RAM_1B(INIT_RAM_1B),
    .INIT_RAM_1C(INIT_RAM_1C),
    .INIT_RAM_1D(INIT_RAM_1D),
    .INIT_RAM_1E(INIT_RAM_1E),
    .INIT_RAM_1F(INIT_RAM_1F),
    .INIT_RAM_20(INIT_RAM_20),
    .INIT_RAM_21(INIT_RAM_21),
    .INIT_RAM_22(INIT_RAM_22),
    .INIT_RAM_23(INIT_RAM_23),
    .INIT_RAM_24(INIT_RAM_24),
    .INIT_RAM_25(INIT_RAM_25),
    .INIT_RAM_26(INIT_RAM_26),
    .INIT_RAM_27(INIT_RAM_27),
    .INIT_RAM_28(INIT_RAM_28),
    .INIT_RAM_29(INIT_RAM_29),
    .INIT_RAM_2A(INIT_RAM_2A),
    .INIT_RAM_2B(INIT_RAM_2B),
    .INIT_RAM_2C(INIT_RAM_2C),
    .INIT_RAM_2D(INIT_RAM_2D),
    .INIT_RAM_2E(INIT_RAM_2E),
    .INIT_RAM_2F(INIT_RAM_2F),
    .INIT_RAM_30(INIT_RAM_30),
    .INIT_RAM_31(INIT_RAM_31),
    .INIT_RAM_32(INIT_RAM_32),
    .INIT_RAM_33(INIT_RAM_33),
    .INIT_RAM_34(INIT_RAM_34),
    .INIT_RAM_35(INIT_RAM_35),
    .INIT_RAM_36(INIT_RAM_36),
    .INIT_RAM_37(INIT_RAM_37),
    .INIT_RAM_38(INIT_RAM_38),
    .INIT_RAM_39(INIT_RAM_39),
    .INIT_RAM_3A(INIT_RAM_3A),
    .INIT_RAM_3B(INIT_RAM_3B),
    .INIT_RAM_3C(INIT_RAM_3C),
    .INIT_RAM_3D(INIT_RAM_3D),
    .INIT_RAM_3E(INIT_RAM_3E),
    .INIT_RAM_3F(INIT_RAM_3F),
    .READ_MODE0(READ_MODE0),
    .READ_MODE1(READ_MODE1),
    .RESET_MODE(RESET_MODE),
    .WRITE_MODE0(WRITE_MODE0),
    .WRITE_MODE1(WRITE_MODE1)
) dp_inst (
    .ADA(ADA),
    .ADB(ADB),
    .BLKSEL(BLKSEL),
    .CEA(CEA),
    .CEB(CEB),
    .CLKA(CLKA),
    .CLKB(CLKB),
    .DIA(DIA),
    .DIB(DIB),
    .DOA(DOA),
    .DOB(DOB),
    .OCEA(OCEA),
    .OCEB(OCEB),
    .RESETA(RESETA),
    .RESETB(RESETB),
    .WREA(WREA),
    .WREB(WREB)
);
```
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