XicTools

https://github.com/wrcad/xictools
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XicTools is an open-source suite of electronic design automation (EDA) tools, featuring the Xic...
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### Run bash in a DOS box

Source: https://github.com/wrcad/xictools/blob/master/xt_base/packages/files/MSWINFO.TXT

Commands to start a Cygwin bash shell from a Windows DOS box. The first command changes to the Cygwin bin directory; adjust if Cygwin is installed elsewhere.

```bash
cd c:/cygwin/bin
bash --login -i
```

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### Run wr_install with 'all' argument

Source: https://github.com/wrcad/xictools/blob/master/xt_base/www/linux_install.html

Run the wr_install script with the argument 'all' to install all distribution files. The 'all' argument is equivalent to *.rpm or *.deb. Do not change the names of the files or the script will likely fail.

```bash
./wr_install all
```

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### Install required MacPorts packages

Source: https://github.com/wrcad/xictools/blob/master/xt_base/www/macos_install.html

Run these commands as root to install the graphical libraries and build tools required by the programs. This is needed for a first-time installation after setting up MacPorts and Xcode.

```bash
port -v selfupdate
port install gsl
port install python2_select
port install python27
port install autoconf
port install pkgconfig
port install gtk2
port install qt6
```

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### Make wr_install and wr_uninstall scripts executable

Source: https://github.com/wrcad/xictools/blob/master/xt_base/www/linux_install.html

Use this command after downloading to ensure the installation scripts are executable, as they might not be after download.

```bash
chmod 0755 wr_install wr_uninstall
```

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### Verilog while Loop Example

Source: https://github.com/wrcad/xictools/blob/master/vl/verilog-manual.html

Example of a while loop in Verilog that prints i from 0 to 9.

```verilog
    i = 0;
    while(i < 10)
       begin
         $display("i= %0d", i);
         i = i + 1;
       end  
```

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### $display Header Example

Source: https://github.com/wrcad/xictools/blob/master/vl/verilog-manual.html

Displays a header string using the $display system task.

```verilog
$display("Registers:   A   B   C");
```

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### Start VeriWell simulator with -s option

Source: https://github.com/wrcad/xictools/blob/master/vl/verilog-manual.html

Command to start the VeriWell simulator with multiple Verilog source files and the -s option to enter interactive mode before simulation begins. Files are processed in the order they appear after options are processed.

```shell
host-name% veriwell cpu.v bus.v top.v -s
```

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### Verilog parameter Statement Example

Source: https://github.com/wrcad/xictools/blob/master/vl/verilog-manual.html

Example of using parameter to define a constant for register width.

```verilog
		parameter byte_size = 8;

		reg [byte_size - 1:0] A, B;
```
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