TerosHDL

https://terostechnology.github.io/terosHDLdoc/
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An open-source HDL integrated development environment providing VHDL/Verilog/SystemVerilog support...
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### Install GHDL on Windows

Source: https://terostechnology.github.io/terosHDLdoc/docs/tutorials/tutorial_vhdl

Installs GHDL on Windows using MinGW and pacman. Ensure MinGW is installed first.

```bash
pacman -S mingw-w64-x86_64-ghdl
```

--------------------------------

### Install Make on macOS

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Installs Make on macOS by installing Xcode Command Line Tools. Run this command in the Terminal application.

```bash
xcode-select
```

```bash
make -v
```

--------------------------------

### Install Make using Chocolatey on Windows

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Installs the Make utility on Windows using the Chocolatey package manager. Ensure you have administrative privileges and Chocolatey installed.

```powershell
Set-ExecutionPolicy Bypass -Scope Process -Force; [System.Net.ServicePointManager]::SecurityProtocol = [System.Net.ServicePointManager]::SecurityProtocol -bor 3072; iex ((New-Object System.Net.WebClient).DownloadString('https://community.chocolatey.org/install.ps1'))
```

```powershell
choco install make
```

```bash
make --version
```

--------------------------------

### Install Make on Linux

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Installs the Make utility on Linux systems using the apt package manager. This command should be run in a terminal window.

```bash
sudo apt install make
```

--------------------------------

### Install Python 3 on Linux

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Update the package list and install Python 3 and its package installer, pip, on a Linux system using apt.

```bash
sudo apt update
```

```bash
sudo apt install python3
```

```bash
sudo apt install python3-pip
```

--------------------------------

### Install GHDL on macOS

Source: https://terostechnology.github.io/terosHDLdoc/docs/tutorials/tutorial_vhdl

Installs GHDL on macOS using Homebrew. Xcode and Make must be installed first, followed by Homebrew itself.

```bash
/bin/bash -c "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install.sh)"
```

```bash
brew install ghdl
```

--------------------------------

### Example CSV File Content (Simple)

Source: https://terostechnology.github.io/terosHDLdoc/docs/project_configuration/sources

An example demonstrating a simple CSV file content for loading files into a project, where files are implicitly assigned to the default library if not specified.

```text
file_0.sv
file_1.vhd
file_2.vhd

```

--------------------------------

### Verilog WaveDrom Example

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/wavedrom

Example of adding a WaveDrom signal definition in Verilog. Ensure the comment is at the head of the file.

```verilog
//! { signal: [  
//!  { name: "clk",  wave: "P......" },  
//!  { name: "bus",  wave: "x.==.=x", data: ["head", "body", "tail", "data"] },  
//!  { name: "wire", wave: "0.1..0." }  
//! ],  
//!  head:{  
//!     text:'WaveDrom example',
//!     tick:0,  
//!     every:2  
//!   }}

```

--------------------------------

### Install teroshdl Python Package

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

After activating a virtual environment, use pip to install the teroshdl Python package. This command installs the necessary libraries for TerosHDL.

```bash
pip install teroshdl
```

--------------------------------

### Example CSV File Content (With Libraries)

Source: https://terostechnology.github.io/terosHDLdoc/docs/project_configuration/sources

An example illustrating a CSV file content where specific libraries are assigned to different VHDL/SystemVerilog files.

```text
lib_0, file_1.vhd
file_2.vhd
lib_0, file_3.vhd

```

--------------------------------

### Install GHDL on Linux

Source: https://terostechnology.github.io/terosHDLdoc/docs/tutorials/tutorial_vhdl

Installs GHDL on Debian-based Linux distributions using apt. Open a terminal to run the command.

```bash
sudo apt install ghdl
```

--------------------------------

### Install yowasp-yosys for Verilog

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/installation

Install the yowasp-yosys package using pip. This is for Verilog designs when using the standalone backend.

```bash
pip install yowasp-yosys  

```

--------------------------------

### VHDL Bitfield Example

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/wavedrom

Example of using the Bitfield extension for WaveDrom in VHDL to define register breakdowns.

```vhdl
--! {reg: [  
--!    { "name": "IPO",   "bits": 8, "attr": "RO" },  
--!    {                  "bits": 7 },  
--!     { "name": "BRK",   "bits": 5, "attr": "RW", "type": 4 },  
--!     { "name": "CPK",   "bits": 1 },  
--!     { "name": "Clear", "bits": 3 },  
--!     { "bits": 8 }
--!]

```

--------------------------------

### Install Python Dependencies

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Installs essential Python packages for VHDL/SystemVerilog development and EDA tool interaction. Use this command in your system's terminal or command prompt.

```bash
pip install vunit-hdl edalize yowasp-yosys cocotb
```

```bash
sudo pip install vunit-hdl edalize yowasp-yosys cocotb
```

```bash
sudo pip install vunit-hdl edalize yowasp-yosys cocotb
```

--------------------------------

### Create and Activate Python Virtual Environment

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

Create a new Python virtual environment named 'venv' and activate it using a batch script. This ensures Python packages are installed in an isolated environment.

```bash
python -m venv venv
```

```bash
venv\Scripts\activate.bat
```

--------------------------------

### Verilog State Machine Example

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/state_machine_viewer/usage

This Verilog code defines a state machine with states IDLE, PUSH_A, PUSH_B, and CRC. It demonstrates how TerosHDL might detect and visualize state machines, including a potential issue with a 'PUSH_M' state not being defined.

```verilog
module verilog_sm (  
    input clk,  
    input rstn  
);
  
wire push_a_done;
wire push_b_done;
wire new_data;
wire crc_done;  
  
typedef enum logic[1:0] {IDLE,PUSH_A,PUSH_B,CRC} state_t;
state_t state;
state_t nextstate;  
  
always @(posedge clk or negedge rstn) begin  
    if (~rstn) begin  
        state <= IDLE;  
    end  
    else begin  
        state <= nextstate;  
    end  
end  
  
always_comb begin  
    case (state)  
        IDLE: if(new_data) nextstate = PUSH_A;  
        PUSH_A: begin  
            if(push_a_done) nextstate = PUSH_B;  
            else if (push_a_done&push_b_done) nextstate = CRC;  
        end  
        PUSH_B: if(push_b_done) nextstate = PUSH_M;  
        CRC: nextstate= IDLE;  
        default: nextstate = state;  
    endcase  
end  
endmodule  

```

--------------------------------

### Custom Yosys Command for Technology Mapping

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/usage

An example of a customized Yosys command that includes 'synth' to map the schematic to a technology map. This results in the design being implemented using logic primitives instead of RTL.

```bash
read_verilog -sv {CURRENTFILE}; synth; proc; opt; write_json teroshdl_yosys_output.json; stat  
```

--------------------------------

### Verilog State Machine Implementation

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/state_machine_viewer/examples

This Verilog code implements a state machine with equivalent functionality to the VHDL example. It uses an enumerated type for states and separate always blocks for state register and next-state logic.

```verilog
module verilog_sm (
    input clk,
    input rstn
);

wire push_a_done;
wire push_b_done;
wire new_data;
wire crc_done;

typedef enum logic[1:0] {IDLE,PUSH_A,PUSH_B,CRC} state_t;
state_t state;
state_t nextstate;

always @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        state <= IDLE;
    end
    else begin
        state <= nextstate;
    end
end

always_comb begin
    case (state)
        IDLE: if(new_data) nextstate = PUSH_A;
        PUSH_A: begin
            if(push_a_done) nextstate = PUSH_B;
            else if (push_a_done&push_b_done) nextstate = CRC;
        end
        PUSH_B: if(push_b_done) nextstate = PUSH_A;
        CRC: nextstate= IDLE;
        default: nextstate = state;
    endcase
end
endmodule

```

--------------------------------

### Add Python to System Path on macOS

Source: https://terostechnology.github.io/terosHDLdoc/docs/installation_checklist/installation

To use Python and pip commands without specifying 'python3' or 'pip3', add the Python installation's bin directory to your system's PATH environment variable by modifying your shell configuration file.

```bash
export PATH="/Library/Frameworks/Python.framework/Versions/3.X/bin:${PATH}"
```

--------------------------------

### VHDL Record Type Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares a record type in VHDL, which groups together different types of data under a single name. This example defines an AXI Stream interface.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

package mytypes is
    --! AXI Stream 32 bits
    type t_axis_32b is record
        tdata : std_logic_vector (31 downto 0); --! tdata description
        tvalid : std_logic; --! tvalid description
        tlast : std_logic; --! tlast description
        tready : std_logic; --! tready description
    end record t_axis_32b;
end package;
```

--------------------------------

### VHDL Enumerated Type Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares an enumerated type in VHDL, which defines a type with a list of named values. This example defines states for a state machine.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

package mytypes is
    --! main state machine description
    type main_sm_type is (IDLE, --! IDLE state description
                        PUSHA, --! PUSHA state description
                        PUSHB, --! PUSHB state description
                        FINISH --! FINISH state description
                        );
end package;
```

--------------------------------

### Module Declaration with Documentation

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Demonstrates how to document a Verilog module, its parameters, and ports using special comment directives.

```Verilog
//! @title mymodule design  
//! @author terosHDL  
module mymodule #(
    parameter PARAM1 = 1024 //! number of bytes in fifo  
)(
    output reg [PARAM1-1:0] data,   
    input clk, //! 300Mhz Clock  
    input rstn  
);
      
endmodule  

```

--------------------------------

### Module Instantiation in a Testbench

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Shows how to instantiate a module (DUT) within a testbench module, connecting its ports.

```Verilog
module tb_mytb(  
    input clk,  
    input rstn  
);
  
mymodule dut(
    .rstn (rstn),
    .clk (clk)
);
  
  
endmodule  

```

--------------------------------

### VHDL Port Declaration with Documentation

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares ports for a VHDL entity, including inline documentation for each port.

```vhdl
entity ports is
    port (
        clk   : in std_logic; --! my clock
        reset : in std_logic --! reset of everything
    );
end entity;
```

--------------------------------

### CSV Format for File Lists

Source: https://terostechnology.github.io/terosHDLdoc/docs/project_configuration/sources

Specifies the Comma Separated Values (CSV) format for listing files to be loaded into a TerosHDL project. Each line should contain the library name and the file path, relative to the CSV or absolute.

```text
library, file path relative to the CSV or absolute
library, file path relative to the CSV or absolute

```

--------------------------------

### Verilog Comment Extraction Configuration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/getting_started

Configure Verilog comments for documentation extraction. The '//!' symbol is used to denote documentation comments.

```verilog
// This is a
// license header
//! This is a description
//! of the module.
module flipflop (q,qbar,clk);
        output reg q; //! Port 0
        output qbar; //! Port 1
        input clk; //! Clock


```

--------------------------------

### CSV Source File Format

Source: https://terostechnology.github.io/terosHDLdoc/docs/external_tools

Specifies the accepted CSV format for adding source files. Files can be listed directly or with an associated library.

```text
file_0.sv
file_1.vhd
file_2.vhd

```

```text
file_1.vhd, lib_0
file_2.vhd
file_3.vhd, lib_0

```

--------------------------------

### Localparam Constant Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Defines a local parameter (constant) within a Verilog module and provides a comment for documentation.

```Verilog
module myconsts ();  
  
localparam SN=11223344; //! SN for this node  
      
endmodule  

```

--------------------------------

### VHDL State Machine Implementation

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/state_machine_viewer/examples

This VHDL code defines a simple state machine with states IDLE, PUSH_A, PUSH_B, and CRC. It uses a clocked process for state transitions and a combinational process to determine the next state based on current inputs and state.

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vhdl_sm is
    port (
        clk   : in std_logic;
        reset : in std_logic

    );
end entity vhdl_sm;

architecture rtl of vhdl_sm is
type sm_t is (IDLE,PUSH_A,PUSH_B,CRC); --! My State machine
signal state : sm_t;
signal next_state : sm_t;

signal push_a_done;
signal push_b_done;
signal new_data;
signal crc_done;

begin

incr_sm_proc: process (clk,rstn)
begin
    if (rstn = '0') then
        state <= IDLE;
    elsif rising_edge(clk) then
       state <= next_state;
    end if;
end process;


sm_proc: process(all)
begin
    case state is
        when IDLE =>
            if (new_data = '1') then
                next_state <= PUSH_A;
            end if;
        when PUSH_A =>
            if (push_a_done='1') then
                next_state <= PUSH_B;
            elsif (push_a_done='1' and push_b_done='1') then
                next_state <= CRC;
            end if;
        when PUSH_B =>
            if (push_b_done='1') then
                next_state <= PUSH_A;
            end if;
        when CRC =>
            next_state <= IDLE;
        when others =>
            next_state <= IDLE;
    end case;
end process;
end architecture;

```

--------------------------------

### Verilog Virtual Bus Definition

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/virtual_bus

Defines a Verilog module that utilizes virtual bus syntax for documentation. The virtual bus 'm00_axi4_stream' is defined with input signals for data, valid, ID, and destination, and an output for ready.

```verilog
module virtualbus (
    //! @virtualbus m00_axi4_stream @dir in  
    //! tdata of stream  
    input [7:0] m00_tdata,  
    //! valid of stream  
    input   m00_tvalid,  
    //! id of current message  
    input [3:0] m00_tid,  
    //! destination of packet  
    input [3:0] m00_tdest,  
    //! this device is ready to receive  
    output reg m00_tready,  
    //! @end  
  
    input clk,  
    input rstn  
);
  
endmodule  

```

--------------------------------

### VHDL Comment Extraction Configuration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/getting_started

Configure VHDL comments for documentation extraction. The '!' symbol is used by default, but can be changed in the TerosHDL configuration.

```vhdl
-- Other comment not included
--! This is a description
--! of the entity.
entity counter is
port (
    clk: in std_logic; --! Clock comment
    out_data: out std_logic --! Description **port comment**
);
end counter;

```

--------------------------------

### Function Definition

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Defines a Verilog function that takes inputs and returns a value based on operations within the function.

```Verilog
module funcs ;  
  
function reg[1:0] myfunc(input a,b);  
  
    myfunc = {a,b};
endfunction  
  
  
endmodule  
  

```

--------------------------------

### Default Verilog Yosys Command

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/usage

The default Yosys command used for Verilog synthesis. This command reads the current Verilog file, performs processing and optimization, writes the output to a JSON file, and displays statistics.

```bash
read_verilog -sv {CURRENTFILE}; proc; opt; write_json teroshdl_yosys_output.json; stat  
```

--------------------------------

### VHDL Process Statement

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Defines a VHDL process, which is a sequential block of code that executes concurrently with other processes and concurrent statements.

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity my_process is
    port (
        clk   : in std_logic;
        reset : in std_logic
    );
end entity my_process;

architecture rtl of my_process is

begin
    myproc: process (clk)
    begin
          
    end process;
      
  
end architecture;
```

--------------------------------

### Default VHDL Yosys Command

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/usage

The default Yosys command used for VHDL synthesis. This command uses ghdl to read the VHDL file, performs synthesis, optimization, and outputs statistics.

```bash
ghdl --std=08 -fsynopsys {CURRENTFILE} -e; proc; opt; write_json teroshdl_yosys_output.json; stat  
```

--------------------------------

### VHDL Function Declaration and Body

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares and defines a VHDL function. Functions are used to perform computations and return a value.

```vhdl
library ieee;
use ieee.std_logic_1164.all;
package mypackage is
    function func1 (x:integer) return std_logic;
      
end package;
package body mypackage is
    function func1 (x:integer) return std_logic is
    begin
          
    end function;
end package body;
```

--------------------------------

### Struct Typedef for AXI-4 Stream

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Defines a packed structure using `typedef` in SystemVerilog to represent data for an AXI-4 Stream interface.

```SystemVerilog
//! AXI-4 Stream  
typedef struct packed {
    logic [7:0] data;
    logic [0:0] valid;
    logic [0:0] clk;
} mystruct;  
      

```

--------------------------------

### Always Block Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/verilog_elements

Declares an always block in Verilog, which is a procedural block that executes based on sensitivity list events.

```Verilog
module alwaysmod (  
    input clk,  
    input rstn  
);
      
always @(posedge clk or negedge rstn) begin: myproc  
      
end  
endmodule  

```

--------------------------------

### VHDL Package Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares a VHDL package. Packages are used to group related declarations such as types, constants, functions, and components.

```vhdl
package mynewpackage is
      
end package;
```

--------------------------------

### VHDL Entity Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Defines a VHDL entity with generics and ports. This is a fundamental building block for VHDL designs.

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity myentity is
    generic (
        gen1 : integer := 0
    );
    port (
        clk   : in std_logic;
        reset : in std_logic

    );
end entity;
architecture rtl of myentity is

begin

      

end architecture;
```

--------------------------------

### VHDL Constant Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares constants within a VHDL package. Constants are used for defining fixed values used throughout the design.

```vhdl
package mypackage is
    constant DATA_WIDTH : integer := 35; --! number of bits
    constant ADDR_WIDTH : integer := 21; --! number of bits
      
end package;
```

--------------------------------

### VHDL Custom Integer Type Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares a custom integer type with a specified range in VHDL. This is useful for defining specific numerical constraints.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

package mytypes is
    type t_my_custom_type is range 0 to 1000; --! my custom type description
end package;
```

--------------------------------

### VHDL Signal Declaration

Source: https://terostechnology.github.io/terosHDLdoc/docs/guides/documenter/vhdl_elements

Declares signals within a VHDL architecture. Signals are used for internal connections and data transfer within an entity.

```vhdl
library ieee;
use ieee.std_logic_1164.all;


entity mysignal is
    port (
        clk   : in std_logic;
        reset : in std_logic

    );
end entity mysignal;

architecture rtl of mysignal is
signal sig_a : std_logic_vector(31 downto 0);
signal sig_b : std_logic_vector(31 downto 0);

signal sig_c : std_logic; --! example documentation

data_a: integer range 0 to 1023;
begin

      

end architecture;
```
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