### Check NEORV32 Toolchain Setup Source: https://stnolting.github.io/neorv32/ug Navigate to a NEORV32 software example directory and run 'make check' to verify that all necessary tools are correctly installed and accessible. ```bash neorv32/sw/example/demo_blink_led$ make check ``` -------------------------------- ### Build and Simulate Hello World Example Source: https://stnolting.github.io/neorv32/ug Navigate to the example's directory and run the make command to clean, install, and simulate the 'Hello World!' application. This command also enables UART0 simulation mode. ```bash neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE clean install sim ``` -------------------------------- ### Example: Install Custom Trap Handlers Source: https://stnolting.github.io/neorv32 This example demonstrates installing custom handlers for various exemplary traps, including the machine timer interrupt, environment call exception, and a specific SLINK receive interrupt. ```c neorv32_rte_handler_install(RTE_TRAP_MTI, machine_timer_irq_handler); // handler for machine timer interrupt neorv32_rte_handler_install(RTE_TRAP_MENV_CALL, environment_call_handler); // handler for machine environment call exception neorv32_rte_handler_install(SLINK_RX_RTE_ID, slink_rx_handler); // handler for SLINK receive interrupt ``` -------------------------------- ### Generate and Install IMEM Application Image Source: https://stnolting.github.io/neorv32/ug This command cleans the build, generates the VHDL initialization file for IMEM with the application firmware, and installs it to the processor's core directory. ```bash neorv32/sw/example/demo_blink_led$ make clean_all image install Memory utilization: text data bss dec hex filename 22192 1352 4216 27760 6c70 main.elf Compiling image generator... Generating neorv32_imem_image.vhd Installing application image to ../../../rtl/core/neorv32_imem_image.vhd ``` -------------------------------- ### Core 1 Main Function Example Source: https://stnolting.github.io/neorv32 Example of a main function for core 1. It should return an integer and can optionally take arguments. Returning 0 typically leads to sleep mode. ```c int core1_main(void) { return 0; // return to crt0 and go to sleep mode } ``` -------------------------------- ### Setup NEORV32 Runtime Environment Source: https://stnolting.github.io/neorv32 Call `neorv32_rte_setup()` at the beginning of your main function to initialize the NEORV32 runtime environment. For SMP configurations, this must be called on each core. ```c int main() { neorv32_rte_setup(); // setup NEORV32 runtime environment ... } ``` -------------------------------- ### NEORV32 System Configuration Information Source: https://stnolting.github.io/neorv32 This example shows the output when the 'i' command is used to display system configuration information, including hardware version, clock speed, and CPU extensions. ```text CMD:> i HWV: 0x01120101 __**(1)** CLK: 0x05f5e100 __**(2)** MISA: 0x40901107 __**(3)** XISA: 0x00000000:0x0fc06fd3 __**(4)** SOC: 0x38efc87b __**(5)** MISC: 0x0a010d00 __**(6)** CMD:> ``` -------------------------------- ### Compile NEORV32 Test Application Source: https://stnolting.github.io/neorv32/ug Compile the 'blink led' example application using make. This generates an ELF file required for debugging. ```bash neorv32/sw/example/demo_blink_led$ make clean_all all ``` -------------------------------- ### Generate documentation using Docker Source: https://stnolting.github.io/neorv32/ug If asciidoctor or asciidoctor-pdf are not installed, use the 'container' target with make to build all documentation via a Docker container. ```bash neorv32/docs$ make container ``` -------------------------------- ### CFU Instruction Software Examples Source: https://stnolting.github.io/neorv32 Demonstrates how to call custom I-Type and R-Type instructions using the NEORV32 intrinsics in C-code. The results can be stored or discarded. ```c uint32_t foo = 12345; uint32_t res = RISCV_INSTR_I_TYPE(RISCV_OPCODE_CUSTOM1, 0b001, foo, 0xABC); res = RISCV_INSTR_R_TYPE(RISCV_OPCODE_CUSTOM0, 0b101, 0b1100110, res, foo); ``` -------------------------------- ### Start Debug Session with GDB Makefile Target Source: https://stnolting.github.io/neorv32/ug Use the 'make gdb' target to quickly start a pre-configured debug session. This assumes 'main.elf' is the executable and 'target extended-remote localhost:3333' is the GDB connection configuration. ```makefile make gdb ``` -------------------------------- ### Start GDB for NEORV32 Debugging Source: https://stnolting.github.io/neorv32/ug Launch the GDB debugger for the RISC-V target. This is the initial step before connecting to the hardware. ```bash .../neorv32/sw/example/demo_blink_led$ riscv32-unknown-elf-gdb GNU gdb (GDB) 10.1 Copyright (C) 2020 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf". Type "show configuration" for configuration details. For bug reporting instructions, please see: . Find the GDB manual and other documentation resources online at: . For help, type "help". Type "apropos word" to search for commands related to "word". (gdb) ``` -------------------------------- ### Start LiteX Simulation with NEORV32 CPU Source: https://stnolting.github.io/neorv32/ug Initiates a LiteX simulation with the NEORV32 processor as the target CPU. This command is run directly from the console. ```bash $ litex_sim --cpu-type=neorv32 ``` -------------------------------- ### Exemplary Bootloader Executable Header Output Source: https://stnolting.github.io/neorv32 An example of the bootloader executable header as displayed by the 'xxd' utility, showing the hexadecimal representation of the signature, base address, size, and checksum. ```text neorv32/sw/example/processor_check$ xxd -e -l 32 neorv32_exe.bin 00000000: 214f454e 00000000 00007078 2af7f9c6 NEO!....xp.....* ``` -------------------------------- ### GDB Example Workflow with Tracer Source: https://stnolting.github.io/neorv32 A typical workflow for using the NEORV32 tracer from GDB. This includes compiling, loading, running the program, importing the tracer script, and retrieving trace data. ```gdb (gdb) make clean elf __**(1)** ... (gdb) load __**(2)** ... (gdb) c __**(3)** ... (gdb) source neorv32_tracer.gdb __**(4)** (gdb) tracer_get __**(5)** ``` -------------------------------- ### Show make build options Source: https://stnolting.github.io/neorv32/ug Use the 'help' target with make to display all available build options and their outputs for documentation generation. ```bash neorv32/docs$ make help ``` -------------------------------- ### NEORV32 openOCD Single-Core Configuration Source: https://stnolting.github.io/neorv32 This Tcl script configures openOCD for a single-core NEORV32 setup. It sources interface, target, authentication, and start scripts. Customize the interface script for different JTAG adapters. ```tcl # configuration set PATH [file dirname [file normalize [info script]]] __**(1)** set CORENAME neorv32 __**(2)** set NUMCORES 1 __**(3)** # configure JTAG interface, setup target, authenticate and start source [file join $PATH lib/interface.cfg] __**(4)** source [file join $PATH lib/target.cfg] __**(5)** source [file join $PATH lib/authenticate.cfg] __**(6)** source [file join $PATH lib/start.cfg] __**(7)** ``` -------------------------------- ### Machine Trap Setup CSRs Source: https://stnolting.github.io/neorv32 Documentation for the machine trap setup related Control and Status Registers (CSRs). ```APIDOC ## mstatus ### Description Machine status register - low word. Used to configure general machine environment parameters. ### Address `0x300` ### Reset Value `0x00000000` ### ISA Support `Zicsr` ### Bit Fields - **MIE** (r/w): Machine-mode interrupt enable flag. - **MPIE** (r/w): Previous machine-mode interrupt enable flag state. - **MPP** (r/w): Previous machine privilege mode (11=M, 00=U). - **MPRV** (r/w): Effective privilege mode for load/stores when set. - **TW** (r/w): Trap on execution of `wfi` instruction in user mode when set. ## misa ### Description ISA and extensions register. Provides information regarding the availability of basic RISC-V ISA extensions. ### Address `0x301` ### Reset Value Defined by enabled ISA extensions. ### ISA Support `Zicsr` ### Read/Write Read-only. Write accesses are ignored. ### Bit Fields - **A_EXT** (r/-): Atomic memory access extension available. - **B_EXT** (r/-): Bit-manipulation extension available. - **C_EXT** (r/-): Compressed instruction extension available. - **E_EXT** (r/-): Embedded extension available. - **I_EXT** (r/-): Base ISA indicator (cleared if E extension enabled). - **M_EXT** (r/-): Multiply/divide extension available. - **U_EXT** (r/-): User mode extension available. - **X_EXT** (r/-): Indicates non-standard / NEORV32-specific extensions. - **MXL** (r/-): 32-bit architecture indicator (always `01`). ## mie ### Description Machine interrupt-enable register. Used to enable/disable individual interrupt sources. ### Address `0x304` ### Reset Value `0x00000000` ### ISA Support `Zicsr` ### Bit Fields - **MSIE** (r/w): Machine software interrupt enable. - **MTIE** (r/w): Machine timer interrupt enable. - **MEIE** (r/w): Machine external interrupt enable. - **FIRQ15E** to **FIRQ0E** (r/w): Fast interrupt channel 15..0 enable. ``` -------------------------------- ### Test Setup Entity Ports Source: https://stnolting.github.io/neorv32/ug Defines the essential ports for the NEORV32 test setup bootloader entity. Includes global control signals, GPIO, and UART communication interfaces. ```vhdl port ( -- Global control -- clk_i : in std_ulogic; -- global clock, rising edge rstn_i : in std_ulogic; -- global reset, low-active, async -- GPIO -- gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output -- UART0 -- uart0_txd_o : out std_ulogic; -- UART0 send data uart0_rxd_i : in std_ulogic -- UART0 receive data ); ``` -------------------------------- ### NEORV32 Bootloader Help Menu Source: https://stnolting.github.io/neorv32 This displays the help menu for the NEORV32 bootloader, listing available commands and their functions. ```text CMD:> h Available CMDs: h: Help __**(1)** i: System info __**(2)** r: Restart __**(3)** u: Upload via UART __**(4)** t: TWI flash - load __**(5)** w: TWI flash - program __**(6)** l: SPI flash - load __**(7)** s: SPI flash - program __**(8)** c: SD card - load __**(9)** e: Start executable __**(10)** x: Exit __**(11)** CMD:> ``` -------------------------------- ### Makefile Upload Target Example Source: https://stnolting.github.io/neorv32 Example of using the `make upload` target from the application Makefile to transfer a compiled executable directly to the bootloader via UART. The `UART_TTY` variable specifies the serial interface device. ```bash neorv32/sw/example/demo_blink_led$ make UART_TTY=/dev/ttyUSB1 upload ``` -------------------------------- ### NEORV32 Makefile Help Menu Source: https://stnolting.github.io/neorv32 Invoking 'make' or 'make help' displays the help menu, listing all available targets and variables with their current settings. This is useful for understanding project configuration and build options. ```makefile neorv32/sw/example/hello_world$ make NEORV32 Software Makefile Find more information at https://github.com/stnolting/neorv32 Use 'make V=1' or set BUILD_VERBOSE to increase build verbosity Targets: help show this text check check toolchain and list supported ISA extensions info show project/makefile configuration gdb start GNU debugging session asm build and generate assembly listing file elf build and generate ELF file exe build and generate executable file for bootloader upload bin build and generate executable memory image coe build and generate executable memory image mem build and generate executable memory image mif build and generate executable memory image image build and generate VHDL IMEM application memory image in local folder install build, generate and install VHDL IMEM application memory image clean clean up project home folder clean_all clean up project home folder and image generator all elf + asm + exe + bin + coe + mem + mif + image + install Additional targets: sim in-console simulation using default testbench (sim folder) and GHDL hdl_lists regenerate HDL file-lists (*.f) in NEORV32_HOME/rtl upload upload executable to bootloader via UART (/dev/ttyUSB1) elf_info show ELF information elf_sections show ELF sections bl_image build and generate VHDL BOOTROM bootloader memory image in local folder bootloader build, generate and install VHDL BOOTROM bootloader memory image Variables: BUILD_VERBOSE Set to increase build verbosity: "0" USER_FLAGS Custom toolchain flags [append only]: "-ggdb -gdwarf-3 -Wl,--defsym,__neorv32_rom_size=16k -Wl,--defsym,__neorv32_rom_base=0x00002000 -Wl,--defsym,__neorv32_ram_size=8k" USER_LIBS Custom libraries [append only]: "" EFFORT Optimization level: "-Os" MARCH Machine architecture: "rv32i_zicsr_zifencei" MABI Machine binary interface: "ilp32" APP_INC C include folder(s) [append only]: "-I ." APP_SRC C source folder(s) [append only]: "./main.c " APP_OBJ Object file(s) [append only]: "" ASM_INC ASM include folder(s) [append only]: "-I ." RISCV_PREFIX Toolchain prefix: "riscv-none-elf-" NEORV32_HOME NEORV32 home folder: "../../.." GDB_ARGS GDB arguments: "-ex target extended-remote localhost:3333" UART_TTY Serial port for upload to bootloader: "/dev/ttyUSB1" GHDL_RUN_FLAGS GHDL simulation run arguments: "" ``` -------------------------------- ### GPIO VHDL Tristate Driver Example Source: https://stnolting.github.io/neorv32 A VHDL example demonstrating the implementation of a tristate driver for GPIO pins. It uses a generate loop to configure each pin based on the `gpio_dir_o` signal and assigns the input data from the `gpio_io` port. ```vhdl gpio_tristate_gen: for i in 0 to IO_GPIO_NUM-1 generate gpio_io(i) <= std_logic(gpio_o(i)) when (gpio_dir_o(i) = '1') else 'Z'; -- drive end generate; gpio_i(IO_GPIO_NUM-1 downto 0) <= std_ulogic_vector(gpio_io(IO_GPIO_NUM-1 downto 0)); -- sense ``` -------------------------------- ### Start GHDL Simulation from Application Makefile Source: https://stnolting.github.io/neorv32/ug Initiate the GHDL simulation directly from the main application makefile. This command also allows for passing user flags, such as enabling UART0 simulation mode. ```bash sw/example/demo_blink_led$ make USER_FLAGS+=-DUART0_SIM_MODE clean_all install sim ``` -------------------------------- ### Check Yosys Installation and GHDL Plugin Source: https://stnolting.github.io/neorv32/ug Verify your yosys installation and confirm the GHDL plugin is available by running the yosys -H command. This output shows the yosys version and lists available plugins, including 'ghdl' for VHDL design loading. ```bash $ yosys -H /----------------------------------------------------------------------------\ | | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | Permission to use, copy, modify, and/or distribute this software for any | purpose with or without fee is hereby granted, provided that the above | copyright notice and this permission notice appear in all copies. | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | \----------------------------------------------------------------------------/ Yosys 0.10+12 (open-tool-forge build) (git sha1 356ec7bb, gcc 9.3.0-17ubuntu1~20.04 -Os) -- Running command `help' -- ... __**(1)** ghdl load VHDL designs using GHDL __**(2)** ... ``` -------------------------------- ### Hello World Program Output Source: https://stnolting.github.io/neorv32/ug The 'Hello World!' application's output, including a decorative ASCII art banner and the 'Hello world! :)' message, is printed to the console when the simulation runs. ```text ## ## ## ## ## ## ######### ######## ######## ## ## ######## ######## ## ################ #### ## ## ## ## ## ## ## ## ## ## ## ## ## #### #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ## ## ## ## ######### ## ## ######### ## ## ##### ## ## #### ###### #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ## ## #### ## ## ## ## ## ## ## ## ## ## ## #### #### ## ## ######### ######## ## ## ## ######## ########## ## ################ ## ## ## ## Hello world! :) ``` -------------------------------- ### NEORV32 RTE Default Trap Handler UART0 Output Examples Source: https://stnolting.github.io/neorv32 These examples show the debug messages generated by the NEORV32 RTE for various trap types. The messages include the trap code, program counter (MEPC), instruction details (MTINST), and faulting value (MTVAL). They indicate whether the trap is fatal and halts the CPU. ```text [cpu0|M] Illegal instruction MEPC=0x000002d6 MTINST=0x000000FF MTVAL=0x00000000 __**(1)** ``` ```text [cpu0|U] Illegal instruction MEPC=0x00000302 MTINST=0x00000000 MTVAL=0x00000000 __**(2)** ``` ```text [cpu0|U] Load address misaligned MEPC=0x00000440 MTINST=0x01052603 MTVAL=0x80000101 __**(3)** ``` ```text [cpu1|M] FIRQ channel 0x00000003 MEPC=0x00000820 MTINST=0x00000000 MTVAL=0x00000000 __**(4)** ``` ```text [cpu1|M] Instruction access fault MEPC=0x90000000 MTINST=0x42078b63 MTVAL=0x00000000 FATAL! HALTING CPU __**(5)** ```