### Create sram22.toml configuration

Source: https://sram22.com/docs/quickstart

Create a sram22.toml configuration file in the working directory. This example defines a single SRAM macro with 64 words, 32-bit data width, mux ratio 4, and write size 8.

```toml
[[sram]]  

num_words = 64  

data_width = 32  

mux_ratio = 4  

write_size = 8  
```

--------------------------------

### Install sram22 with Cargo

Source: https://sram22.com/docs/quickstart

Install the sram22 generator from its Git repository using Cargo. Requires a current stable Rust toolchain and Cargo.

```bash
cargo install --git https://github.com/ucb-substrate/sram22 --locked sram22  
```

--------------------------------

### Run sram22 with explicit paths

Source: https://sram22.com/docs/quickstart

Run sram22 with explicit configuration and output directory paths. The --config option specifies the TOML path and --output-dir specifies the parent output directory.

```bash
sram22 --config sram22.toml --output-dir output  
```

--------------------------------

### OpenROAD place_inst with R90 orientation

Source: https://sram22.com/docs/orientations

Place an instance with a quarter-turn orientation in OpenROAD. Coordinates are in microns; -origin positions the transformed cell origin, while -location positions its bounding box. Check the API for your OpenROAD version.

```tcl
place_inst -name u_mem -origin {120.0 80.0} -orientation R90 -status FIRM
```

--------------------------------

### Run sram22 generator

Source: https://sram22.com/docs/quickstart

Run the generator. SRAM22 reads sram22.toml and writes GDS, LEF, SPICE, Verilog, and Liberty to build/sram22_64x32m4w8/ beside the configuration file.

```bash
sram22  
```

--------------------------------

### Instantiate sram22_64x32m4w8 macro in RTL

Source: https://sram22.com/docs/tutorial/openroad

Instantiate the SRAM22 macro in top-level RTL. Use the behavioral .v in simulation; in synthesis, bind to a Liberty library cell or black box so the SRAM remains a hard macro.

```verilog
sram22_64x32m4w8 u_mem (
  .clk(clk), .rstb(rstb), .ce(ce), .we(we),
  .wmask(wmask), // [3:0]
  .addr(addr),   // [5:0]
  .din(din),    // [31:0]
  .dout(dout)   // [31:0]
);
```

--------------------------------

### Load SRAM22 views in custom OpenROAD Tcl flow

Source: https://sram22.com/docs/tutorial/openroad

Load technology LEF, standard-cell LEF and Liberty, SRAM LEF and Liberty, and the synthesized netlist before linking the design in a custom OpenROAD Tcl flow. Assumes TECH_LEF, SC_LEF, and SC_LIB are set by the flow.

```tcl
read_lef $::env(TECH_LEF)
read_lef $::env(SC_LEF)
read_lef ./macros/sram22_64x32m4w8.lef
read_liberty $::env(SC_LIB)
read_liberty ./macros/sram22_64x32m4w8_tt_025C_1v80.lib
read_verilog ./results/synth.v
link_design top
```

--------------------------------

### Genus synthesis command sequence

Source: https://sram22.com/docs/tutorial/cadence

Synthesis command sequence for Genus after libraries are configured. The sequence reads the top-level HDL, elaborates the design, reads SDC constraints, and runs generic synthesis, mapping, and optimization. The mapped netlist must keep u_mem as an instance of the intended SRAM library cell.

```tcl
read_hdl top.v  

elaborate top  

read_sdc constraints.sdc  

syn_generic  

syn_map  

syn_opt  
```

--------------------------------

### Register SRAM22 views in ORFS configuration

Source: https://sram22.com/docs/tutorial/openroad

Register the SRAM22 LEF, Liberty, and GDS files in an ORFS design configuration, assuming the files are under the macro directory.

```makefile
export ADDITIONAL_LEFS += $(DESIGN_HOME)/macros/sram22_64x32m4w8.lef
export ADDITIONAL_LIBS += $(DESIGN_HOME)/macros/sram22_64x32m4w8_tt_025C_1v80.lib
export ADDITIONAL_GDS  += $(DESIGN_HOME)/macros/sram22_64x32m4w8.gds
```

--------------------------------

### Verilog declaration for sram22_64x32m4w8

Source: https://sram22.com/docs/interface/pin-list

Verilog module declaration for the sram22_64x32m4w8 macro (64 words × 32 bits, byte write mask). The power pins vdd and vss are conditionally declared only when USE_POWER_PINS is defined. Signal pins are on met1; power pins are on met2.

```verilog
module sram22_64x32m4w8 (  

`ifdef USE_POWER_PINS  

  inout  vdd,  

  inout  vss,  

`endif  

  input  clk,  

  input  rstb,            // active-low reset  

  input  ce,              // chip enable  

  input  we,              // write enable  

  input  [3:0]  wmask,    // data_width / write_size  

  input  [5:0]  addr,     // log2(num_words)  

  input  [31:0] din,  

  output [31:0] dout  

);  


```

--------------------------------

### Decompress SRAM22 GDS

Source: https://sram22.com/docs/tutorial/openroad

Decompress the GDS file from the published catalog before using it in the flow.

```bash
gzip -d sram22_64x32m4w8.gds.gz
```

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