loongArch64

https://docs.rs/loongArch64/0.2.6
Admin
loongArch64 is a Rust crate providing low-level abstractions and interfaces for the LoongArch 64-bit...
Tokens:144,923
Snippets:1,551
Trust Score:9.1
Update:5 months ago
Show doc for...
Tokens:
Raw
### Set the starting address of the level 4 directory

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/fn.set_dir4_base.html

Use this function to set the starting address of the level 4 directory. It takes a `usize` value representing the address.

```rust
pub fn set_dir4_base(val: usize)
```

--------------------------------

### loongArch64 Library Setup

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/lib.rs.html

Sets up the library for no_std environments and defines core constants for the architecture.

```rust
#![no_std]
#![allow(unused)]
#![allow(non_snake_case)]
pub mod asm;
pub mod consts;
pub mod cpu;
pub mod iocsr;
pub mod ipi;
pub mod register;
pub mod time;
const VALEN: usize = 48;
const PALEN: usize = 48;

```

--------------------------------

### Get STLB Page Size Exponent

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/stlbps/struct.StlbPs.html

Calculates and returns the `log(RealPageSize)/log(2)` for the STLB page size. For example, a page size of 16KB results in `PS` = 0xE.

```rust
pub fn ps(&self) -> usize
```

--------------------------------

### set_ptwidth

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_ptwidth.html

Sets the starting address of the lowest level directory.

```APIDOC
## Function set_ptwidth

### Description
Set the starting address of the lowest level directory.

### Signature
```rust
pub fn set_ptwidth(ptwidth: usize)
```

### Parameters
* `ptwidth` (usize) - The starting address of the lowest level directory.
```

--------------------------------

### Get Directory 2 Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/struct.Pwcl.html

Retrieves the starting address of the next level directory. This is used in multi-level page table structures.

```rust
pub fn dir2_base(&self) -> usize
```

--------------------------------

### Get Directory 1 Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/struct.Pwcl.html

Retrieves the starting address of the lowest level directory. This is part of the hierarchical page table structure.

```rust
pub fn dir1_base(&self) -> usize
```

--------------------------------

### Set Page Size (PS)

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/stlbps/fn.set_ps.html

Sets the `log(RealPageSize)/log(2)` value. For example, a 16KB page size corresponds to `PS` = `0xE`.

```rust
pub fn set_ps(page_size: usize)
```

--------------------------------

### Set Page Table Width

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_ptwidth.html

Use this function to set the starting address of the lowest level directory. It takes a usize argument representing the page table width.

```rust
pub fn set_ptwidth(ptwidth: usize)
```

--------------------------------

### set_dir2_base

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_dir2_base.html

Sets the starting address of the next level directory.

```APIDOC
## Function set_dir2_base

### Description
Set the starting address of the next level directory.

### Signature
```rust
pub fn set_dir2_base(dir2_base: usize)
```

### Parameters
* `dir2_base` (usize) - The starting address of the next level directory.
```

--------------------------------

### Set Directory Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_dir2_base.html

Use this function to set the starting address for the next level directory. It takes a `usize` value representing the base address.

```rust
pub fn set_dir2_base(dir2_base: usize)
```

--------------------------------

### Get Architecture Information

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/cpu.rs.html

Retrieves the architecture information by reading CPU configuration register 1 and extracting bits 0 through 1.

```rust
pub fn get_arch() -> usize {
    let cfg = CPUCFG::read(1);
    cfg.get_bits(0, 1)
}
```

--------------------------------

### Get STLB Page Size

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/stlbps.rs.html

Retrieves the `log(RealPageSize)/log(2)` from the STLBPS register. For example, a page size of 16KB corresponds to a `PS` value of 0xE.

```rust
impl StlbPs {
    /// Get the `log(RealPageSize)/log(2)`
    /// For example, if the page size is 16KB, then `PS`=`0xE`.
    pub fn ps(&self) -> usize {
        self.bits.get_bits(0..=5)
    }
}
```

--------------------------------

### set_dir1_base

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_dir1_base.html

Sets the starting address of the lowest level directory.

```APIDOC
## Function set_dir1_base

### Description
Set the starting address of the lowest level directory.

### Signature
```rust
pub fn set_dir1_base(dir1_base: usize)
```

### Parameters
* **dir1_base** (usize) - The starting address of the lowest level directory.
```

--------------------------------

### set_dir3_base

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/fn.set_dir3_base.html

Sets the starting address of the level 3 directory.

```APIDOC
## Function set_dir3_base

### Description
Set the starting address of the level 3 directory.

### Signature
```rust
pub fn set_dir3_base(val: usize)
```

### Parameters
* `val` (usize) - The starting address for the level 3 directory.
```

--------------------------------

### Get Supported Page Sizes

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/prcfg2/struct.Prcfg2.html

Returns a bit vector indicating supported TLB page sizes. A '1' at bit `i` means 2^i page size is supported.

```rust
pub fn psval(&self) -> usize
```

--------------------------------

### Get Support for Huge Pages

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/fn.get_support_huge_page.html

This function checks and returns whether the system supports huge pages on the loongArch64 architecture. It is a public function with no arguments.

```rust
pub fn get_support_huge_page() -> bool
```

--------------------------------

### Set Directory 1 Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_dir1_base.html

Use this function to set the starting address of the lowest level directory. It takes the base address as a usize argument.

```rust
pub fn set_dir1_base(dir1_base: usize)
```

--------------------------------

### set_ps Function

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/stlbps/fn.set_ps.html

Sets the page size configuration. The `page_size` parameter represents log(RealPageSize)/log(2). For example, a page size of 16KB would be represented as `0xE`.

```APIDOC
## Function set_ps

### Signature
```rust
pub fn set_ps(page_size: usize)
```

### Description
Sets the `log(RealPageSize)/log(2)` value. For instance, if the page size is 16KB, then `PS` would be `0xE`.
```

--------------------------------

### Get MMU Support Page

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/fn.get_mmu_support_page.html

Returns a boolean indicating whether MMU support is available for the page.

```rust
pub fn get_mmu_support_page() -> bool
```

--------------------------------

### Get Bit Range from CPUCFG

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/struct.CPUCFG.html

Extracts a range of bits from the CPUCFG. The start and end indices define the range (inclusive of start, exclusive of end).

```rust
pub fn get_bits(&self, start: usize, end: usize) -> usize
```

--------------------------------

### TlbRSave Conversions

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbrsave/struct.TlbRSave.html

Demonstrates how to create a TlbRSave instance from a `usize` value and vice versa.

```APIDOC
## TlbRSave Conversions

### `impl From<usize> for TlbRSave`

#### `fn from(bits: usize) -> Self`

Converts a `usize` value into a `TlbRSave` instance.

### `impl Clone for TlbRSave`

#### `fn clone(&self) -> TlbRSave`

Returns a duplicate of the `TlbRSave` value.

#### `fn clone_from(&mut self, source: &Self)`

Performs copy-assignment from a source `TlbRSave` instance.
```

--------------------------------

### Read Era Register Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/era/fn.read.html

Call this function to get the current value of the Era register. No specific setup is required.

```rust
pub fn read() -> Era
```

--------------------------------

### Dmw0 Conversions and Traits

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw0/struct.Dmw0.html

Information on how to convert to and from Dmw0, as well as its implemented traits.

```APIDOC
## Dmw0 Conversions and Traits

### `From<usize>`

- **Description**: Allows creating a `Dmw0` instance from a `usize` value.
- **Signature**: `fn from(bits: usize) -> Self`

### `Clone` Trait

- **Description**: Implements cloning for `Dmw0` instances.
- **Methods**: `clone(&self) -> Dmw0`, `clone_from(&mut self, source: &Self)`

### `Debug` Trait

- **Description**: Implements the `Debug` trait for formatting `Dmw0` instances.
- **Method**: `fmt(&self, f: &mut Formatter<'_>) -> Result`

### `Copy` Trait

- **Description**: Indicates that `Dmw0` is a `Copy` type.
```

--------------------------------

### Read DMW2 Register

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw2/fn.read.html

Call the read function to get the current value of the DMW2 register. No setup or imports are required.

```rust
pub fn read() -> Dmw2
```

--------------------------------

### Get Pwch Dir4 Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/struct.Pwch.html

Retrieves the starting memory address for the level 4 directory in the page table structure.

```rust
pub fn dir4_base(&self) -> usize
```

--------------------------------

### Dmw0 Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw0/struct.Dmw0.html

This section details the methods available for the Dmw0 struct, allowing users to interact with direct mapping configurations.

```APIDOC
## Dmw0 Struct Methods

### `raw()`

- **Description**: Returns the raw `usize` representation of the Dmw0 configuration.
- **Signature**: `pub fn raw(&self) -> usize`

### `plv0()`

- **Description**: Checks if privilege level 0 is enabled.
- **Signature**: `pub fn plv0(&self) -> bool`

### `plv1()`

- **Description**: Checks if privilege level 1 is enabled.
- **Signature**: `pub fn plv1(&self) -> bool`

### `plv2()`

- **Description**: Checks if privilege level 2 is enabled.
- **Signature**: `pub fn plv2(&self) -> bool`

### `plv3()`

- **Description**: Checks if privilege level 3 is enabled.
- **Signature**: `pub fn plv3(&self) -> bool`

### `mat()`

- **Description**: Returns the Memory Access Type associated with the Dmw0 configuration.
- **Signature**: `pub fn mat(&self) -> MemoryAccessType`

### `vseg()`

- **Description**: Returns the virtual segment size (`usize`) for the Dmw0 configuration.
- **Signature**: `pub fn vseg(&self) -> usize
```

--------------------------------

### TlbREntry Conversions

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbrentry/struct.TlbREntry.html

Demonstrates conversions to and from the TlbREntry structure.

```APIDOC
## impl From<usize> for TlbREntry

### fn from(bits: usize) -> Self
Converts a `usize` value into a `TlbREntry`.
```

--------------------------------

### Get Pwch Dir3 Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/struct.Pwch.html

Retrieves the starting memory address for the level 3 directory in the page table structure.

```rust
pub fn dir3_base(&self) -> usize
```

--------------------------------

### Pwch Register Accessors

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/pwch.rs.html

Provides methods to get the starting address and width of level 3 and level 4 directories from the PWCH register.

```APIDOC
## Pwch Register Accessors

### Description
These methods allow reading specific fields from the PWCH register, which defines aspects of the page table structure.

### Methods

- `dir3_base()`: Returns the starting address of the level 3 directory.
- `dir3_width()`: Returns the number of index bits for the level 3 directory (0 indicates no such level).
- `dir4_base()`: Returns the starting address of the level 4 directory.
- `dir4_width()`: Returns the number of index bits for the level 4 directory (0 indicates no such level).

### Example
```rust
let pwch = Pwch::new(0x12345678);
let base3 = pwch.dir3_base();
let width3 = pwch.dir3_width();
let base4 = pwch.dir4_base();
let width4 = pwch.dir4_width();
```
```

--------------------------------

### Set Exception Entry Point (loongArch64)

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/eentry/fn.set_eentry.html

Use this function to set the exception entry point. It takes a `usize` value representing the entry point address.

```rust
pub fn set_eentry(eentry: usize)
```

--------------------------------

### Read Estat Register

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/estat/fn.read.html

Call the read function to get the current value of the Estat register. No setup or imports are required beyond the module itself.

```rust
pub fn read() -> Estat
```

--------------------------------

### Get Bit Range from CPUCFG

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/cpu.rs.html

Extracts a range of bits from the `bits` field of a `CPUCFG` struct. `start` and `end` define the inclusive range of bits to retrieve.

```rust
pub fn get_bits(&self, start: usize, end: usize) -> usize {
        self.bits.get_bits(start..=end)
    }
```

--------------------------------

### Dmw2 Conversion

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw2/struct.Dmw2.html

Demonstrates the conversion from a `usize` to a `Dmw2` struct.

```APIDOC
## `From<usize>` for `Dmw2`

### `from(bits: usize)`

- **Description**: Converts a `usize` value into a `Dmw2` struct.
- **Signature**: `fn from(bits: usize) -> Self
```

--------------------------------

### Get Page Table Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/struct.Pwcl.html

Retrieves the starting address of the last page table. This is a key component in understanding the memory layout for page table walking.

```rust
pub fn ptbase(&self) -> usize
```

--------------------------------

### Function read() -> Pwcl

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.read.html

This function reads and returns a Pwcl value. No specific setup or constraints are mentioned, implying it's a direct read operation.

```rust
pub fn read() -> Pwcl
```

--------------------------------

### Set Level 3 Directory Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/fn.set_dir3_base.html

Use this function to set the starting address for the level 3 directory. This is typically used in memory management or paging contexts.

```rust
pub fn set_dir3_base(val: usize)
```

--------------------------------

### Llbctl Clone and Copy

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/llbctl/struct.Llbctl.html

Information about cloning and copying Llbctl instances.

```APIDOC
### Clone and Copy

#### `clone()`

Returns a duplicate of the `Llbctl` value.

```rust
impl Clone for Llbctl {
    fn clone(&self) -> Llbctl;
}
```

#### `clone_from()`

Performs copy-assignment from `source` to `self`.

```rust
impl Clone for Llbctl {
    fn clone_from(&mut self, source: &Self);
}
```

#### `Copy` Trait

The `Llbctl` struct implements the `Copy` trait, indicating that it can be copied by simple bitwise copy.

```rust
impl Copy for Llbctl {}
```

--------------------------------

### get_arch

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/cpu.rs.html

Retrieves the architecture information of the CPU.

```APIDOC
## get_arch

### Description
Gets the architecture information of the CPU. This is typically done by reading configuration register 1 and extracting bits 0 to 1.

### Returns
The architecture information as a `usize`.
```

--------------------------------

### Get Type ID of CPUCFG

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/struct.CPUCFG.html

Gets the `TypeId` of the CPUCFG. This is part of the blanket implementation of the `Any` trait.

```rust
fn type_id(&self) -> TypeId
```

--------------------------------

### Set TLB Index Page Size

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbidx/fn.set_ps.html

Sets the page size for the TLB index. Refer to TlbIdx::ps() for more details.

```rust
pub fn set_ps(ps: usize)
```

--------------------------------

### Set Page Table Base Address

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_ptbase.html

Call this function to set the start address of the last page table. It takes the desired base address as a usize argument.

```rust
pub fn set_ptbase(ptbase: usize)
```

--------------------------------

### Blanket Implementations

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/ecfg/struct.LineBasedInterrupt.html

General implementations applicable to various types, including LineBasedInterrupt.

```APIDOC
## Any for T

### Description
Provides runtime type information.

### Method
`type_id(&self) -> TypeId`

## Borrow<T> for T

### Description
Allows immutable borrowing.

### Method
`borrow(&self) -> &T`

## BorrowMut<T> for T

### Description
Allows mutable borrowing.

### Method
`borrow_mut(&mut self) -> &mut T`

## CloneToUninit for T

### Description
Performs copy-assignment to uninitialized memory (nightly-only).

### Method
`clone_to_uninit(&self, dest: *mut u8) -> Self` (unsafe)

## From<T> for T

### Description
Provides a way to create a type from itself.

### Method
`from(t: T) -> T`

## Into<U> for T

### Description
Provides a way to convert a type into another type for which `From` is implemented.

### Method
`into(self) -> U`

## TryFrom<U> for T

### Description
Provides a fallible conversion from one type to another.

### Method
`try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`

### Associated Types
- `Error = Infallible`

## TryInto<U> for T

### Description
Provides a fallible conversion into another type for which `TryFrom` is implemented.

### Method
`try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`

### Associated Types
- `Error = <U as TryFrom<T>>::Error`
```

--------------------------------

### CPUCFG Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/struct.CPUCFG.html

This section details the methods available for the CPUCFG struct, allowing users to read CPU configuration data.

```APIDOC
## pub fn read(index: usize) -> Self

### Description
Reads the CPU configuration at the specified index.

### Parameters
* **index** (usize) - The index of the CPU configuration to read.

### Returns
* Self - The CPUCFG struct representing the configuration.
```

```APIDOC
## pub fn get_bit(&self, index: usize) -> bool

### Description
Checks if a specific bit is set in the CPU configuration.

### Parameters
* **index** (usize) - The index of the bit to check.

### Returns
* bool - True if the bit is set, false otherwise.
```

```APIDOC
## pub fn get_bits(&self, start: usize, end: usize) -> usize

### Description
Retrieves a range of bits from the CPU configuration.

### Parameters
* **start** (usize) - The starting index of the bit range (inclusive).
* **end** (usize) - The ending index of the bit range (inclusive).

### Returns
* usize - The value represented by the specified bits.
```

--------------------------------

### Set PWCH Register Fields

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/pwch.rs.html

These functions allow setting the starting address and width for level 3 and level 4 directories in the PWCH register. Use these to configure the page table structure.

```rust
/// Set the starting address of the level 3 directory.
pub fn set_dir3_base(val: usize) {
    set_csr_loong_bits!(0x1d, 0..=5, val);
}
```

```rust
/// Set the number of index bits of the level 3 directory. 0 means there is no such level.
pub fn set_dir3_width(val: usize) {
    set_csr_loong_bits!(0x1d, 6..=11, val);
}
```

```rust
/// Set the starting address of the level 4 directory.
pub fn set_dir4_base(val: usize) {
    set_csr_loong_bits!(0x1d, 12..=17, val);
}
```

```rust
/// Set the number of index bits of the level 4 directory. 0 means there is no such level.
pub fn set_dir4_width(val: usize) {
    set_csr_loong_bits!(0x1d, 18..=23, val);
}
```

--------------------------------

### Dwm3 Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw3/struct.Dwm3.html

Provides methods to access raw values and configuration bits for the Dwm3 struct.

```APIDOC
## Dwm3

Direct Mapping Configuration Window 3

### Methods

#### `raw(&self) -> usize`
Returns the raw `usize` representation of the Dwm3 configuration.

#### `plv0(&self) -> bool`
Checks if privilege level 0 is enabled.

#### `plv1(&self) -> bool`
Checks if privilege level 1 is enabled.

#### `plv2(&self) -> bool`
Checks if privilege level 2 is enabled.

#### `plv3(&self) -> bool`
Checks if privilege level 3 is enabled.

#### `mat(&self) -> MemoryAccessType`
Returns the Memory Access Type.

#### `vseg(&self) -> usize`
Returns the virtual segment size.
```

--------------------------------

### TlbIdx Trait Implementations

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbidx/struct.TlbIdx.html

Demonstrates trait implementations for the TlbIdx struct, including Clone, From, and Copy.

```APIDOC
## TlbIdx Trait Implementations

### `impl Clone for TlbIdx`

#### `fn clone(&self) -> TlbIdx`
Returns a duplicate of the value.

#### `fn clone_from(&mut self, source: &Self)`
Performs copy-assignment from `source`.

### `impl From<usize> for TlbIdx`

#### `fn from(bits: usize) -> Self`
Converts to this type from the input type.

### `impl Copy for TlbIdx`
```

--------------------------------

### set_dir4_base

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwch/fn.set_dir4_base.html

Sets the starting address of the level 4 directory.

```APIDOC
## Function set_dir4_base

### Description
Set the starting address of the level 4 directory.

### Signature
```rust
pub fn set_dir4_base(val: usize)
```

### Parameters
* `val` (usize): The starting address for the level 4 directory.
```

--------------------------------

### Set STLB Page Size

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/stlbps.rs.html

Configures the `log(RealPageSize)/log(2)` for the STLBPS register. For instance, a page size of 16KB is set using `PS`=`0xE`.

```rust
/// Set the `log(RealPageSize)/log(2)`
/// For example, if the page size is 16KB, then `PS`=`0xE`.

pub fn set_ps(page_size: usize) {
    set_csr_loong_bits!(0x1e, 0..=5, page_size);
}
```

--------------------------------

### Get Trap Information

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/estat/struct.Estat.html

Retrieves the Trap information associated with the Estat.

```rust
pub fn cause(&self) -> Trap
```

--------------------------------

### TlbREntry Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbrentry/struct.TlbREntry.html

Provides methods to interact with the TlbREntry structure, including retrieving the raw bits and the entry address.

```APIDOC
## impl TlbREntry

### pub fn raw(&self) -> usize
Retrieves the raw `usize` representation of the TLB entry.

### pub fn addr(&self) -> usize
Gets the TLB refill entry base address.
```

--------------------------------

### Check Dwm3 Privilege Levels

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw3/struct.Dwm3.html

Checks the privilege levels (PLV0, PLV1, PLV2, PLV3) of the Dwm3 configuration.

```rust
pub fn plv0(&self) -> bool
```

```rust
pub fn plv1(&self) -> bool
```

```rust
pub fn plv2(&self) -> bool
```

```rust
pub fn plv3(&self) -> bool
```

--------------------------------

### Get Core ID

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/cpuid/struct.CpuId.html

Retrieves the core ID from the CpuId register.

```APIDOC
### pub fn core_id(&self) -> usize

Source§

Returns the core id.
```

--------------------------------

### set_ptbase Function

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/fn.set_ptbase.html

Sets the start address of the last page table.

```APIDOC
## set_ptbase

### Description
Set the start address of the last page table.

### Signature
```rust
pub fn set_ptbase(ptbase: usize)
```

### Parameters
* `ptbase` (usize) - The start address of the last page table.
```

--------------------------------

### Get Type ID

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/time/struct.Time.html

Retrieves the TypeId of an object. This is part of the Any trait implementation.

```rust
fn type_id(&self) -> TypeId

```

--------------------------------

### Implement PartialEq for CpuMode

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/enum.CpuMode.html

Allows for equality comparisons between CpuMode instances. This enables checking if two CPU modes are the same.

```rust
impl PartialEq for CpuMode {
    fn eq(&self, other: &CpuMode) -> bool {
        // ... implementation details ...
    }
    fn ne(&self, other: &Rhs) -> bool {
        // ... implementation details ...
    }
}
```

--------------------------------

### Get Exception Sub-Code (EsubCode)

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/estat/struct.Estat.html

Returns the second-level encoding of the triggered exceptions.

```rust
pub fn esubcode(&self) -> usize
```

--------------------------------

### TLBREHI Register Field Accessors

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/tlbrehi.rs.html

Provides methods to get and set the page size (ps) and virtual page number (vppn) for the TLBREHI register. These are crucial for configuring TLB behavior during refill exceptions.

```rust
impl TlbREhi {
    /// Page size specified for `TLB` refill exception.
    /// That is, if `CSR.TLBRERA.IsTLBR`=1,
    /// `TLBWR` or `TLBFILL` instructions write this `PS` field into the TLB entry.
    pub fn ps(&self) -> usize {
        self.bits.get_bits(0..=5)
    }
    pub fn set_ps(&mut self, page_size: usize) -> &mut Self {
        self.bits.set_bits(0..=5, page_size);
        self
    }
    /// When CSR.TLBRERA.IsTLBR=1, the value of VPPN used for querying TLB when executing TLBSRCH instruction,
    /// and the value of VPPN field of TLB table entry written when executing TLBWR and TLBFILL instructions come from here.
    /// When a TLB refill exception is triggered, the [VALEN-1:13] bits of the virtual address that triggered the exception are recorded here.
    pub fn vppn(&self) -> usize {
        self.bits.get_bits(13..VALEN)
    }
}
```

--------------------------------

### Get Local Interrupt Status

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/estat/struct.Estat.html

Returns the local interrupt status from the Estat.

```rust
pub fn is(&self) -> usize
```

--------------------------------

### Dmw2 Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw2/struct.Dmw2.html

Provides methods to interact with the Dmw2 struct, allowing retrieval of raw register values and specific configuration parameters.

```APIDOC
## Dmw2 Struct Methods

### `raw()`

- **Description**: Returns the raw `usize` value of the Dmw2 register.
- **Signature**: `pub fn raw(&self) -> usize`

### `plv0()`

- **Description**: Checks if Privilege Level 0 (PLV0) is enabled.
- **Signature**: `pub fn plv0(&self) -> bool`

### `plv1()`

- **Description**: Checks if Privilege Level 1 (PLV1) is enabled.
- **Signature**: `pub fn plv1(&self) -> bool`

### `plv2()`

- **Description**: Checks if Privilege Level 2 (PLV2) is enabled.
- **Signature**: `pub fn plv2(&self) -> bool`

### `plv3()`

- **Description**: Checks if Privilege Level 3 (PLV3) is enabled.
- **Signature**: `pub fn plv3(&self) -> bool`

### `mat()`

- **Description**: Returns the Memory Access Type (MAT) configuration.
- **Signature**: `pub fn mat(&self) -> MemoryAccessType`

### `vseg()`

- **Description**: Returns the Virtual Segment (VSEG) size configuration.
- **Signature**: `pub fn vseg(&self) -> usize
```

--------------------------------

### Get Raw Register Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/cpuid/struct.CpuId.html

Retrieves the raw value of the CpuId register as a usize.

```APIDOC
### pub fn raw(&self) -> usize

Source§

Returns the raw value of the CpuId register.
```

--------------------------------

### Clone to Uninit (Nightly)

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/asid/struct.Asid.html

Performs copy-assignment from self to an uninitialized memory location. This is a nightly-only experimental API.

```rust
unsafe fn clone_to_uninit(&self, dest: *mut u8)
```

--------------------------------

### raw() - Get raw register value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/prmd/struct.Prmd.html

Returns the raw `usize` value of the PRMD register.

```APIDOC
## impl Prmd

### pub fn raw(&self) -> usize

Returns the raw value of the PRMD register.
```

--------------------------------

### Get Line-Based Interrupt Status

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/ecfg/struct.Ecfg.html

Returns the local interrupt status, represented by the LineBasedInterrupt type.

```rust
pub fn lie(&self) -> LineBasedInterrupt
```

--------------------------------

### get_support_rplv

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/cpu.rs.html

Checks if the CPU supports Register Protection Level Verification.

```APIDOC
## get_support_rplv

### Description
Checks if the CPU supports Register Protection Level Verification (RPLV). This is typically done by reading configuration register 1 and checking bit 23.

### Returns
`true` if RPLV is supported, `false` otherwise.
```

--------------------------------

### Prcfg1 Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/prcfg1/struct.Prcfg1.html

This section details the public methods available on the Prcfg1 struct for retrieving configuration details.

```APIDOC
## Prcfg1 Struct Methods

### `raw()`

Returns the raw value of the Prcfg1 configuration.

#### Signature
`pub fn raw(&self) -> usize`

### `save_num()`

Returns the number of SAVE control and status registers.

#### Signature
`pub fn save_num(&self) -> usize`

### `timer_bits()`

Returns the number of valid bit width of the timer.

#### Signature
`pub fn timer_bits(&self) -> usize`

### `vs_max()`

Returns the maximum value that can be set for the exception and interrupt vector entry spacing (CSR.ECTL.VS).

#### Signature
`pub fn vs_max(&self) -> usize`
```

--------------------------------

### Get ASID Width

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/asid/struct.Asid.html

Returns the width of the ASID field. This method is part of the Asid implementation.

```rust
pub fn asid_width(&self) -> usize
```

--------------------------------

### Register TLB Entry Functions

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/all.html

Functions for reading and setting TLB entries.

```APIDOC
## register::tlbrentry::read

### Description
Reads the value of a TLB entry.

### Method
N/A (Function Call)

### Endpoint
N/A

### Parameters
- **index** (integer) - The index of the TLB entry to read.

### Request Example
```
register::tlbrentry::read(index=0)
```

### Response
#### Success Response
- **value** (integer) - The value of the TLB entry.

#### Response Example
```
0xABCDEF01
```
```

```APIDOC
## register::tlbrentry::set_tlbrentry

### Description
Sets the value of a TLB entry.

### Method
N/A (Function Call)

### Endpoint
N/A

### Parameters
- **index** (integer) - The index of the TLB entry to set.
- **value** (integer) - The value to set for the TLB entry.

### Request Example
```
register::tlbrentry::set_tlbrentry(index=0, value=0x12345678)
```

### Response
#### Success Response
None

#### Response Example
None
```

--------------------------------

### set_dir2_base Function

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/index.html

Sets the starting address of the next level directory for page table walks.

```APIDOC
## Function set_dir2_base

Set the starting address of the next level directory.
```

--------------------------------

### get_support_rplv

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/fn.get_support_rplv.html

Checks if the RPLV feature is supported by the CPU. Returns true if supported, false otherwise.

```APIDOC
## Function get_support_rplv

### Description
Checks if the RPLV feature is supported by the CPU.

### Signature
```rust
pub fn get_support_rplv() -> bool
```

### Returns
- `bool`: `true` if RPLV is supported, `false` otherwise.
```

--------------------------------

### set_dir1_base Function

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/index.html

Sets the starting address of the lowest level directory for page table walks.

```APIDOC
## Function set_dir1_base

Set the starting address of the lowest level directory.
```

--------------------------------

### set_va32l1

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/misc/fn.set_va32l1.html

Set to 1 to enable 32-bit address mode at the PLV1 privilege level.

```APIDOC
## set_va32l1

### Description
Set to 1 to enable 32-bit address mode at the PLV1 privilege level.

### Signature
```rust
pub fn set_va32l1(value: bool)
```

### Parameters
* `value` (bool) - If true, enables 32-bit address mode at PLV1.
```

--------------------------------

### Read Llbctl Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/llbctl/fn.read.html

This function reads and returns an Llbctl value. No specific setup or constraints are mentioned.

```rust
pub fn read() -> Llbctl
```

--------------------------------

### Get ASID Width

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/asid.rs.html

Retrieves the ASID width from the register bits. This indicates the number of bits used for the ASID.

```rust
    /// The ASID width
    pub fn asid_width(&self) -> usize {
        self.bits.get_bits(16..=23)
    }
}
```

--------------------------------

### Dmw2 Clone Implementation

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw2/struct.Dmw2.html

Details the cloning behavior for the Dmw2 struct.

```APIDOC
## `Clone` for `Dmw2`

### `clone()`

- **Description**: Returns a duplicate of the `Dmw2` value.
- **Signature**: `fn clone(&self) -> Dmw2`

### `clone_from()`

- **Description**: Performs copy-assignment from a source `Dmw2` value.
- **Signature**: `fn clone_from(&mut self, source: &Self)
```

--------------------------------

### Get TLB Index

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbidx/struct.TlbIdx.html

Retrieves the index for TLB table entries when executing TLBRD, TLBWR, or TLBSRCH instructions.

```rust
pub fn index(&self) -> usize
```

--------------------------------

### Dwm3 Conversions

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw3/struct.Dwm3.html

Provides conversion methods for the Dwm3 struct.

```APIDOC
## Dwm3 Conversions

### `from(bits: usize) -> Self`
Converts a `usize` value into a `Dwm3` struct.
```

--------------------------------

### Dwm3 Trait Implementations

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw3/struct.Dwm3.html

Details the trait implementations available for the Dwm3 struct, including Clone, Debug, and Copy.

```APIDOC
## Dwm3 Trait Implementations

### `impl Clone for Dwm3`

#### `clone(&self) -> Dwm3`
Returns a duplicate of the value.

#### `clone_from(&mut self, source: &Self)`
Performs copy-assignment from `source`.

### `impl Debug for Dwm3`

#### `fmt(&self, f: &mut Formatter<'_>) -> Result`
Formats the value using the given formatter.

### `impl Copy for Dwm3`
Indicates that the type is copyable.
```

--------------------------------

### Get Raw ASID Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/asid/struct.Asid.html

Retrieves the raw ASID value as a usize. This method is part of the Asid implementation.

```rust
pub fn raw(&self) -> usize
```

--------------------------------

### Get Support for IOCSR

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/fn.get_support_iocsr.html

This function checks if the CPU supports IOCSR. It returns a boolean value indicating support.

```rust
pub fn get_support_iocsr() -> bool
```

--------------------------------

### Pgdl Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pgdl/struct.Pgdl.html

Provides methods to interact with the Pgdl register, including retrieving the raw value and the base address, and setting the base address.

```APIDOC
## Implementations

### impl Pgdl

#### pub fn raw(&self) -> usize
Returns the raw value of the Pgdl register.
```

```APIDOC
#### pub fn base(&self) -> usize
Returns the base address of the global directory in the lower half address space. By lower half address space, it means that the [VALEN-1] bit of the virtual address is equal to 0.
```

```APIDOC
#### pub fn set_base(&mut self, val: usize) -> &mut Self
Sets the base address of the global directory in the lower half address space.
```

--------------------------------

### Read StlbPs Register

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/stlbps/fn.read.html

Call this function to read the value of the StlbPs register. No specific setup or constraints are mentioned.

```rust
pub fn read() -> StlbPs
```

--------------------------------

### Read Prcfg1 Register

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/prcfg1/fn.read.html

Call this function to retrieve the current value of the Prcfg1 register. No specific setup is required.

```rust
pub fn read() -> Prcfg1
```

--------------------------------

### Estat Conversions and Traits

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/estat/struct.Estat.html

Details on converting Estat from a usize and its trait implementations like Clone and Copy.

```APIDOC
## Estat Conversions and Traits

### `impl From<usize> for Estat`

#### `fn from(bits: usize) -> Self`
Converts to this type from the input type.

### `impl Copy for Estat`

### `impl Clone for Estat`

#### `fn clone(&self) -> Estat`
Returns a duplicate of the value.

#### `fn clone_from(&mut self, source: &Self)`
Performs copy-assignment from `source`.
```

--------------------------------

### Get WE field from PRMD

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/base/prmd.rs.html

Retrieves the WE (Watchpoint Enable) bit from the PRMD register. This indicates whether watchpoints were enabled before the exception.

```rust
pub fn pwe(&self) -> bool {
        self.bits.get_bit(3)
    }
```

--------------------------------

### read()

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/prmd/index.html

Reads the current Pre-exception Mode Information (PRMD) from the processor.

```APIDOC
## Function read()

### Description
Reads the PRMD value.

### Returns
Prmd - The current PRMD value.
```

--------------------------------

### Implement From<usize> for CpuMode

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/enum.CpuMode.html

Provides a way to create a CpuMode instance from a usize value. This is useful for converting raw integer representations of CPU modes into the strongly-typed enum.

```rust
impl From<usize> for CpuMode {
    fn from(value: usize) -> Self {
        // ... implementation details ...
    }
}
```

--------------------------------

### Tval::time_val() - Get Timer Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tval/struct.Tval.html

Retrieves the timer value as a usize. This method is part of the Tval struct implementation.

```rust
pub fn time_val(&self) -> usize
```

--------------------------------

### Set TLBREHI Page Size

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/mmu/tlbrehi.rs.html

Configures the page size for TLBWR and TLBFILL instructions when CSR.TLBRERA.IsTLBR is set to 1. Use this function to specify the desired page size.

```rust
/// Set the page size used by `TLBWR` & `TLBFILL` when `CSR.TLBRERA.IsTLBR`=1.
pub fn set_ps(ps: usize) {
    set_csr_loong_bits!(0x8e, 0..=5, ps);
}
```

--------------------------------

### Get Timer Frequency

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/time/fn.get_timer_freq.html

Retrieves the system timer frequency. This function is part of the loongArch64 platform's time module.

```rust
pub fn get_timer_freq() -> usize
```

--------------------------------

### set_ps

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbidx/fn.set_ps.html

Sets the Page Size (PS) for the TLB index. Refer to TlbIdx::ps() for more details.

```APIDOC
## Function set_ps

### Signature
```rust
pub fn set_ps(ps: usize)
```

### Description
Sets the Page Size (PS) for the TLB index. See `TlbIdx::ps()`.
```

--------------------------------

### Get Virtual Segment for Dmw0

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw0/struct.Dmw0.html

Retrieves the virtual segment (`usize`) value from the Dmw0 register. This is relevant for memory segmentation.

```rust
pub fn vseg(&self) -> usize
```

--------------------------------

### Get Specific Bit from CPUCFG

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/struct.CPUCFG.html

Retrieves the boolean value of a specific bit from the CPUCFG. The index specifies which bit to check.

```rust
pub fn get_bit(&self, index: usize) -> bool
```

--------------------------------

### Read Euen Register

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/euen/fn.read.html

This function reads the value of the Euen register. No specific setup or imports are required beyond the module itself.

```rust
pub fn read() -> Euen
```

--------------------------------

### Get Local Interrupt Status (lie)

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/base/ecfg.rs.html

Retrieves the local interrupt status from the ECFG register, returning a LineBasedInterrupt bitflags value.

```rust
pub fn lie(&self) -> LineBasedInterrupt {
    LineBasedInterrupt::from_bits_truncate(self.bits.get_bits(0..13))
}
```

--------------------------------

### Euen Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/euen/struct.Euen.html

Provides methods to access and interpret the enable bits for various instruction set extensions.

```APIDOC
## Euen

Extended Component Unit Enable (EUEN)

### Description

The Euen struct manages software-configurable enable bits for instruction set extensions. When these controls are disabled, execution of the corresponding instruction triggers an instruction unavailable exception. This mechanism is used for context saving scope determination and can also be used by hardware for circuit power control.

### Methods

#### `raw(&self) -> usize`

Returns the raw register value.

#### `fpe(&self) -> bool`

Checks the base floating-point instruction enable bit. If disabled, execution of the base floating-point instruction triggers a floating-point instruction disable exception (FPD).

#### `sxe(&self) -> bool`

Checks the base SIMD extension instruction enable bit. If disabled, execution of the SIMD instruction triggers an SIMD extension instruction disable exception (SXD).

#### `asxe(&self) -> bool`

Checks the Advanced SIMD extension instruction enable bit. If disabled, execution of the Advanced SIMD instruction triggers an Advanced SIMD extension instruction disable exception (ASXD).

#### `bte(&self) -> bool`

Checks the Binary Translation extension instruction enable bit. If disabled, execution of the Binary Translation instruction triggers a Binary Translation extension instruction disable exception (BTD).

```

--------------------------------

### Badi Type Conversions and Traits

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/badi/struct.Badi.html

Details on how to convert to and from the Badi type, and its trait implementations.

```APIDOC
## Trait Implementations

### impl Clone for Badi

#### fn clone(&self) -> Badi
Returns a duplicate of the value.

#### fn clone_from(&mut self, source: &Self)
Performs copy-assignment from `source`.

### impl From<usize> for Badi

#### fn from(bits: usize) -> Self
Converts to this type from the input type.

### impl Copy for Badi
```

--------------------------------

### Get Timer Number

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tid/struct.Tid.html

Retrieves the timer number, which can be configured by software. On processor core reset, it can be reset to the same value as the CoreID in CSR.CPUID.

```rust
pub fn tid(&self) -> usize
```

--------------------------------

### set_ps

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbrehi/fn.set_ps.html

Sets the page size used by TLBWR & TLBFILL when CSR.TLBRERA.IsTLBR is 1.

```APIDOC
## Function set_ps

### Description
Sets the page size used by `TLBWR` & `TLBFILL` when `CSR.TLBRERA.IsTLBR`=1.

### Signature
```rust
pub fn set_ps(ps: usize)
```

### Parameters
* `ps` (usize) - The page size to set.
```

--------------------------------

### Dmw1 Methods

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw1/struct.Dmw1.html

Provides methods to access various fields and configurations of the Dmw1 struct.

```APIDOC
## Dmw1 Struct Methods

### `raw()`

- **Description**: Returns the raw `usize` representation of the Dmw1 configuration.
- **Signature**: `pub fn raw(&self) -> usize`

### `plv0()`

- **Description**: Checks if privilege level 0 is enabled.
- **Signature**: `pub fn plv0(&self) -> bool`

### `plv1()`

- **Description**: Checks if privilege level 1 is enabled.
- **Signature**: `pub fn plv1(&self) -> bool`

### `plv2()`

- **Description**: Checks if privilege level 2 is enabled.
- **Signature**: `pub fn plv2(&self) -> bool`

### `plv3()`

- **Description**: Checks if privilege level 3 is enabled.
- **Signature**: `pub fn plv3(&self) -> bool`

### `mat()`

- **Description**: Returns the Memory Access Type configuration.
- **Signature**: `pub fn mat(&self) -> MemoryAccessType`

### `vseg()`

- **Description**: Returns the virtual segment size configuration.
- **Signature**: `pub fn vseg(&self) -> usize
```

--------------------------------

### Get Page Table Width

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pwcl/struct.Pwcl.html

Retrieves the width (in bits) of the page table entries. This determines how much memory each entry occupies.

```rust
pub fn ptwidth(&self) -> usize
```

--------------------------------

### TlbElo0::from<usize>

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/tlbelo0/struct.TlbElo0.html

Creates a TlbElo0 register from a `usize` value.

```APIDOC
## fn from(bits: usize) -> Self

Converts to this type from the input type (`usize`).
```

--------------------------------

### Get Memory Access Type for Dmw0

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/dmw0/struct.Dmw0.html

Retrieves the `MemoryAccessType` associated with the Dmw0 register. This indicates the type of memory access allowed.

```rust
pub fn mat(&self) -> MemoryAccessType
```

--------------------------------

### Get Core ID from CpuId

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/cpuid/struct.CpuId.html

Extracts and returns the core ID from the CpuId register. This provides the specific identifier for the processor core.

```rust
pub fn core_id(&self) -> usize
```

--------------------------------

### get_arch

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/cpu/fn.get_arch.html

Retrieves the architecture information for the loongArch64 CPU. This function returns the architecture as a usize value.

```APIDOC
## get_arch

### Description
获取架构信息 (Retrieves architecture information).

### Signature
```rust
pub fn get_arch() -> usize
```

### Returns
- `usize`: The architecture information.
```

--------------------------------

### Get ASID Field

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/asid/struct.Asid.html

Extracts the ASID field, which identifies the address space of the virtual address. This method is part of the Asid implementation.

```rust
pub fn asid(&self) -> usize
```

--------------------------------

### set_va32l2

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/misc/fn.set_va32l2.html

Sets the 32-bit address mode at the PLV2 privilege level. Pass `true` to enable, `false` to disable.

```APIDOC
## Function set_va32l2

### Description
Set to 1 to enable 32-bit address mode at the PLV2 privilege level.

### Signature
```rust
pub fn set_va32l2(value: bool)
```

### Parameters
* `value` (bool) - `true` to enable 32-bit address mode, `false` to disable.
```

--------------------------------

### set_base Function

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/pgdl/fn.set_base.html

Sets the base address of the global directory in the lower half address space. The address must be 4K page aligned.

```APIDOC
## Function set_base

### Signature
```rust
pub fn set_base(val: usize)
```

### Description
Set the base address of the global directory in the lower half address space.

### Warning
The address MUST be 4K page aligned.
```

--------------------------------

### Define and Read Prcfg3 CSR

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/base/prcfg3.rs.html

Defines the Prcfg3 CSR and implements reading from its address. This is a foundational setup for interacting with the Prcfg3 register.

```rust
use bit_field::BitField;

impl_define_csr!(Prcfg3, "Privileged Resource Configuration 1");

impl_read_csr!(0x23, Prcfg3);
```

--------------------------------

### Read Ticlr Value

Source: https://docs.rs/loongArch64/0.2.6/loongArch64/register/ticlr/fn.read.html

This function reads the current value of the Ticlr register. No specific setup is required beyond calling the function.

```rust
pub fn read() -> Ticlr
```

--------------------------------

### Set Page Translation Mode (PG)

Source: https://docs.rs/loongArch64/0.2.6/src/loongArch64/register/base/crmd.rs.html

Sets the page translation mode. Pass `true` to enable, `false` to disable.

```rust
pub fn set_pg(pg: bool) {
    set_csr_loong_bit!(0x0, 4, pg);
}
```
Tokens:
Raw