### Install Arachne-PNR Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Build and install the place-and-route tool Arachne-PNR from source. ```bash git clone https://github.com/YosysHQ/arachne-pnr.git arachne-pnr cd arachne-pnr make -j$(nproc) sudo make install ``` -------------------------------- ### Install Yosys Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Install the Verilog synthesis tool Yosys from source. ```bash git clone https://github.com/YosysHQ/yosys.git yosys cd yosys make -j$(nproc) sudo make install ``` -------------------------------- ### Install IceStorm tools Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Clone, build, and install the IceStorm tools (icepack, icebox, iceprog, icetime) to /usr/local. ```bash git clone https://github.com/YosysHQ/icestorm.git icestorm cd icestorm make -j$(nproc) sudo make install ``` -------------------------------- ### Example script for implementing and programming the rot example with Yosys, arachne-pnr, icepack, and iceprog Source: https://prjicestorm.readthedocs.io/en/latest/overview.html This script synthesizes the rot example for the iCEstick development board using Yosys, performs place-and-route with arachne-pnr, and programs the resulting bitstream with iceprog. ```bash yosys -p "synth_ice40 -blif rot.blif" rot.v arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc icepack rot.asc rot.bin iceprog rot.bin ``` -------------------------------- ### icebox_explain example output Source: https://prjicestorm.readthedocs.io/en/latest/overview.html Sample output of running icebox_explain on the example design 'top' after the full Yosys, Arachne-PNR, and icepack flow. It reveals the parsed tile and logic cell details. ```text $ icebox_explain example.asc Reading file 'example.asc'.. Fabric size (without IO tiles): 12 x 16 .io_tile 0 10 IOB_1 PINTYPE_0 IOB_1 PINTYPE_3 IOB_1 PINTYPE_4 IoCtrl IE_0 IoCtrl IE_1 IoCtrl REN_0 buffer local_g0_5 io_1/D_OUT_0 buffer logic_op_tnr_5 local_g0_5 .io_tile 0 14 IOB_1 PINTYPE_0 IoCtrl IE_1 IoCtrl REN_0 buffer io_1/D_IN_0 span4_vert_b_6 .io_tile 0 11 IOB_0 PINTYPE_0 IoCtrl IE_0 IoCtrl REN_1 routing span4_vert_t_14 span4_horz_13 .logic_tile 1 11 LC_5 0001000000000000 0000 buffer local_g0_0 lutff_5/in_1 buffer local_g3_0 lutff_5/in_0 buffer neigh_op_lft_0 local_g0_0 buffer sp4_h_r_24 local_g3_0 ``` -------------------------------- ### Install NextPNR (place&route tool, Arachne-PNR replacement) Source: https://prjicestorm.readthedocs.io/en/latest/overview.html This sequence clones the nextpnr repository recursively, configures it for the ice40 architecture, builds, and installs it to /usr/local. ```bash git clone --recursive https://github.com/YosysHQ/nextpnr nextpnr cd nextpnr cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . make -j$(nproc) sudo make install ``` -------------------------------- ### Install prerequisites on Fedora 24 Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Install build dependencies on Fedora 24 using dnf. ```bash sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison \ flex readline-devel gawk tcl-devel libffi-devel git mercurial \ graphviz python-xdot pkgconfig python python3 libftdi-devel \ qt5-devel python3-devel boost-devel boost-python3-devel eigen3-devel ``` -------------------------------- ### Install prerequisites on Ubuntu 14.04 Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Install development packages required for building the IceStorm tools, Arachne-PNR, and Yosys on Ubuntu 14.04. ```bash sudo apt-get install build-essential clang bison flex libreadline-dev \ gawk tcl-dev libffi-dev git mercurial graphviz \ xdot pkg-config python python3 libftdi-dev \ qt5-default python3-dev libboost-all-dev cmake libeigen3-dev ``` -------------------------------- ### Install libftdi0 on OSX with port or brew Source: https://prjicestorm.readthedocs.io/en/latest/_sources/notes_osx.rst.txt Install the libftdi0 package on OSX using either Mac Ports or Homebrew. The libftdi package has been renamed to libftdi0, and Mac Ports installs to /opt instead of /usr. ```shell port install libftdi0 ``` ```shell brew install libftdi0 ``` -------------------------------- ### Example Verilog and PCF files Source: https://prjicestorm.readthedocs.io/en/latest/overview.html Example source files for synthesizing a simple AND circuit: a Verilog module 'top' and a PCF file defining I/O pin assignments. These files are used in the Yosys/Arachne-PNR flow. ```verilog // example.v module top (input a, b, output y); assign y = a & b; endmodule # example.pcf set_io a 1 set_io b 10 set_io y 11 ``` ```text $ yosys -p 'synth_ice40 -top top -blif example.blif' example.v $ arachne-pnr -d 1k -o example.asc -p example.pcf example.blif $ icepack example.asc example.bin ``` -------------------------------- ### Install NextPNR Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Build and install the NextPNR tool (Arachne-PNR replacement) with generic build flow using cmake. ```bash git clone --recursive https://github.com/YosysHQ/nextpnr nextpnr cd nextpnr cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . make -j$(nproc) sudo make install ``` -------------------------------- ### Install prerequisites on Fedora 24 Source: https://prjicestorm.readthedocs.io/en/latest/overview.html This command installs all required build dependencies for the open source iCE40 flow on Fedora 24. ```bash sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison \ flex readline-devel gawk tcl-devel libffi-devel git mercurial \ graphviz python-xdot pkgconfig python python3 libftdi-devel \ qt5-devel python3-devel boost-devel boost-python3-devel eigen3-devel ``` -------------------------------- ### Install prerequisites on Ubuntu 14.04 Source: https://prjicestorm.readthedocs.io/en/latest/overview.html This command installs all required build dependencies for the open source iCE40 flow on Ubuntu 14.04. ```bash sudo apt-get install build-essential clang bison flex libreadline-dev \ gawk tcl-dev libffi-dev git mercurial graphviz \ xdot pkg-config python python3 libftdi-dev \ qt5-default python3-dev libboost-all-dev cmake libeigen3-dev ``` -------------------------------- ### iceunpack output: .logic_tile bitstream block Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Example output from the iceunpack program, showing a block of 0 and 1 characters for a logic tile. The bits are referred to as B[y][x] in the documentation, e.g., B0 is the first line, B0[0] the first bit, B15[53] the last bit. ```text .logic_tile 12 12 000000000000000000000000000000000000000000000000000000 000000000000000000000000011010000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000001011000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000001000001000010101010000000000 000000000000000000000000000101010000101010100000000000 ``` -------------------------------- ### Fix iceprog Makefile for ftdi.h not found Source: https://prjicestorm.readthedocs.io/en/latest/_sources/notes_osx.rst.txt Modify the first two lines of iceprog/Makefile to fix the 'ftdi.h not found' error. This adds the /opt/local paths for the lib and header, since Mac Ports installs to /opt instead of /usr. ```makefile LDLIBS = -L/usr/local/lib -L/opt/local/lib -lftdi -lm CFLAGS = -MD -O0 -ggdb -Wall -std=c99 -I/usr/local/include -I/opt/local/include/ ``` -------------------------------- ### Verilog and PCF files (example.v, example.pcf) Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Missing 'example.v' and 'example.pcf'. Shows a simple 'top' module with assign y = a & b, and pins to use for 'a', 'b', 'y'. ```verilog // example.v module top (input a, b, output y); assign y = a & b; endmodule # example.pcf set_io a 1 set_io b 10 set_io y 11 ``` -------------------------------- ### icebox_explain output for example.asc Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Sample run of icebox_explain example.asc showing fabric size 12 x 16, AND configuration bits, and buffers. ```shell $ icebox_explain example.asc Reading file 'example.asc'.. Fabric size (without IO tiles): 12 x 16 .io_tile 0 10 IOB_1 PINTYPE_0 IOB_1 PINTYPE_3 IOB_1 PINTYPE_4 IoCtrl IE_0 IoCtrl IE_1 IoCtrl REN_0 buffer local_g0_5 io_1/D_OUT_0 buffer logic_op_tnr_5 local_g0_5 .io_tile 0 14 IOB_1 PINTYPE_0 IoCtrl IE_1 IoCtrl REN_0 buffer io_1/D_IN_0 span4_vert_b_6 .io_tile 0 11 IOB_0 PINTYPE_0 IoCtrl IE_0 IoCtrl REN_1 routing span4_vert_t_14 span4_horz_13 .logic_tile 1 11 LC_5 0001000000000000 0000 buffer local_g0_0 lutff_5/in_1 buffer local_g3_0 lutff_5/in_0 buffer neigh_op_lft_0 local_g0_0 buffer sp4_h_r_24 local_g3_0 ``` -------------------------------- ### Yosys, Arachne-PNR, and IcePack commands (shell) Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Command lines to synthesize 'example.v' and 'example.pcf' into a bitstream. Use Yosys synth_ice40 with -top top and -blif example.blif, then arachne-pnr -d 1k -o example.asc -p example.pcf, then icepack to produce example.bin. ```shell $ yosys -p 'synth_ice40 -top top -blif example.blif' example.v $ arachne-pnr -d 1k -o example.asc -p example.pcf example.blif $ icepack example.asc example.bin ``` -------------------------------- ### icebox_vlog output for example.asc and example.pcf Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Sample run of icebox_vlog -p example.pcf example.asc generating Verilog with signal path markers and final assign y = b ? a : 0. ```verilog $ icebox_vlog -p example.pcf example.asc // Reading file 'example.asc'.. module chip (output y, input b, input a); wire y; // io_0_10_1 // (0, 10, 'io_1/D_OUT_0') // (0, 10, 'io_1/PAD') // (0, 10, 'local_g0_5') // (0, 10, 'logic_op_tnr_5') // (0, 11, 'logic_op_rgt_5') // (0, 12, 'logic_op_bnr_5') // (1, 10, 'neigh_op_top_5') // (1, 11, 'lutff_5/out') // (1, 12, 'neigh_op_bot_5') // (2, 10, 'neigh_op_tnl_5') // (2, 11, 'neigh_op_lft_5') // (2, 12, 'neigh_op_bnl_5') wire b; // (0, 11, 'io_0/D_IN_0') // (0, 11, 'io_0/PAD') // (1, 10, 'neigh_op_tnl_0') // (1, 10, 'neigh_op_tnl_4') // (1, 11, 'local_g0_0') // (1, 11, 'lutff_5/in_1') // (1, 11, 'neigh_op_lft_0') // (1, 11, 'neigh_op_lft_4') // (1, 12, 'neigh_op_bnl_0') // (1, 12, 'neigh_op_bnl_4') wire a; // io_0_14_1 // (0, 11, 'span4_horz_13') // (0, 11, 'span4_vert_t_14') // (0, 12, 'span4_vert_b_14') // (0, 13, 'span4_vert_b_10') // (0, 14, 'io_1/D_IN_0') // (0, 14, 'io_1/PAD') // (0, 14, 'span4_vert_b_6') // (0, 15, 'span4_vert_b_2') // (1, 11, 'local_g3_0') // (1, 11, 'lutff_5/in_0') // (1, 11, 'sp4_h_r_24') // (1, 13, 'neigh_op_tnl_2') // (1, 13, 'neigh_op_tnl_6') // (1, 14, 'neigh_op_lft_2') // (1, 14, 'neigh_op_lft_6') // (1, 15, 'neigh_op_bnl_2') // (1, 15, 'neigh_op_bnl_6') // (2, 11, 'sp4_h_r_37') // (3, 11, 'sp4_h_l_37') assign y = b ? a : 0; endmodule ``` -------------------------------- ### Generate timing report with icetime Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Produce a simple timing analysis report for an iCE40 HX1K using the icetime utility. ```bash icetime -tmd hx1k rot.asc ``` -------------------------------- ### icebox_vlog command and Verilog output Source: https://prjicestorm.readthedocs.io/en/latest/overview.html Run icebox_vlog with a PCF constraints file and an ASC bitstream file to generate a Verilog netlist. The output includes module declarations, wire definitions, and LUT assignments with comments showing routing details. ```bash $ icebox_vlog -p example.pcf example.asc // Reading file 'example.asc'.. ``` ```verilog module chip (output y, input b, input a); wire y; // io_0_10_1 // (0, 10, 'io_1/D_OUT_0') // (0, 10, 'io_1/PAD') // (0, 10, 'local_g0_5') // (0, 10, 'logic_op_tnr_5') // (0, 11, 'logic_op_rgt_5') // (0, 12, 'logic_op_bnr_5') // (1, 10, 'neigh_op_top_5') // (1, 11, 'lutff_5/out') // (1, 12, 'neigh_op_bot_5') // (2, 10, 'neigh_op_tnl_5') // (2, 11, 'neigh_op_lft_5') // (2, 12, 'neigh_op_bnl_5') wire b; // io_0_11_0 // (0, 11, 'io_0/D_IN_0') // (0, 11, 'io_0/PAD') // (1, 10, 'neigh_op_tnl_0') // (1, 10, 'neigh_op_tnl_4') // (1, 11, 'local_g0_0') // (1, 11, 'lutff_5/in_1') // (1, 11, 'neigh_op_lft_0') // (1, 11, 'neigh_op_lft_4') // (1, 12, 'neigh_op_bnl_0') // (1, 12, 'neigh_op_bnl_4') wire a; // io_0_14_1 // (0, 11, 'span4_horz_13') // (0, 11, 'span4_vert_t_14') // (0, 12, 'span4_vert_b_14') // (0, 13, 'span4_vert_b_10') // (0, 14, 'io_1/D_IN_0') // (0, 14, 'io_1/PAD') // (0, 14, 'span4_vert_b_6') // (0, 15, 'span4_vert_b_2') // (1, 11, 'local_g3_0') // (1, 11, 'lutff_5/in_0') // (1, 11, 'sp4_h_r_24') // (1, 13, 'neigh_op_tnl_2') // (1, 13, 'neigh_op_tnl_6') // (1, 14, 'neigh_op_lft_2') // (1, 14, 'neigh_op_lft_6') // (1, 15, 'neigh_op_bnl_2') // (1, 15, 'neigh_op_bnl_6') // (2, 11, 'sp4_h_r_37') // (3, 11, 'sp4_h_l_37') assign y = /* LUT 1 11 5 */ b ? a : 0; endmodule ``` -------------------------------- ### icebox_explain cell configuration output Source: https://prjicestorm.readthedocs.io/en/latest/overview.html Shows the icebox_explain program's output that converts config bits into a description of the cell configuration for a logic tile. ```text .logic_tile 12 12 LC_7 0101010110101010 0000 buffer local_g0_2 lutff_7/in_3 buffer local_g1_4 lutff_7/in_0 buffer sp12_h_r_18 local_g0_2 buffer sp12_h_r_20 local_g1_4 ``` -------------------------------- ### Yosys synthesis, PnR, and programming for iCEstick Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Commands to synthesize, place-and-route with arachne-pnr, pack and program an iCE40 bitstream. Targets the iCEstick development board. ```bash yosys -p "synth_ice40 -blif rot.blif" rot.v aarachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc icepack rot.asc rot.bin iceprog rot.bin ``` -------------------------------- ### Generate timing analysis report with icetime Source: https://prjicestorm.readthedocs.io/en/latest/overview.html This command generates a simple timing analysis report for the rot.asc file using the icetime utility with the hx1k device. ```bash icetime -tmd hx1k rot.asc ``` -------------------------------- ### Udev rule for unprivileged iCEstick access Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt Create /etc/udev/rules.d/53-lattice-ftdi.rules with this line to allow unbuffered uploading to iCEstick and iCE40-HX8K Breakout Board as unprivileged user. ```udev ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0660", GROUP="plugdev", TAG+="uaccess" ``` -------------------------------- ### BibTeX citation for Project IceStorm Source: https://prjicestorm.readthedocs.io/en/latest/_sources/overview.rst.txt BibTeX entry for citing Project IceStorm in papers and reports. Use this entry with the \cite command to reference the project documentation. ```bibtex @MISC{IceStorm, author = {Claire Wolf and Mathias Lasser}, title = {Project IceStorm}, howpublished = "\url{https://prjicestorm.readthedocs.io/}" } ``` -------------------------------- ### Check FTDI driver with kextstat Source: https://prjicestorm.readthedocs.io/en/latest/_sources/notes_osx.rst.txt Check if the FTDI kernel driver is loaded on OSX (Mountain Lion 10.8.2). This is the first step to fix the 'Can't find iCE FTDI USB device' error when uploading code to the FPGA. ```shell kextstat | grep FTDIUSBSerialDriver ``` -------------------------------- ### Switch yosys Makefile from clang to gcc Source: https://prjicestorm.readthedocs.io/en/latest/_sources/notes_osx.rst.txt Edit the yosys Makefile to work around the ' not found' compiler error. Comment out the clang line and uncomment the gcc line to compile with gcc instead. ```makefile #CONFIG := clang CONFIG := gcc ``` -------------------------------- ### Unload FTDI driver with kextunload Source: https://prjicestorm.readthedocs.io/en/latest/_sources/notes_osx.rst.txt Unload the FTDI kernel driver on OSX (Mountain Lion 10.8.2) to fix the 'Can't find iCE FTDI USB device' error. Run this after confirming the driver is loaded with kextstat, then repeat kextstat to verify it was unloaded. ```shell sudo kextunload -b com.FTDI.driver.FTDIUSBSerialDriver ``` === COMPLETE CONTENT === This response contains all available snippets from this library. No additional content exists. Do not make further requests.