SAM C20/C21 Microcontroller Datasheet

https://onlinedocs.microchip.com/oxy/GUID-DDF2C9BC-07FB-4ABF-938A-774B157B4519-en-US-10/
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Microchip SAM C20/C21 is a series of ARM Cortex-M0+ microcontrollers with integrated analog and...
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### GET /registers/TXBTIE

Source: https://onlinedocs.microchip.com/oxy/GUID-DDF2C9BC-07FB-4ABF-938A-774B157B4519-en-US-10/GUID-F5DD545D-A502-4194-9C70-F632CAC7B472.html

Retrieves the configuration and status of the Tx Buffer Transmission Interrupt Enable (TXBTIE) register.

```APIDOC
## GET /registers/TXBTIE

### Description
This endpoint returns the current state of the TXBTIE register, which controls the transmission interrupt enable bits for individual Tx Buffers.

### Method
GET

### Endpoint
/registers/TXBTIE

### Parameters
#### Path Parameters
- None

#### Query Parameters
- None

### Request Body
None

### Response
#### Success Response (200)
- **TIEn[31:0]** (integer) - A 32-bit value where each bit represents the interrupt enable status for a specific Tx Buffer (0: Disabled, 1: Enabled).

#### Response Example
{
  "TXBTIE": 0x00000000
}
```

--------------------------------

### GET /registers/sercom/baud

Source: https://onlinedocs.microchip.com/oxy/GUID-DDF2C9BC-07FB-4ABF-938A-774B157B4519-en-US-10/GUID-7D5DCED9-3021-4FC9-BC62-8617655C8770.html

Retrieves the configuration of the BAUD register, which controls the SCL high and low timing periods for host communication.

```APIDOC
## GET /registers/sercom/baud

### Description
Reads the current state of the BAUD register (Offset 0x0C) to determine the SCL timing configuration for the SERCOM peripheral.

### Method
GET

### Endpoint
/registers/sercom/baud

### Parameters
#### Path Parameters
- **None**

### Request Example
{
  "action": "read"
}

### Response
#### Success Response (200)
- **HSBAUDLOW** (integer) - Bits 31:24, High Speed Host Baud Rate Low
- **HSBAUD** (integer) - Bits 23:16, High Speed Host Baud Rate
- **BAUDLOW** (integer) - Bits 15:8, Host Baud Rate Low
- **BAUD** (integer) - Bits 7:0, Host Baud Rate

#### Response Example
{
  "HSBAUDLOW": 0,
  "HSBAUD": 0,
  "BAUDLOW": 0,
  "BAUD": 0
}
```

--------------------------------

### OUTTGL Register Documentation

Source: https://onlinedocs.microchip.com/oxy/GUID-DDF2C9BC-07FB-4ABF-938A-774B157B4519-en-US-10/GUID-863B3938-9DAB-4FD6-81A7-6F3EEDECDAC9.html

This section details the OUTTGL register, its purpose, and how to use it to toggle I/O pin states.

```APIDOC
## POST /registers/OUTTGL

### Description
This endpoint allows toggling the drive level of one or more output I/O pins without performing a read-modify-write operation. Changes to this register are also reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET), and Data Output Value Clear (OUTCLR) registers.

### Method
POST

### Endpoint
`/registers/OUTTGL`

### Parameters
#### Query Parameters
- **port_group** (string) - Required - Specifies the port group (e.g., 'PORTA', 'PORTB') to which the OUTTGL register belongs.

#### Request Body
- **OUTTGL** (object) - Required - Contains the bitmask for toggling output values.
  - **bits** (integer) - Required - A 32-bit integer where each bit corresponds to an I/O pin. Writing '1' to a bit toggles the corresponding bit in the OUT register.

### Request Example
```json
{
  "port_group": "PORTA",
  "OUTTGL": {
    "bits": 1024 
  }
}
```

### Response
#### Success Response (200)
- **status** (string) - Indicates the success of the operation (e.g., 'success').
- **message** (string) - A confirmation message.

#### Response Example
```json
{
  "status": "success",
  "message": "OUTTGL register updated successfully."
}
```

### Error Handling
- **400 Bad Request**: If the request body is invalid or missing required fields.
- **404 Not Found**: If the specified port group does not exist.
- **500 Internal Server Error**: If there is a server-side issue.
```
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