Jetson Sensor Processing Engine (SPE) Developer Guide

https://docs.nvidia.com/jetson/archives/r35.6.0/spe
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The Jetson Sensor Processing Engine (SPE) is a built-in Cortex-R5 microcontroller on NVIDIA Jetson...
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### SPI Application Example (C)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/index

This snippet demonstrates the implementation of an SPI application. It is written in C and likely interacts with hardware SPI interfaces on the NVIDIA Jetson platform. Further details on its specific inputs, outputs, and dependencies can be found in the linked documentation.

```c
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <linux/spi/spidev.h>

#define SPI_DEVICE "/dev/spidev0.0"
#define BUFFER_SIZE 64

int main() {
    int fd;
    uint8_t tx_buffer[BUFFER_SIZE];
    uint8_t rx_buffer[BUFFER_SIZE];
    struct spi_ioc_transfer tr;
    int ret;

    // Open SPI device
    fd = open(SPI_DEVICE, O_RDWR);
    if (fd < 0) {
        perror("Error opening SPI device");
        return 1;
    }

    // Initialize transfer structure
    memset(tx_buffer, 0, sizeof(tx_buffer));
    memset(rx_buffer, 0, sizeof(rx_buffer));
    memset(&tr, 0, sizeof(tr));

    tr.tx_buf = (unsigned long)tx_buffer;
    tr.rx_buf = (unsigned long)rx_buffer;
    tr.len = BUFFER_SIZE;
    tr.speed_hz = 1000000; // 1 MHz
    tr.bits_per_word = 8;

    // Example: Send some data
    strcpy((char*)tx_buffer, "Hello SPI!");

    // Perform SPI transfer
    ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
    if (ret < 0) {
        perror("Error performing SPI transfer");
        close(fd);
        return 1;
    }

    printf("Sent: %s\n", tx_buffer);
    printf("Received: %s\n", rx_buffer);

    close(fd);
    return 0;
}

```

--------------------------------

### Enable I2C Application Build Flag (Makefile)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_i2c_app

This example shows how to enable the I2C application by setting a specific flag in a Makefile. This is a common practice in embedded development to conditionally compile features or applications based on build configurations.

```makefile
ENABLE_I2C_APP := 1
```

--------------------------------

### Test IVC Echo Channel Communication (Linux Shell)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_ivc

This example shows how to test the Inter VM Communication (IVC) echo channel from the Linux kernel side. It involves writing a message to the `/sys/devices/platform/aon_echo/data_channel` node and then reading it back to verify the echo functionality.

```shell
ubuntu@jetson:~$ sudo su -c 'echo tegra > /sys/devices/platform/aon_echo/data_channel'
ubuntu@jetson:~$ cat /sys/devices/platform/aon_echo/data_channel
tegra
```

--------------------------------

### Timer Application Example (C)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/index

This C code snippet illustrates a timer application, likely for managing time-based events or scheduling tasks on the NVIDIA Jetson platform. It utilizes standard C libraries for time manipulation. Specific usage, inputs, and outputs depend on the application's context within the Jetson environment.

```c
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>

int main() {
    time_t start_time, current_time;
    double elapsed_time;

    printf("Starting timer...\n");
    start_time = time(NULL);

    // Simulate some work
    sleep(3);

    current_time = time(NULL);
    elapsed_time = difftime(current_time, start_time);

    printf("Timer stopped.\n");
    printf("Elapsed time: %.2f seconds\n", elapsed_time);

    return 0;
}

```

--------------------------------

### Enable SPI Application in Target Specific Makefile (SPE)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

This code demonstrates how to enable the SPI application by setting a flag in the target specific makefile. This is a necessary step before rebuilding the application and copying it to the SPE binary location.

```makefile
ENABLE_SPI_APP := 1
```

--------------------------------

### SPI 2 Pin Mappings for Jetson Orin Nano

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

This section outlines the hardware pin mappings for SPI 2 signals on the Jetson Orin Nano's J2 connector. These pins are essential for establishing the SPI communication.

```text
SPI 2 signals are available at connector J2 with below pin mappings.
  * Pin 126 - CLK
  * Pin 127 - MISO
  * Pin 128 - MOSI
  * Pin 130 - CS0
```

--------------------------------

### Update SPI2 Pinmux Configuration in DTS

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

Modifies the pinmux configuration for SPI2 by changing the 'nvidia,function' from 'rsvd1' to 'spi2' and adjusting tristate and enable-input settings. This ensures proper SPI2 functionality.

```dts
--- a/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+++ b/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
@@ -608,7 +608,7 @@

                                spi2_sck_pcc0 {
                                        nvidia,pins = "spi2_sck_pcc0";
-                                       nvidia,function = "rsvd1";
+                                       nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -618,17 +618,17 @@

                                spi2_miso_pcc1 {
                                        nvidia,pins = "spi2_miso_pcc1";
-                                       nvidia,function = "rsvd1";
+                                       nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                       nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                       nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                        nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                                };

                                spi2_mosi_pcc2 {
                                        nvidia,pins = "spi2_mosi_pcc2";
       -                                nvidia,function = "rsvd1";
+                                       nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -638,7 +638,7 @@

                               spi2_cs0_pcc3 {
                                        nvidia,pins = "spi2_cs0_pcc3";
-                                       nvidia,function = "rsvd1";
+                                       nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;

```

--------------------------------

### Enable IVC Echo Channel in Device Tree (AGX Xavier)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_ivc

This snippet shows how to enable the IVC echo channel in the device tree for AGX Xavier. It involves adding or modifying entries in the `tegra194-aon.dtsi` file to set the 'status' to 'okay'.

```device-tree
+ aon_echo {
+ compatible = "nvidia,tegra186-aon-ivc-echo";
+ mboxes = <&aon 0>;
+ status = "okay";
+ };
```

--------------------------------

### SPI Application Loopback Test (SPE)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

The SPI application demonstrates accessing and manipulating Always On (AON) SPI from the SPE/AON processor. It performs a loopback test by sending predefined bytes and comparing them with received bytes. Success is indicated by printing 'SPI test successful'.

```c
// SPI application code for loopback test
// Sends predefined bytes and compares with received bytes.
// Prints 'SPI test successful' on success.
```

--------------------------------

### Enable IVC Echo Channel in Device Tree (AGX Orin)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_ivc

This snippet demonstrates enabling the IVC echo channel in the device tree for AGX Orin. It requires updating the `tegra234-aon.dtsi` file, specifically changing the 'status' of the 'aon_echo' node from 'disabled' to 'okay'.

```device-tree
aon_echo {
compatible = "nvidia,tegra186-aon-ivc-echo";
mboxes = <&aon 1>;
- status = "disabled";
+ status = "okay";
};
```

--------------------------------

### Modify Firewall Settings for GTE Access (Orin Nano)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gte_app

This code snippet details the modification of firewall settings in a DTS file for Orin Nano to grant SPE read/write access to GTE registers. It updates the value for GTE_GPIO_SCR_TESCR_0 in the firewall configuration, ensuring proper communication between SPE and GTE.

```dts
reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
exclusion-info = <3>;
 value = <0x38001232>;
};
```

--------------------------------

### Modify Firewall Settings for SPI2 Access (DTS)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

This snippet shows modifications to the tegra234-mb2-bct-scr-p3701-0000-override.dts file to adjust firewall settings. The goal is to allow the SPE (Security and Performance Extension) to read and write to the SPI2 register. This is crucial for enabling communication between the SPE and the SPI2 peripheral.

```dts
+++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
@@ -24,6 +24,11 @@

```

--------------------------------

### Modify Firewall Settings for GTE Access (AGX Orin)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gte_app

This code snippet illustrates modifying firewall settings in a DTS file for AGX Orin to allow SPE to read/write to GTE registers. It adds a new 'reg' entry to the firewall configuration, specifically for GTE_GPIO_SCR_TESCR_0, enabling necessary access.

```dts
reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
 exclusion-info = <2>;
 value = <0x38001232>;
 };
```

--------------------------------

### Enable GPIO App and SPE for Orin Nano in Makefile

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This snippet shows how to enable the GPIO application and the SPE for Orin Nano by setting specific flags in the `target_specific.mk` file. After modification, the application needs to be rebuilt, and the output binary copied to the bootloader directory.

```makefile
ENABLE_GPIO_APP := 1
ENABLE_SPE_FOR_ORIN_NANO := 1
```

--------------------------------

### Enable GPIO Application in Makefile

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This snippet shows how to enable GPIO application access by setting a flag in the `target_specific.mk` file. This is a prerequisite for accessing GPIOs from the SPE.

```makefile
ENABLE_GPIO_APP := 1
```

--------------------------------

### Update GPIO Configuration in DTS

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

Adjusts the GPIO configuration by removing specific TEGRA234_AON_GPIO entries from 'gpio-output-low' and 'gpio-output-high' lists. This modifies the default state of certain GPIO pins.

```dts
   --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
   +++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
   @@ -91,13 +91,9 @@
                                   TEGRA234_AON_GPIO(EE, 4)
                                   >;
                           gpio-output-low = <
-                               TEGRA234_AON_GPIO(CC, 0)
-                               TEGRA234_AON_GPIO(CC, 2)
-                               TEGRA234_AON_GPIO(CC, 3)
                                   TEGRA234_AON_GPIO(AA, 4)
                                   >;
                           gpio-output-high = <
-                               TEGRA234_AON_GPIO(CC, 1)
                                   TEGRA234_AON_GPIO(AA, 5)
                                   TEGRA234_AON_GPIO(BB, 3)
                                   >;

```

--------------------------------

### Expected Output Logs for GPIO Application

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This snippet shows the expected terminal output after successfully configuring and running the GPIO application. It indicates that the GPIO output is set and an interrupt is triggered and handled, demonstrating the correct functioning of the GPIO interrupt mechanism.

```text
gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0
```

--------------------------------

### Successful I2C Test Message (Plain Text)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_i2c_app

This is a simple success message printed by an I2C application after it successfully retrieves a sensor ID. It indicates that the communication with the I2C device was established and the expected data was read.

```text
I2C test successful

```

--------------------------------

### Enable DMIC5 Clock State on Jetson

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_aodmic_app

This command enables the DMIC5 clock state on the NVIDIA Jetson platform. It requires root privileges and directly manipulates a debugfs file.

```bash
sudo su -c 'echo 1 > /sys/kernel/debug/bpmp/debug/clk/dmic5/state'
```

--------------------------------

### Modify SPI2 Firewall Settings in DTS

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

Updates the firewall settings in the SCR DTS file to allow the SPE to read and write to the SPI2 register. This is achieved by adding a new 'reg' entry with specific exclusion information and value.

```dts
     +++ b/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts
     @@ -810,6 +810,10 @@
                           exclusion-info = <0>;
                           value = <0x00000000>;
                           };
+                     reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
+                     exclusion-info = <3>;
+                     value = <0x30001410>;
+                     };
                           reg@2228 { /* CLK_RST_CONTROLLER_ERR_COLLATOR_FSI_SCR_EC_SCR_0 */
                           exclusion-info = <0>;

```

--------------------------------

### Update GPIO Configuration (DTS)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This snippet illustrates modifications to the GPIO configuration within a Device Tree Source Include (DTSI) file. It reorders the inclusion of GPIO BB0 and adds GPIO BB1 to the `gpio-output-low` list.

```dts
--- a/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+++ b/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
@@ -118,12 +118,12 @@
                                TEGRA234_AON_GPIO(AA, 2)
                                TEGRA234_AON_GPIO(AA, 3)
                                TEGRA234_AON_GPIO(BB, 0)
-                               TEGRA234_AON_GPIO(BB, 1)
                                TEGRA234_AON_GPIO(BB, 3)
                                >;
                          gpio-output-low = <
                                TEGRA234_AON_GPIO(CC, 2)
                                TEGRA234_AON_GPIO(CC, 3)
+                               TEGRA234_AON_GPIO(BB, 1)
                                >;
                          gpio-output-high = <
                                >;
```

--------------------------------

### Disable SPI Driver in Linux Kernel Device Tree (SPE)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

This snippet shows how to disable the SPI driver in the Linux kernel device tree for the Jetson SPE. It ensures no other processors are using the driver. The configuration is found in the tegra194-camera-e3377-a00.dtsi file.

```c
spi@c260000 {
status = "disabled";
spi-max-frequency = <12000000>;
...
}
```

--------------------------------

### Update GPIO Configuration for Orin Nano

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This snippet illustrates changes to the GPIO configuration DTS file (`tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi`). It shows the addition of TEGRA234_AON_GPIO(DD, 2) to the `gpio-input` list and TEGRA234_AON_GPIO(DD, 1) to the `gpio-output-low` list, configuring specific GPIO pins for input and output.

```diff
--- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
@@ -89,8 +89,10 @@
 gpio-input = <
 TEGRA234_AON_GPIO(EE, 2)
 TEGRA234_AON_GPIO(EE, 4)
+ TEGRA234_AON_GPIO(DD, 2)
 >;
 gpio-output-low = <
+ TEGRA234_AON_GPIO(DD, 1)
 TEGRA234_AON_GPIO(CC, 0)


```

--------------------------------

### Recreate Device Tree Blob (DTB) from DTS

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_aodmic_app

This command uses the Device Tree Compiler (dtc) to compile a patched Device Tree Source (DTS) file back into a Device Tree Blob (DTB) file. This DTB can then be flashed to the target device.

```bash
dtc -I dts -O dtb <temp_file.dts> -o <BPMP DT file>
```

--------------------------------

### Update Pinmux Configuration for Orin Nano

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_gpio

This section details the necessary modifications in the pinmux configuration DTS file (`tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi`). It shows changes for `gen8_i2c_scl_pdd1` and `gen8_i2c_sda_pdd2`, reassigning their functions to `rsvd1` and adjusting pull and tristate settings, which impacts I2C functionality and pin availability.

```diff
--- a/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+++ b/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
@@ -134,19 +134,18 @@

 gen8_i2c_scl_pdd1 {
 nvidia,pins = "gen8_i2c_scl_pdd1";
- nvidia,function = "i2c8";
+ nvidia,function = "rsvd1";
 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 nvidia,lpdr = <TEGRA_PIN_DISABLE>;
 };

 gen8_i2c_sda_pdd2 {
 nvidia,pins = "gen8_i2c_sda_pdd2";
- nvidia,function = "i2c8";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 nvidia,lpdr = <TEGRA_PIN_DISABLE>;


```

--------------------------------

### Enable AODMIC Application

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_aodmic_app

Enables the AODMIC application by setting a build flag in the target-specific makefile. After modification, the application needs to be rebuilt, and the output binary copied to the specified bootloader path.

```makefile
ENABLE_AODMIC_APP := 1
```

--------------------------------

### Update GPIO Configuration (DTS)

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_spi_app

This snippet demonstrates how to update the GPIO configuration by modifying the tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi file. It removes specific GPIO pins (TEGRA234_AON_GPIO(CC, 0) through TEGRA234_AON_GPIO(CC, 3)) from the configuration. This change affects the availability or configuration of these GPIO pins.

```dts
--- a/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+++ b/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
@@ -125,10 +125,6 @@
                                TEGRA234_AON_GPIO(EE, 6)
                                TEGRA234_AON_GPIO(EE, 2)
                                TEGRA234_AON_GPIO(EE, 4)
-                               TEGRA234_AON_GPIO(CC, 0)
-                               TEGRA234_AON_GPIO(CC, 1)
-                               TEGRA234_AON_GPIO(CC, 2)
-                               TEGRA234_AON_GPIO(CC, 3)
                                TEGRA234_AON_GPIO(AA, 0)


```

--------------------------------

### Reconstruct Device Tree Source (DTS) from DTB

Source: https://docs.nvidia.com/jetson/archives/r35.6.0/spe/md__home_jenkins_workspace_Utilities_rt_aux_cpu_demo_fsp_docs_work_rt_aux_cpu_demo_fsp_doc_aodmic_app

This command uses the Device Tree Compiler (dtc) to decompile a Device Tree Blob (DTB) file into a human-readable Device Tree Source (DTS) file. This is a necessary step before patching the device tree.

```bash
dtc -I dtb -O dts <BPMP DT file> -o <temp_file.dts>
```
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