JITX Documentation

https://docs.jitx.com
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### Common Example Board

Source: https://docs.jitx.com/reference/jsl/pin-assignment

An example board configuration file for common functionalities. This snippet likely contains code related to general board setup or common components.

```html
<a href="examples/protocols/common/example-board.html">example-board</a>
```

--------------------------------

### Example pcb-component with Datasheet

Source: https://docs.jitx.com/reference/statements/cstmt/datasheet

An example demonstrating the 'datasheet' statement within a 'pcb-component' definition, linking to a specific component's datasheet URL.

```JITX
pcb-component oscillator:
  datasheet = "https://www.analog.com/media/en/technical-documentation/data-sheets/6906fc.pdf"
```

--------------------------------

### JITX Description Statement Examples

Source: https://docs.jitx.com/reference/statements/boardstmt/description

Illustrates how to use the 'description' statement in JITX. The first example shows a static string description for a PCB component. The second example demonstrates using string formatting with variables to create dynamic descriptions for a parameterized PCB module.

```JITX
; We can use string literals to describe a particular component.
pc b-component analog-devices-ADM7150 :
  description = "800 mA Ultralow Noise, High PSRR, RF Linear Regulator"

; We can use string formatting to construct descriptions based on variables
;   or arguments to a JITX Definition
pc b-module band-pass-filter (high-cut:Double, low-cut:Double) :
  description = to-string(
    "Band-pass Filter - Highpass = %_ Hz and Lowpass = %_ Hz." % [high-cut, low-cut]
    )
```

--------------------------------

### JITX Description Statement Examples

Source: https://docs.jitx.com/reference/statements/symstmt/description

Illustrates how to use the 'description' statement in JITX. The first example shows a static string description for a PCB component. The second example demonstrates using string formatting with variables to create dynamic descriptions for a parameterized PCB module.

```JITX
; We can use string literals to describe a particular component.
pc b-component analog-devices-ADM7150 :
  description = "800 mA Ultralow Noise, High PSRR, RF Linear Regulator"

; We can use string formatting to construct descriptions based on variables
;   or arguments to a JITX Definition
pc b-module band-pass-filter (high-cut:Double, low-cut:Double) :
  description = to-string(
    "Band-pass Filter - Highpass = %_ Hz and Lowpass = %_ Hz." % [high-cut, low-cut]
    )
```

--------------------------------

### JITX Description Statement Examples

Source: https://docs.jitx.com/reference/statements/materialstmt/description

Illustrates how to use the 'description' statement in JITX. The first example shows a static string description for a PCB component. The second example demonstrates using string formatting with variables to create dynamic descriptions for a parameterized PCB module.

```JITX
; We can use string literals to describe a particular component.
pc b-component analog-devices-ADM7150 :
  description = "800 mA Ultralow Noise, High PSRR, RF Linear Regulator"

; We can use string formatting to construct descriptions based on variables
;   or arguments to a JITX Definition
pc b-module band-pass-filter (high-cut:Double, low-cut:Double) :
  description = to-string(
    "Band-pass Filter - Highpass = %_ Hz and Lowpass = %_ Hz." % [high-cut, low-cut]
    )
```

--------------------------------

### Install VSCode on Ubuntu

Source: https://docs.jitx.com/installationinstructions

Command to install Visual Studio Code on Ubuntu systems. VSCode is a prerequisite for the JITX extension.

```bash
sudo apt-get install code
```

--------------------------------

### JITX Project Setup and File Management

Source: https://docs.jitx.com/cad-integration/kicad-importer

Illustrates the initial setup of a JITX project and the subsequent file organization required for importing a KiCad design. This includes creating a new project directory and managing subdirectories and project files.

```jitx
# Create a new JITX project directory
# Use the 'New project' command in the JITX sidebar of the VSCode extension
# Select the newly created (and empty) directory as the folder in which to create the project.

# Example project structure after cloning and setup:
kicad-tutorial
 \ usb-sniffer/
 \ open-components-database/
 | stanza.proj

# Delete unnecessary files for the imported project:
# rm kicad-tutorial/main.stanza
# rm kicad-tutorial/helpers.stanza
```

--------------------------------

### JITX Description Statement Examples

Source: https://docs.jitx.com/reference/statements/lpstmt/description

Illustrates how to use the 'description' statement in JITX. The first example shows a static string description for a PCB component. The second example demonstrates using string formatting with variables to create dynamic descriptions for a parameterized PCB module.

```JITX
; We can use string literals to describe a particular component.
pc b-component analog-devices-ADM7150 :
  description = "800 mA Ultralow Noise, High PSRR, RF Linear Regulator"

; We can use string formatting to construct descriptions based on variables
;   or arguments to a JITX Definition
pc b-module band-pass-filter (high-cut:Double, low-cut:Double) :
  description = to-string(
    "Band-pass Filter - Highpass = %_ Hz and Lowpass = %_ Hz." % [high-cut, low-cut]
    )
```

--------------------------------

### DisplayPort Source Example

Source: https://docs.jitx.com/reference/jsl/pin-assignment

Provides an example source file for the DisplayPort protocol. This snippet likely contains code related to the implementation or configuration of DisplayPort functionality.

```html
<a href="examples/protocols/displayport/displayport-src.html">displayport-src</a>
```

--------------------------------

### SATA Source Example

Source: https://docs.jitx.com/reference/jsl/pin-assignment

Provides an example source file for the SATA protocol. This snippet likely contains code related to the implementation or configuration of SATA functionality.

```html
<a href="examples/protocols/sata/SATA-src.html">SATA-src</a>
```

--------------------------------

### JITX Description Statement Examples

Source: https://docs.jitx.com/reference/statements/mstmt/description

Illustrates how to use the 'description' statement in JITX. Examples show using simple string literals for component descriptions and formatted strings to dynamically generate descriptions based on module parameters.

```JITX
; We can use string literals to describe a particular component.
pc b-component analog-devices-ADM7150 :
  description = "800 mA Ultralow Noise, High PSRR, RF Linear Regulator"
```

```JITX
; We can use string formatting to construct descriptions based on variables
;   or arguments to a JITX Definition
pc b-module band-pass-filter (high-cut:Double, low-cut:Double) :
  description = to-string(
    "Band-pass Filter - Highpass = %_ Hz and Lowpass = %_ Hz." % [high-cut, low-cut]
    )
```

--------------------------------

### JITX Text Usage Example

Source: https://docs.jitx.com/reference/statements/gstmt/text

Demonstrates how to instantiate the `Text` function to place a string on the silkscreen. The example shows specifying the text content, size, anchor point (e.g., 'C' for center), and location.

```JITX
Text("Sample", 2.0, C, loc(1.0, 1.0))
```

--------------------------------

### JITX Net Naming Example

Source: https://docs.jitx.com/getting-started/quickstart-organize-a-schematic

Demonstrates how to add names to net statements in JITX code to improve clarity and organization in generated schematics. The example shows an original net declaration and its enhanced version with a specific name, facilitating better schematic readability.

```JITX
net (ctl.USB usb-if.USB)
```

```JITX
net USB-DATA (ctl.USB usb-if.USB)
```

--------------------------------

### Instantiate EEPROM Component

Source: https://docs.jitx.com/getting-started/quickstart-components-nets

Demonstrates how to instantiate an EEPROM component within the controller module and connect its power and configuration nets.

```JITX DSL
inst EEPROM : components/MC-93LC46CT/module
net (EEPROM.VDD-3v3 rail-3v3)
net (EEPROM.cfg debug-if.CFG)
```

--------------------------------

### Get Pads by Column

Source: https://docs.jitx.com/reference/jsl/landpatterns/VirtualLP

Retrieves all pads located within a specified column index in the Virtual Landpattern. Pads are indexed starting from 0.

```APIDOC
get-pads-by-column(vp:VirtualLP, column:Int) -> Seq<VirtualPad>
  - Retrieves pads from a specific column.
  - Parameters:
    - vp: VirtualLP - The VirtualLP SceneGraph.
    - column: Int - The index of the column to retrieve pads from (must be >= 0).
  - Returns: Seq<VirtualPad> - A sequence of VirtualPad objects. Returns an empty sequence if the column does not exist.
```

--------------------------------

### JITX Pad and Component Placement

Source: https://docs.jitx.com/reference/statements/gstmt/loc

Demonstrates defining pads with specific geometries and placing them at calculated poses. It also shows how to instantiate components and place them using the 'place' command with a defined pose.

```jitx-dsl
pad p[0] : smd-pad(2.0, 1.0) at loc(0.0, 0.0, 90.0) * loc(2.0, 3.0)
  // Defines a pad 'p[0]' with smd-pad geometry (2.0, 1.0)
  // and places it at the pose resulting from the composition:
  // loc(0.0, 0.0, 90.0) * loc(2.0, 3.0)

pad p[1] : smd-pad(5.0, 1.0) at loc(2.0, 3.0) * loc(0.0, 0.0, 90.0)
  // Defines a pad 'p[1]' with smd-pad geometry (5.0, 1.0)
  // and places it at the pose resulting from the composition:
  // loc(2.0, 3.0) * loc(0.0, 0.0, 90.0)

inst c : my-component
  // Instantiates a component named 'c' of type 'my-component'

place(c) at loc(2.0, 3.0) on Top
  // Places the instance 'c' at the pose (x,y) = (2.0mm, 3.0mm) on the 'Top' side.
```

--------------------------------

### JITX Design Setup and Execution Commands

Source: https://docs.jitx.com/code-md/multi-ch_pa

This snippet details the JITX commands for setting up a design, including defining rules, vendors, board parameters, and export backends. It also shows how to set the schematic paper size, specify the main module, and initiate visualization of the generated board, schematic, and BOM.

```jitx
public defn setup-design (name:String, board:Board
                          --
                          rules:Rules = ocdb/utils/defaults/default-rules
                          vendors:Tuple<String|AuthorizedVendor> = ocdb/utils/design-vars/APPROVED-DISTRIBUTOR-LIST
                          quantity:Int = ocdb/utils/design-vars/DESIGN-QUANTITY
                          bom-columns:Tuple<BOMColumn> = ocdb/utils/design-vars/BOM-COLUMNS) :
  set-current-design(name)
  set-board(board)
  set-rules(rules)
  set-bom-vendors(vendors)
  set-bom-design-quantity(quantity)
  set-bom-columns(bom-columns)
  set-paper(ISO-A4)
  set-export-backend(`altium) ; set the CAD software for export to be altium (also supported: `kicad)

setup-design(
  "jitx-design",
  ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape)
)

; Set the schematic sheet size
set-paper(ANSI-A)

; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(my-design)

; Use any helper function from helpers.stanza here
; run-check-on-design(my-design)

; View the results
view-board()
view-schematic()
view-design-explorer()
view-bom(BOM-STD)
```

--------------------------------

### Via Tented Function

Source: https://docs.jitx.com/reference/jitx/commands

Gets the tented sides of a pcb-via definition. It returns a Side, True, or False, indicating which sides are tented or if the attribute is not specified. Includes a syntax example.

```APIDOC
public defn via-tented (obj:JITXDef) -> Side|True|False
```

```JITX
pcb-via th-via :
  type = MechanicalDrill
  start = LayerIndex(0, Top)
  stop = LayerIndex(0, Bottom)
  diameter = 0.6
  hole-diameter = 0.3

println(via-tented(th-via))
```

--------------------------------

### Get Merged Physical Design Module

Source: https://docs.jitx.com/reference/jitx/commands

Obtains the physical-design-transformed 'main' module of the current design. Returns an Instantiable object representing the merged module. Includes a syntax example.

```APIDOC
public defn get-merged-physical-design-module () -> Instantiable
```

```JITX
val new-module = get-merged-physical-design-module()
```

--------------------------------

### JITX Project Structure

Source: https://docs.jitx.com/getting-started/quickstart-your-first-jitx-design

Illustrates the standard directory layout for a new JITX project, including design files, helper modules, configuration files, and project definitions.

```text
ethernet_io/
├── designs/jitx-design/
│   ├── design-info/
│   └── kicad/
├── helpers.stanza
├── main.stanza
├── slm.toml
└── stanza.proj
```

--------------------------------

### Get Default Diode Symbol Params (JITX)

Source: https://docs.jitx.com/reference/jsl/symbols/diodes

Retrieves the default parameters for generic diode symbols. This function is useful for obtaining a base configuration that can be used as a starting point for creating or modifying diode symbol definitions.

```JITX
public defn get-default-diode-symbol-params () -> DiodeSymbolParams
```

--------------------------------

### Main Module Integration (After)

Source: https://docs.jitx.com/getting-started/quickstart-power-layout

Updated setup for the main communications-core pcb-module, including the instantiation of a power-management module and wiring its power rails to the controller and system ports.

```Stanza
#use-added-syntax(jitx)

defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

  import ethernet-io/power
  import ethernet-io/controller

val board-shape = RoundedRectangle(100.0, 70.0, 3.0)

pc b-module communications-core :
  port rail-3v3 : power

  inst pwr-mng : power-management
  inst ctl : controller

  ; Example: wire your controller to the power rails
  net (pwr-mng.VDD-3v3 rail-3v3 ctl.rail-3v3)
  net (pwr-mng.VDD-USB ctl.VDD-USB)
  net (pwr-mng.VDD-1v2 ctl.VDD-1v2)
```

--------------------------------

### JITX Instance Placement Example

Source: https://docs.jitx.com/reference/statements/gstmt/loc

Demonstrates the basic syntax for placing an instance named 'c' of type 'my-component' at a specific location on the board. It shows how to use the 'place' command and the 'loc' function.

```JITX
inst c : my-component
place(c) at loc(2.0, 3.0) on Top
```

--------------------------------

### Apply Backdrill to PCB Via

Source: https://docs.jitx.com/reference/statements/viastmt/backdrill

Illustrates how to integrate a Backdrill definition into a PCB via object. This example shows setting the start and stop layers for the via and assigning a combined top and bottom backdrill configuration.

```JITX
pcb-via drill-both:
  start = LayerIndex(2, Top)
  stop = LayerIndex(2, Bottom)
  backdrill = Backdrill(top = big-drill, bottom = small-drill)
  ; ...other via properties
```

--------------------------------

### Conceptual RBE Navigation Instructions

Source: https://docs.jitx.com/essentials/physical_design/autorouter

Illustrates the sequence of movements and turns around obstacles that define a Rubber Band Equivalent (RBE) path. This conceptual example shows how an RBE can be described as a series of navigation instructions from a starting point to an endpoint, specifying turns around intermediate obstacles.

```conceptual
1. Start at (10,20)
2. Go straight to the obstacle at (20,20) and turn right (CW) around it.
3. Go straight to the obstacle at (20,0) and turn left (CCW) around it.
4. Go straight and finish at (30,0).
```

--------------------------------

### JITX Simple Board Setup Function

Source: https://docs.jitx.com/reference/jsl/examples/protocols/common/example-board

A function to set up a PCB board for a design. It creates a board with a defined shape, stackup, and design rules.

```JITX
public defn setup-board ()

```

--------------------------------

### Backdrill Depth Calculation Example

Source: https://docs.jitx.com/reference/statements/viastmt/backdrill

Explains the drill depth calculation for a backdrill based on the via's start and stop layers. It details how layers not part of the via on the backdrill's side are drilled out, illustrating the concept with a via spanning from Top to LayerIndex(2, Bottom).

```PCB DSL
public pcb-via example-via :
  start = LayerIndex(0, Top)
  stop = LayerIndex(2, Bottom)
  backdrill = Backdrill(bottom = small-drill)
  ; ...other via properties

; In this example - the backdrill will drill out all layers until it reaches the
; via at LayerIndex(2, Bottom). The drill depth is computed from the sum of the
; copper and dielectric layers from the Bottom layer to 3rd copper layer
; (zero-indexed value) from the bottom. The 3rd copper layer from the bottom is the
; layer that will conduct signal for this via. The 1st and 2nd copper layers from the
; bottom will be drilled out and not able to conduct or form a stub.

; LayerIndex(0, Top)     <-  Via start
; ...                    <-  Barrel of via
; LayerIndex(2, Bottom)  <-  Via stop
; LayerIndex(1, Bottom)  <-  Drilled
; LayerIndex(0, Bottom)  <-  Drilled

```

--------------------------------

### JITX Property Get and Set Operations

Source: https://docs.jitx.com/reference/statements/cstmt/properties

Defines the syntax for retrieving and assigning properties using the `property` and `property?` statements. It covers accessing properties via dot-path notation, handling missing properties with default values or `Maybe` types, checking for property existence with `has-property?`, and setting properties with `JITXValue` types. Includes an example of setting a property on a component's port.

```APIDOC
; Get Form
val v1:JITXValue = property(dot-path)
val v2:Maybe<JITXValue> = property?(dot-path)
val v3:JITXValue = property?(dot-path, def-value)

val v4:True|False = has-property?(dot-path)

; Set Form
property(dot-path) = 3.0

; Example Usage:
pcb-component props-test:
  port gnd : pin
  property(self.gnd.voltage) = 0.0

; Explanation:
The 'Get' form inspects properties. 'property?' returns a Maybe or a default value, avoiding exceptions for missing properties. 'has-property?' checks existence. The 'Set' form creates or overrides properties. The 'dot-path' argument specifies the property location, often starting with an instance name (like 'self') and ending with the property identifier. Values assigned must be of type JITXValue. Custom types require pcb-struct definitions.
```

--------------------------------

### Main Module Integration (Before)

Source: https://docs.jitx.com/getting-started/quickstart-power-layout

Initial setup for the main communications-core pcb-module, defining board shape and importing necessary libraries and modules. This version does not include power management instantiation.

```Stanza
#use-added-syntax(jitx)

defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

  import ethernet-io/controller

val board-shape = RoundedRectangle(100.0, 70.0, 3.0)

pc b-module communications-core :
  port rail-3v3 : power

  inst ctl : controller
```

--------------------------------

### Instantiate Connector Component in Stanza

Source: https://docs.jitx.com/getting-started/quickstart-components-nets

Provides an example of instantiating a component from an external library, specifically a USB Type-C High-Speed interface from the 'connectors' library.

```stanza
inst usb-if : connectors/components/USB/USBTypeC/USBC-HighSpeed-Iface()
```

--------------------------------

### JITX Instance Declaration Syntax Examples

Source: https://docs.jitx.com/reference/statements/mstmt/inst

Illustrates various ways to declare instances in JITX, including basic component instantiation, array instantiation, instantiation within loops, and module instantiation.

```JITX
pcb-module my-module:
  inst my-inst : my-component
  inst my-inst-array : my-component[10]

  for i in 0 to 10 do :
    inst r : chip-resistor(1.0e3)

  inst my-module-inst : my-other-module
```

--------------------------------

### Install JITX Libraries (TOML)

Source: https://docs.jitx.com/getting-started/quickstart-power-layout

Specifies how to add external libraries, such as TI-vreg and power-systems, to your project's configuration file (`slm.toml`) for use in JITX.

```toml
TI-vreg = { git = "JITx-Inc/TI-VREG", version = "0.4.0" }
power-systems = { git = "JITx-Inc/power-systems", version = "0.5.0" }
```

--------------------------------

### InstantiableType Get Function

Source: https://docs.jitx.com/reference/jitx

Provides a 'get' function for the InstantiableType data structure, allowing retrieval based on a length parameter.

```APIDOC
InstantiableType:
  Type definition supporting retrieval operations.
  Functions:
    get (c:InstantiableType, len:Int) -> InstantiableType
```

--------------------------------

### Command-Based Via Fanout

Source: https://docs.jitx.com/getting-started/quickstart-layout

Explains how to create vias programmatically using the command line. This method allows specifying offsets and angles for fanout connections.

```JITX
auto-via 180 0.1
```

--------------------------------

### JITX Core Setup and Module Definitions

Source: https://docs.jitx.com/code-md/multi-ch_pa

This snippet defines the core JITX environment, including imports and basic PCB module definitions for a single RC low-pass filter and a pass-through bundle. It demonstrates component instantiation (resistor, capacitor) and netlist creation within a module.

```jitx
#use-added-syntax(jitx)
defpackage main :
  import core
  import math
  import jitx
  import jitx/commands
  import ocdb/utils/generic-components

; Define the shape/size of the board
val board-shape = RoundedRectangle(30.0, 18.5, 0.25)

doc: <DOC>
RC Low Pass Filter

This is a very crude implementation. This is really
only intended to demonstrate the concept of modules
with multiple components being used as a channel
in pin assignment.

@param freq Corner Frequency for the RC Filter. Must be greater than zero.
@param R-val Resistance value to use by default in the RC filter.
<DOC>
pcbd-module low-pass (freq:Double, R-val:Double = 10.0e3) :

  port vin : pin
  port vout : pin
  port gnd : pin

  val C-val =   1.0 / ( 2.0 * PI * R-val * freq)
  val C-val* = closest-std-val(C-val, 10.0)

  inst R : chip-resistor(R-val)
  inst C : ceramic-cap(C-val*)

  net (vin, R.p[1])
  net (R.p[2], C.p[1], vout)
  net (C.p[2], gnd)

doc: <DOC>
Pass Through Connection Bundle
<DOC>
pcbd-bundle pass-through:
  port A : pin
  port B : pin
```

--------------------------------

### Start New Timer

Source: https://docs.jitx.com/reference/jitx/commands

Starts a new timer with a given name and returns the timer's identifier as a String.

```JITX
public defn start-new-timer (name:String) -> String
```

--------------------------------

### JITX API: Component Querying and Creation Example

Source: https://docs.jitx.com/reference/query-api

This snippet demonstrates advanced usage of the JITX API for electronic component selection and instantiation. It covers setting global query defaults, constructing base and specialized query objects (e.g., ResistorQuery, CapacitorQuery), utilizing special value markers like FindMinimum and FindDistinct, creating component instances, and performing searches with specific parameters and output formatting.

```JITX DSL
; These params will be used in all queries without needing to pass a
; query object arg.
set-global-query-defaults!(min-stock = 1, quantity-needed = 10)

; A basic query object to build off of.  Note the usage a special
; value marker, FindMinimum.  Instead of setting the parameter it is
; given with, it sets the ‘sort!’ parameter (aka ‘_sort’ in low-level
; query interface).  This is meant to replace the OPTIMIZE-FOR
; functionality from OCDB.
val general-query = BaseQuery(price = FindMinimum
                              sellers! = [JLCPCB LCSC DigiKey Future
                                          Mouser Arrow Avnet Newark])
; A more specialized, but still basic query object to build off of.
; This includes all parameters from the previous one.
val smd-query = set(general-query, mounting = "smd"
                                   case = valid-smd-pkgs("0402"))

pc b-module main :
  ; Create a ResistorQuery, which allows us to set keys specific to
  ; resistor category.
  val q1 = ResistorQuery(smd-query, resistance = 8000. +/- 500.
                                    rated-power = AtLeast(0.1)
                                    precision = (5 %)
                                    )

  ; Variant with different resistance.
  val q2 = set(q1, resistance = 1.0e3 +/- 500.0)

  ; If the query already has everything, component creation can be
  ; very terse.
  inst r1 : create-resistor(q1)
  ; We can also override any key we want at the last minute.
  inst r2 : create-resistor(q2, resistance = 12000.)
  ; Here we create a resistor directly from a base query and some
  ; explicit resistor keys.
  inst r3 : create-resistor(smd-query, resistance = 100.,
                                       rated-power = 0.25)
  ; Caution: here we do not use a query object, so the only keys
  ; respected are the global defaults and the ones explicitly given.
  ; This may well return a through-hole resistor from a seller not on
  ; our list.
  inst r4 : create-resistor(resistance = 100.)

  net (r1.p[2] r2.p[1])
  net (r2.p[2] r3.p[1])
  net (r3.p[2] r4.p[1])

  val cap-query = CapacitorQuery(smd-query, type = "electrolytic")
  insert-capacitor(r1.p[1], r4.p[2], cap-query, capacitance = 1.e-6)

; Here we show use of the special value marker FindDistinct, which
; maps to ‘_distinct’ in the low-level dbquery interface.  This will
; give us all the possible values of rated-power for 1000Ω resistors
; with our basic smd-query parameters.

println("searching for possible values of rated-power...")
println(search-resistors(smd-query, rated-power = FindDistinct,
                                    resistance = 1000.))
; prints output:
; [0.0625 0.063 0.1 0.125 0.25 0.2 0.5 0.333333 0.75 0.333 0.6]

; We can also just do a raw search.  This will return the JSON from
; the lower-level dbquery call directly.  In this case the ‘limit’
; keyword is helpful.
println("Searching for 1MΩ resistors...")
println(search-resistors(smd-query, resistance = 1.e6, limit = 1))
; prints output:
;  a boatload of json which I will not copy here

```

--------------------------------

### InstantiableType Get Function

Source: https://docs.jitx.com/reference/jitx

Details the 'get' function associated with the InstantiableType. This function is used to retrieve or access information related to instantiable types.

```APIDOC
InstantiableType:
  Functions:
    get: Retrieves instantiable type information
```

--------------------------------

### JITX Stanza Quick Reference

Source: https://docs.jitx.com/getting-started/quickstart-organize-a-schematic

A quick reference guide for JITX Stanza, the declarative language used for defining electronic designs. Covers syntax and common statements.

```APIDOC
Stanza Quick Reference:
  Provides a concise overview of JITX Stanza syntax and keywords.
  Covers fundamental statements for defining components, nets, and board layouts.
  (Detailed syntax and examples are available in the JITX Manual and specific statement documentation.)
```

--------------------------------

### Basic Option Statement Example

Source: https://docs.jitx.com/reference/statements/common/supports

Demonstrates the fundamental use of the 'option' statement within a 'supports' declaration. This allows a single pending port to map to one of several physical ports, creating an OR-like selection.

```jitx
pcb-bundle gpio:
  port p

pc b-component mcu:
  port PA : pin[16]

  supports gpio :
    option :
      gpio.p => self.PA[1]
    option :
      gpio.p => self.PA[4]
```

--------------------------------

### PortType Get Function

Source: https://docs.jitx.com/reference/jitx

Details the 'get' function associated with the PortType. This function likely retrieves or accesses port-related information. It has additional overloads indicated by (+ 2).

```APIDOC
PortType:
  Functions:
    get (+ 2): Retrieves port information
```

--------------------------------

### JITX Stanza Quick Reference

Source: https://docs.jitx.com/code-md/stubs_example

A concise reference for the Stanza language used in JITX, covering syntax and common constructs for hardware description.

```APIDOC
Stanza Quick Reference: syntax_elements
  - Keywords: list_of_keywords
  - Data Types: list_of_types
  - Operators: list_of_operators
```

--------------------------------

### JITX Ref Prefix Check Example

Source: https://docs.jitx.com/reference/jitx/ref

Demonstrates the `prefix?` function in JITX, which checks if one Ref is a prefix of another, providing examples for both true and false cases.

```JITX
pcb-component cpu :
  port p[50]

; returns true
prefix?(#R(cpu.p[5]), #R(cpu.p))

; returns false
prefix?(#R(cpu.p[5]), #R(p[5]))

```

--------------------------------

### PortType Get Functions

Source: https://docs.jitx.com/reference/jitx

Provides overloaded 'get' functions for the PortType data structure. These functions allow retrieving parts of a PortType based on indices, ranges, or lengths.

```APIDOC
PortType:
  Type definition supporting retrieval operations.
  Functions:
    get (c:PortType, elems:Tuple<Int|Range>) -> PortType
    get (c:PortType, elems:Range) -> PortType
    get (c:PortType, length:Int) -> PortType
```

--------------------------------

### Example Usage of emodel?

Source: https://docs.jitx.com/reference/statements/cstmt/emodel

Demonstrates how to use the `emodel?` function with a resistor instance and print the resulting electrical model. The output shows the structure of the retrieved model.

```Julia
val r1 = res-strap(power-5v, signal, 10.0e3)
val m = emodel?(r1)
println("Model: %_" % [m])

; Prints:
; Model: Resistor(10000.0, 0.05, 0.063)
```

--------------------------------

### Microvia - Bottom Side

Source: https://docs.jitx.com/reference/statements/viastmt/index

Defines a microvia on the bottom side of the board, connecting layers starting from the bottom. The LayerIndex is reversed when starting from the bottom of the board.

```JITX
public pcb-via bot-uvia :
  name = "Bot-0-1-uvia"
  start = LayerIndex(1, Bottom)
  stop = LayerIndex(0, Bottom)
  diameter = 0.15
  hole-diameter = 0.1
  type = LaserDrill
  tented = Bottom

```

--------------------------------

### JITX Example: Component Placement in Module

Source: https://docs.jitx.com/reference/jitx/pose

Illustrates placing component instances within a PCB module using the `loc` function to define their position and side.

```JITX DSL
pcb-module example-mod :
  description = "Simple Module Demonstrating Placement"
  inst R1 : res-strap(10.0e3)
  place(R1) at loc(0.5, 0.5) on Top
```

--------------------------------

### JITX Module Hierarchy and Placement Example

Source: https://docs.jitx.com/essentials/physical_design/kinematic-tree

Demonstrates how to define and instantiate PCB modules, place components within them, and establish hierarchical relationships. It shows the use of 'inst', 'place', 'at loc', and 'on' keywords to define component placement and module instantiation.

```jitx-dsl
pcb-module module-a () :
  inst r1 : chip-resistor(50.0)
  place(r1) at loc(0.0, -2.0) on Top

  inst r2 : chip-resistor(100.0)
  place(r2) at loc(0.0, 2.0) on Top

  inst r3 : chip-resistor(200.0)

pc b-module module-b () :
  inst r4 : chip-resistor(500.0)
  place(r4) at loc(-2.0, 0.0) on Top

  inst r5 : chip-resistor(750.0)
  place(r5) at loc(2.0, 0.0) on Top

pc b-module module-c () :
  inst m1 : module-a()
  place(m1) at loc(0.0, 0.0) on Top

  inst m2 : module-b()

  inst r6 : chip-resistor(1000.0)
  place(r6) at loc(-5.0, 0.0) on Top

pc b-module top-module () :
  inst m3 : module-c()

```

--------------------------------

### 10GBASE-KR Ethernet Source Example

Source: https://docs.jitx.com/reference/jsl/pin-assignment

Provides an example source file for the 10GBASE-KR Ethernet standard. This snippet likely contains code related to high-speed Ethernet communication.

```html
<a href="examples/protocols/ethernet/10GBASE-KR/e10GBASE-KR-src.html">e10GBASE-KR-src</a>
```

--------------------------------

### topo-bus Example Usage

Source: https://docs.jitx.com/reference/jsl/si/bus

Demonstrates the usage of the topo-bus function by connecting JITX objects, including ports and instances, through resistors and short traces. It illustrates creating a resistor and defining bus connections for the function.

```JITX
port mii : rmii-bus
require sw-bus : rmii-bus from mcu
val series-R-type = create-resistor(resistance = 51.0, precision = (1 %), case = ["0603"])
val rx-bus = [sw-bus.rxd, sw-bus.crs-dv, sw-bus.ref-clk]
val rx-out = [mii.rxd, mii.crs-dv, mii.ref-clk]
topo-bus(ShortTrace(rx-bus => series-R-type) => rx-out)
```

--------------------------------

### JITX Example: Pad Placement in Land Pattern

Source: https://docs.jitx.com/reference/jitx/pose

Demonstrates how to define PCB pads and place them within a land pattern using the `loc` function with specific coordinates and optional side placement.

```JITX DSL
pcb-pad example-pad :
  name  = "Example Circle Pad"
  type  = SMD
  shape = Circle(1.0)
  layer(SolderMask(Top)) = Circle(1.2)

pc b-landpattern example-lp :
  description = "Land Pattern Demonstrating use of 'loc' for a Pad"

  pad p[1] : example-pad at loc(2.0, 3.0)
  pad p[2] : example-pad at loc(2.0, 3.0) on Bottom
```

--------------------------------

### JITX Copper Statement Examples with Shapes

Source: https://docs.jitx.com/reference/statements/gstmt/copper

Provides specific examples of using the `copper` statement with different geometric shapes like `Circle` and `Line` on various copper layers.

```JITX DSL
geom(my-net):
  copper(LayerIndex(0)) = Circle(0.0, 15.0, 1.0)
  copper(LayerIndex(1)) = Line(1.0, [Point(0.0, -5.0) Point(5.0, -5.0)])
```

--------------------------------

### SLM Configuration File Example

Source: https://docs.jitx.com/reference/slm

Illustrates the basic structure of an slm.toml file, defining project name, version, and dependencies. It shows path dependencies referencing local folders, using forward slashes for paths.

```toml
name = "motor-controller"
version = "0.1.0"
[dependencies]
JITX = { path = "{SLM_ROOT}/JITX" }
ocdb = { path = "{SLM_ROOT}/ocdb" }

```

--------------------------------

### Example Support Declaration for 1000Base-T

Source: https://docs.jitx.com/reference/jsl/protocols/ethernet/MDI/MDI-1000Base-T

An example demonstrating how to declare support statements for a 1000Base-T connection using the 'make-1000Base-T-supports' function. It maps specific differential pairs to the interface.

```jitx
; From 'JITx-Inc/microchip-networking'
make-1000Base-T-supports(
  MDI-1000Base-T,
  [C.TXRX1P_A, C.TXRX1M_A]
  [C.TXRX1P_B, C.TXRX1M_B]
  [C.TXRX1P_C, C.TXRX1M_C]
  [C.TXRX1P_D, C.TXRX1M_D]
)
```

--------------------------------

### loc Rotation Example

Source: https://docs.jitx.com/reference/jitx/pose

Illustrates how the 'loc' helper function handles rotation. This example shows a 'loc' transform with a 90-degree rotation applied to a 'Point', highlighting that rotation is applied before translation.

```scala
val p1 = Point(1.0, 5.0)
val tx = loc(1.0, 1.0, 90.0)

val p2 = tx * p1
println(p2)
; Point(-4.0, 2.0)
```

--------------------------------

### JITX Line Usage Example

Source: https://docs.jitx.com/reference/statements/gstmt/line

Provides an example of how to create an instance of the `Line` structure. It initializes a line with a specified width and a sequence of `Point` objects, forming a rectangular shape.

```Julia
Line(0.15, [
  Point(2.0, 2.0),
  Point(-2.0, 2.0),
  Point(-2.0, -2.0),
  Point(2.0, -2.0)])
```

--------------------------------

### Place Component Instance

Source: https://docs.jitx.com/getting-started/quickstart-layout

Shows how to fix the location of a component instance on the PCB. The 'place' statement specifies the instance, its coordinates, and the side of the board.

```JITX
pcb-module top-level :
  inst core : communications-core
```

```JITX
pcb-module top-level :
  inst core : communications-core
  place(core.usb-if.USBC.J) at loc(10.0, -30.5) on Top
```

--------------------------------

### Pin Assignment Swizzle Example

Source: https://docs.jitx.com/reference/jsl/pin-assignment

An example illustrating pin assignment swizzling techniques. This snippet likely contains code related to configuring pin mappings and signal routing.

```html
<a href="examples/pin-assignment/swizzle.html">swizzle</a>
```

--------------------------------

### JITX Component Instantiation Example

Source: https://docs.jitx.com/essentials/design-hierarchy

Demonstrates how to instantiate a component (NE555) within a module (top-level) in JITX. It shows the syntax for defining a component and creating an instance of it, highlighting the JITX keyword for instantiation.

```JITX
pcb-component NE555:
  ...

pcb-module top-level:

  inst timer : NE555

; ^^^^------------------- JITX Keyword for Instantiation
;      ^^^^^------------- Symbol Name of the constructed Instance
;              ^^^^^----- Instantiable (recipe) for this Instance
```

--------------------------------

### Get Reference Name

Source: https://docs.jitx.com/reference/jsl/design/introspection

Gets the final name field for a reference object. This function returns the final field in a ref, which can be either a VarRef or an IndexRef. It takes a Ref object and returns a Ref.

```APIDOC
get-ref-name(r:Ref)
  -> Ref

  Description:
    Get the final name field for a ref.

  Parameters:
    - r: Ref - Ref object that we will interrogate.

  Returns:
    Ref - The field field of the ref as either a VarRef or an IndexRef.

  Example:
    val A = #R(some.mod.C.GND[0])
    val N = get-ref-name(A)
    println("N: %_" % [N])
    ; Will Print:
    ; N: GND[0]

    val B = #R(some.other.C.VDD)
    val N2 = get-ref-name(B)
    println("N2: %_" % [N2])
    ; Will Print:
    ; N2: VDD
```

--------------------------------

### DifferentialNeckDown Usage Example

Source: https://docs.jitx.com/reference/statements/routingstructstmt/neckdown

Demonstrates how to use the DifferentialNeckDown object within a PCB routing structure definition. This example shows overriding the `clearance` property for the neckdown region of a differential trace on the Top layer.

```dsl
pcb-differential-routing-structure diff-85 :
  layer-constraints(Top):
    trace-width = 0.12
    pair-spacing = 0.127
    clearance = 0.3
    velocity = 0.19e12
    insertion-loss = 0.008
    neck-down = DifferentialNeckDown(
      clearance = 0.15
    )
```

--------------------------------

### App-Specific Keepout Land Pattern Example

Source: https://docs.jitx.com/reference/jsl/pin-assignment

An example demonstrating app-specific keepout rules for land patterns. This snippet likely contains code related to PCB layout and design constraints.

```html
<a href="examples/landpatterns/app-specific-keepout.html">app-specific-keepout</a>
```

--------------------------------

### loc Transform Chaining Example

Source: https://docs.jitx.com/reference/jitx/pose

Explains and demonstrates the chaining of multiple 'loc' transformations. This example shows how sequential transformations (rotation and translation) are applied to a point and emphasizes that the order of operations is critical and non-commutative.

```scala
val p1 = Point(1.0, 5.0)
val tx1 = loc(1.0, 1.0, 90.0)
val tx2 = loc(0.0, 0.0, 180.0)

val p2 = tx2 * tx1 * p1
println(p2)
; Point(4.0, -2.0)

val p3 = tx1 * tx2 * p1
println(p3)
; Point(6.0, 0.0)
```

--------------------------------

### Make Instance Public

Source: https://docs.jitx.com/getting-started/quickstart-layout

Demonstrates how to make a component instance public, allowing it to be accessed from other modules. This is achieved by prepending the 'public' keyword to the instance declaration.

```JITX
inst usb-if : connectors/components/USB/USBTypeC/USBC-HighSpeed-Iface()
```

```JITX
public inst usb-if : connectors/components/USB/USBTypeC/USBC-HighSpeed-Iface()
```
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