### Start TIMER1 with Internal Clock and 1:1 Prescaler

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Initializes and starts TIMER1 using the internal system clock (FSYS) with a 1:1 prescaler. It also clears the TIMER1 interrupt flag.

```asm
; TIMER1 使用 FSYS，1:1 预分频，开启
CLR  TMR1H
CLR  TMR1L
CLRB PIR1,TMR1IF
LDIA B'00000001'
LD   T1CON,A
```

--------------------------------

### Reset Vector Initialization

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Sets up the reset vector and interrupt vector for the microcontroller. The START label indicates where user initialization code should begin.

```asm
ORG 0000H          ; 复位向量
JP START

ORG 0004H          ; 中断向量
JP INT_SERVICE

START:
    ; 用户初始化代码
END
```

--------------------------------

### TABLE Instruction Example

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Demonstrates using the TABLE instruction to read a byte from Flash memory. The address is set using TABLE_SPL and TABLE_SPH. The high byte is read into TABLE_DATAH.

```asm
LDIA 02H
LD   TABLE_SPL,A
LDIA 06H
LD   TABLE_SPH,A
TABLE R01              ; Flash[0602H] 低 8 位 -> R01，高 8 位 -> TABLE_DATAH
LD   A,TABLE_DATAH
LD   R02,A

ORG 0600H
DW 1234H
DW 2345H
DW 3456H              ; 地址 0602H
DW 0000H
```

--------------------------------

### ADC Read AN0 Example

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Reads analog channel AN0 using 12-bit left-aligned format with a specific ADC clock and enables the ADC. Ensure a DELAY subroutine is available for capacitor stabilization.

```assembly
; AN0 = RA0，12-bit 左对齐，ADC 时钟 FSYS/128，打开 ADC
LDIA B'10000000'
LD   ADCON1,A       ; ADFM=1/按项目格式需求设置；CHS4=0
SETB TRISA,0        ; RA0 输入
SETB ANSEL0,0       ; AN0 模拟功能打开
LDIA B'11000001'    ; ADCS=11, CHS=0000, ADON=1
LD   ADCON0,A
CALL DELAY          ; 等待采样电容稳定
SETB ADCON0,GO      ; 启动 A/D
SZB  ADCON0,GO      ; 等待 GO 清零
JP   $-1
LD   A,ADRESH
LD   RESULTH,A
LD   A,ADRESL
LD   RESULTL,A
```

--------------------------------

### Configure PORTA as Output and Input

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Sets the lower 4 bits of PORTA as output and the upper 4 bits as input. Then, it outputs a value to PORTA.

```asm
; 设置 PORTA<3:0> 为输出，PORTA<7:4> 为输入
LDIA B'11110000'
LD   TRISA,A

; 输出 PORTA<1:0> = 1，PORTA<3:2> = 0
LDIA 03H
LD   PORTA,A
```

--------------------------------

### Enable Peripheral Interrupts and Global Interrupts

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

This snippet demonstrates the general steps to enable a specific peripheral interrupt (TIMER1 in this case), the peripheral interrupt enable bit, and the global interrupt enable bit.

```asm
; 例：打开 TIMER1 中断
SETB PIE1,TMR1IE
SETB INTCON,PEIE
SETB INTCON,GIE
```

--------------------------------

### Initialize TIMER0 with External Clock and Prescaler

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Configures TIMER0 to use an external clock source (T0CKI) with a 1:256 prescaler. It also enables the TIMER0 interrupt.

```asm
; TIMER0 使用内部 FSYS/4，预分频 1:256
; OPTION_REG: T0CS=0, PSA=0, PS=111
CLRWDT
LDIA B'10000111'
LD   OPTION_REG,A
CLR  TMR0
CLRB INTCON,T0IF
SETB INTCON,T0IE
SETB INTCON,GIE
```

--------------------------------

### Prepare for STOP Low-Power Mode

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Configures the microcontroller for STOP low-power mode. It clears interrupts, sets I/O directions, and saves a flag before entering STOP. Ensure I/O states do not cause leakage.

```asm
SLEEP_MODE:
    CLR  INTCON
    LDIA B'00000000'
    LD   TRISA,A
    LD   TRISB,A
    LD   TRISC,A
    LDIA 0A5H
    LD   SP_FLAG,A
    CLRWDT
    STOP
```

--------------------------------

### Enable PORTB Weak Pull-up Resistors

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Enables the global weak pull-up on PORTB and specifically enables pull-ups for RB0 and RB1.

```asm
; 使能 PORTB 弱上拉总控，并打开 RB0/RB1 上拉
CLRB OPTION_REG,RBPU
LDIA B'00000011'
LD   WPUB,A
```

--------------------------------

### Configure ADC Pin as Digital Output

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

This snippet demonstrates how to configure an Analog-to-Digital Converter (ADC) pin as a general-purpose digital output. It involves clearing bits in ANSELx and TRISx registers and setting the desired state in the PORTx register.

```asm
CLRB ANSEL0,0
CLRB TRISA,0
CLRB PORTA,0
```

--------------------------------

### Asynchronous UART Initialization

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Initializes the USART for asynchronous UART communication at 9600 bps with an 8 MHz system clock. Ensure the CONFIG setting selects the appropriate USART pins (e.g., RC0=TX, RC1=RX).

```assembly
; CONFIG 需要选择 USART_SEL，例如 RC0=TX、RC1=RX
; 设置波特率 9600，FSYS=8MHz：SPBRG=51
LDIA 33H
LD   SPBRG,A

; 异步模式，8-bit，发送使能
LDIA B'00100000'    ; TXEN=1, SYNC=0
LD   TXSTA,A

; 串口端口使能，连续接收使能
LDIA B'10010000'    ; SPEN=1, CREN=1
LD   RCSTA,A

; 可选：开启接收中断
SETB PIE1,RCIE
SETB INTCON,PEIE
SETB INTCON,GIE
```

--------------------------------

### Configure TIMER2 for a Specific Period

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Sets up TIMER2 to generate an interrupt after a specific period (PR2 = 249). It configures the prescaler to 1:4 and the postscaler to 1:1, then enables TIMER2.

```asm
; TIMER2: PR2=249，预分频 1:4，后分频 1:1，开启
LDIA 0F9H
LD   PR2,A
CLR  TMR2
CLRB PIR1,TMR2IF
LDIA B'00000101'   ; TMR2ON=1, T2CKPS=01
LD   T2CON,A
```

--------------------------------

### Write Byte to EEPROM

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Writes a single byte to EEPROM. Ensure WADDR and WDATA are set before calling. Uses a 10ms timing setting for EEPROM write.

```asm
; WADDR = EEPROM 地址，WDATA = 待写数据
EEPDATA_WRITE:
    LD   A,WADDR
    LD   EEADR,A
    LD   A,WDATA
    LD   EEDAT,A

    CLRWDT
    CLR  EECON1
    SETB EECON1,EETIME0
    SETB EECON1,EETIME1  ; 选择 10ms，保守设置
    CLRB EECON1,EEPGD    ; 选择 EEPROM
    SETB EECON1,WREN

    ; 解锁序列期间关闭全局中断
    CLRB F_GIE_ON
    SZB  INTCON,GIE
    SETB F_GIE_ON
    CLRB INTCON,GIE
    SZB  INTCON,GIE
    JP   $-2

    LDIA 055H
    LD   EECON2,A
    LDIA 0AAH
    LD   EECON2,A
    SETB EECON1,WR
    NOP
    NOP
    CLRWDT
    CLRB EECON1,WREN

    SZB  F_GIE_ON
    SETB INTCON,GIE
    RET
```

--------------------------------

### EEPROM Read Byte

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Reads a single byte from the EEPROM at a specified address. Ensure the address is loaded into RADDR and the result is stored in RDATA.

```assembly
; RADDR = EEPROM 地址，RDATA = 返回数据
EEPDATA_READ:
    LD   A,RADDR
    LD   EEADR,A
    CLRB EECON1,EEPGD    ; 选择 EEPROM
    SETB EECON1,RD       ; 启动读
    NOP
    NOP
    LD   A,EEDAT
    LD   RDATA,A
    RET
```

--------------------------------

### Interrupt Service Routine Template

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

A template for an interrupt service routine (ISR) that includes saving and restoring the accumulator (ACC) and status registers. Ensure the interrupt service code is placed correctly within the INT_START and INT_BACK labels.

```asm
ORG 0004H
INT_START:
    CALL PUSH      ; 保存 ACC、STATUS
    ; interrupt service code here
INT_BACK:
    CALL POP       ; 恢复 ACC、STATUS
    RETI

PUSH:
    LD   ACC_BAK,A
    SWAPA STATUS
    LD   STATUS_BAK,A
    RET

POP:
    SWAPA STATUS_BAK
    LD   STATUS,A
    SWAPR ACC_BAK
    SWAPA ACC_BAK
    RET
```

--------------------------------

### Read Program Memory

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Reads a 16-bit instruction or data word from program memory. The address is specified by RADDRH and RADDRL.

```asm
; RADDRH:RADDRL = 程序存储器地址
; RDATH:RDATL = 读出的 16-bit 指令/数据字
LD   A,RADDRL
LD   EEADR,A
LD   A,RADDRH
LD   EEADRH,A
SETB EECON1,EEPGD
SETB EECON1,RD
NOP
NOP
LD   A,EEDAT
LD   RDATL,A
LD   A,EEDATH
LD   RDATH,A
```

--------------------------------

### USART Send Byte

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Sends a byte of data stored in the accumulator (ACC) via the USART. It waits until the transmit shift register is empty before loading the data.

```assembly
; ACC 中为待发送数据
WAIT_TX:
    SNZB PIR1,TXIF    ; TXREG 空时 TXIF=1
    JP   WAIT_TX
    LD   TXREG,A
```

--------------------------------

### USART Receive Byte

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Receives a byte of data from the USART. It waits until the receive register is full (RCIF flag is set) before reading the data.

```assembly
WAIT_RX:
    SNZB PIR1,RCIF    ; RCREG 有数据时 RCIF=1
    JP   WAIT_RX
    LD   A,RCREG
```

--------------------------------

### OERR Error Recovery

Source: https://github.com/tobebestkk/cms79f72x/blob/main/CMS79F72x_项目资料_Context7_合并版.md

Recovers from an overrun error (OERR) in the USART receiver. This involves clearing and re-setting the Continuous Receive Enable (CREN) bit.

```assembly
; 若 RCSTA.OERR=1，FIFO 溢出，接收停止
SNZB RCSTA,OERR
JP   NO_OERR
CLRB RCSTA,CREN
SETB RCSTA,CREN
NO_OERR:
```

=== COMPLETE CONTENT === This response contains all available snippets from this library. No additional content exists. Do not make further requests.