STM32Cube CMSIS Device H7

https://github.com/stmicroelectronics/cmsis-device-h7
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### New Device Support and Startup Files

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Addition of support for new STM32H7 device families and their corresponding startup files for various toolchains.

```APIDOC
New Device Support:
  - Added support for STM32H7A3xx, STM32H7A3xxQ, STM32H7B3xx, STM32H7B3xxQ, STM32H7B0xx, and STM32H7B0xxQ devices.
  - Added support for STM32H745xx, STM32H747xx, STM32H755xx, STM32H757xx Dual Core devices and STM32H742xx single core device.

Startup Files (.s):
  - Added for EWARM, MDK-ARM, and STM32CubeIDE/SW4STM32 toolchains.
  - Examples:
    - startup_stm32h7a3xx.s
    - startup_stm32h7b3xxq.s
    - startup_stm32h745xx.s
    - startup_stm32h742xx.s
```

--------------------------------

### Align GCC Startup Files with EWARM/MDK-ARM

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates GCC startup files for all devices to match the initialization sequence of EWARM/MDK-ARM. Specifically, it ensures that 'SystemInit' is called before any memory access, preventing issues with external memory initialization.

```armasm
/* GCC Startup File Alignment */
    LDR     R0, =SystemInit
    BLX     R0

    LDR     R0, =__main
    BX      R0

    END
```

--------------------------------

### Improve GCC Startup Files for .data Copy

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Optimizes GCC startup files to reduce the number of load operations required for copying the .data section. This enhancement aims to speed up the initialization process and improve startup performance.

```armasm
/* Optimized .data section copy for GCC startup files */
LDR     R0, =_sdata
LDR     R1, =_edata
LDR     R2, =_la_data

CMP     R0, R1
BEQ     __main

/* Optimized copy loop */
COPY_DATA:
    LDR     R3, [R2], #4
    STR     R3, [R0], #4
    CMP     R0, R1
    BNE     COPY_DATA

__main:
```

--------------------------------

### Add EWARM/MDK-ARM/GCC Linker Files for STM32H745xG/STM32H747xG

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Provides EWARM, MDK-ARM, and GCC linker files for STM32H745xG and STM32H747xG devices. These devices feature 1MB flash, split into 512KB per bank, and the linker files are configured accordingly for each toolchain.

```linker-script
/* EWARM Linker Script for STM32H745xG/STM32H747xG (1MB Flash) */
/* ... */

/* MDK-ARM Linker Script for STM32H745xG/STM32H747xG (1MB Flash) */
/* ... */

/* GCC Linker Script for STM32H745xG/STM32H747xG (1MB Flash) */
/* ... */
```

--------------------------------

### EWARM Linker Files for New Devices

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Provides EWARM linker files for the newly supported STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx, and STM32H730xxQ devices. These include configurations for 1MB flash and a subset for 512KB flash (STM32H723xE, STM32H725xE).

```linker-script
/* EWARM Linker Script for STM32H723xx (1MB Flash) */
/* ... */

/* EWARM Linker Script for STM32H725xE (512KB Flash) */
/* ... */
```

--------------------------------

### Add System Initialization Files for STM32H7

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Introduces new system initialization template source files for STM32H7 series microcontrollers. These files support single-core and various dual-core boot configurations, including scenarios with gated cores.

```C
system_stm32h7xx_singlecore.c
system_stm32h7xx_dualcore_boot_cm4_cm7.c
system_stm32h7xx_dualcore_bootcm7_cm4gated.c
system_stm32h7xx_dualcore_bootcm4_cm7gated.c
```

--------------------------------

### Add Support for New STM32H7 Devices (V1.9.0)

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Introduces support for several new STM32H7 microcontroller variants, including STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx, and STM32H730xxQ. This includes new header files, startup files for EWARM, MDK-ARM, and GCC, and updated part number lists.

```c
/* New header files added */
// stm32h723xx.h
// stm32h725xx.h
// stm32h733xx.h
// stm32h735xx.h
// stm32h730xx.h
// stm32h730xxq.h

/* Part number list update in stm32h7xx.h */
/* STM32H723xx: STM32H723VGH6, STM32H723VGT6, ... */
/* STM32H725xx: STM32H725AGI6, STM32H725IGK6, ... */
/* STM32H733xx: STM32H733VGH6, STM32H733VGT6, ... */
/* STM32H735xx: STM32H735AGI6, STM32H735IGK6, ... */
/* STM32H730xx: STM32H730VBH6, STM32H730VBT6, ... */
/* STM32H730xxQ: STM32H730IBT6Q, STM32H730ABI6Q, ... */
```

```armasm
/* New startup files for EWARM, MDK-ARM, GCC */
// startup_stm32h723xx.s
// startup_stm32h725xx.s
// startup_stm32h733xx.s
// startup_stm32h735xx.s
// startup_stm32h730xx.s
// startup_stm32h730xxq.s
```

--------------------------------

### Add Linker Files for Dual Core and STM32H742xx Devices

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Adds linker files for EWARM, MDK-ARM, and SW4STM32 environments to support dual-core STM32H7 devices. Additionally, specific linker files for STM32H742xx devices using EWARM are included.

```APIDOC
Add EWARM, MDK-ARM and SW4STM32 Dual Core devices linker files
Add EWARM STM32H742xx devices linker files
```

--------------------------------

### EWARM Linker File Additions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

New EWARM linker files (.icf) added for specific STM32H7A3 devices with reduced Flash sizes.

```APIDOC
EWARM Linker Files (.icf):
  - Added for STM32H7A3 devices with reduced Flash size to 1MB.
  - Files include:
    - stm32h7a3xg_flash.icf
    - stm32h7a3xg_flash_rw_sram1.icf
    - stm32h7a3xg_flash_rw_sram2.icf
    - stm32h7a3xgq_flash.icf
    - stm32h7a3xgq_flash_rw_sram1.icf
    - stm32h7a3xgq_flash_rw_sram2.icf
```

--------------------------------

### SDMMC Instance Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Management of SDMMC (Secure Digital MultiMedia Card) instance definitions.

```APIDOC
SDMMC Instance Definitions:
  - Removed useless definition of 'SDMMC' instance.
  - Kept only definitions for 'SDMMC1' and 'SDMMC2'.
```

--------------------------------

### Add EWARM Linker Files for STM32H742xG/STM32H743xG

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Introduces EWARM linker files for STM32H742xG and STM32H743xG devices, which come with 1MB flash (512KB per bank). These files configure memory regions for dual-bank operation.

```linker-script
/* EWARM Linker Script for STM32H742xG/STM32H743xG (1MB Flash) */
/* ... */
```

--------------------------------

### STM32H7xx.h Header Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates and additions to the main STM32H7xx.h header file, including enumeration definitions, device identification, and part number lists.

```APIDOC
ErrorStatus Enumeration:
  - Updated definition in stm32h7xx.h with SUCCESS set to numerical value zero.

STM32H7_DEV_ID Define:
  - Added define allowing to identify the H7 Device ID.

Part Numbers List in stm32h7xx.h:
  - Added part numbers for STM32H7A3xx, STM32H7A3xxQ, STM32H7B3xx, STM32H7B3xxQ, STM32H7B0xx, and STM32H7B0xxQ devices.
  - Example entries:
    - STM32H7A3xx: STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6
    - STM32H7B0xx: STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ
```

--------------------------------

### TIM Macro Implementation Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates to the implementation of TIM (Timer) related macros.

```APIDOC
TIM Macros:
  - Updated implementation for IS_TIM_REMAP_INSTANCE macro.
  - Updated implementation for IS_TIM_SYNCHRO_INSTANCE macro.
```

--------------------------------

### TIM Channel Instance Check Macro Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Extends the IS_TIM_CCX_INSTANCE macro to include TIM_CHANNEL_4 through TIM_CHANNEL_6. This update allows for proper validation of timer capture/compare channels up to channel 6.

```c
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_5) || ((CHANNEL) == TIM_CHANNEL_6))
```

--------------------------------

### GPIO Instance Check Macro Addition

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Adds a new macro, IS_GPIO_AF_INSTANCE, for validating GPIO alternate function instances. This macro helps in ensuring that the correct GPIO ports are configured for alternate functions.

```c
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE) || ((INSTANCE) == GPIOF) || ((INSTANCE) == GPIOG) || ((INSTANCE) == GPIOH) || ((INSTANCE) == GPIOI) || ((INSTANCE) == GPIOJ) || ((INSTANCE) == GPIOK))
```

--------------------------------

### HRTIM Timer Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates to HRTIM (High Resolution Timer) definitions, specifically regarding timer instance pointers.

```APIDOC
HRTIM Timer Pointers:
  - Updated definitions of HRTIM1_TIMA to HRTIM1_TIME.
  - These now point to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef.
```

--------------------------------

### STM32H750xx Device Support

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Adds support for the STM32H750xx value line devices. This includes the necessary header file and startup files for various development environments (EWARM, MDK-ARM, SW4STM32).

```c
#include "stm32h750xx.h"
```

--------------------------------

### SDMMC Instance Check Macro Addition

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Introduces a new macro for validating SDMMC peripheral instances. This macro aids in compile-time checks to ensure that only valid SDMMC instances are used in the code.

```c
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1) || ((INSTANCE) == SDMMC2))
```

--------------------------------

### SystemCoreClock Variable Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Update to the system_stm32h7xx.c file concerning the SystemCoreClock global variable.

```APIDOC
SystemCoreClock Global Variable:
  - Updated system_stm32h7xx.c to reflect the current core clock in SystemCoreClock.
  - Handles Corex-M7 or Corext-M4 clock depending on the context in Dual Core devices.
```

--------------------------------

### Update System Clock Flash Latency Settings

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Enhances system initialization files (system_stm32h7xx.c, etc.) by adding flash latency settings that adapt to CPU frequency changes (increasing or decreasing). This ensures stable memory access during dynamic clock frequency adjustments.

```c
/* Update system_stm32h7xx.c */
void SystemCoreClockUpdate(void)
{
  /* ... */
  /* Update Flash Latency based on CPU frequency */
  if (SystemCoreClock <= 100000000U) {
    FLASH->ACR &= ~FLASH_ACR_LATENCY;
  } else if (SystemCoreClock <= 200000000U) {
    FLASH->ACR = FLASH_ACR_LATENCY_1;
  } else {
    FLASH->ACR = FLASH_ACR_LATENCY_2;
  }
  /* ... */
}
```

--------------------------------

### Fix MDK-ARM Scatter Files for Dual Core

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects a typo within the IRAM1 section of MDK-ARM template scatter files for dual-core devices. This ensures correct memory region definitions for the secondary core, preventing potential linking or runtime issues.

```linker-script
/* MDK-ARM Scatter File Fix */
LR_IROM1 0x08000000 0x00100000  {
  ER_IROM1 0x08000000 0x00100000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
  }
  RAM_D3 0x30000000 0x00020000  {
    /* Corrected IRAM1 section definition */
    *.o (.bss)
    .ANY (.bss)
  }
}
```

--------------------------------

### Add UID_BASE Definition

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Adds the definition for UID_BASE, which represents the base address of the Unique Device ID register, to the STM32H7xx include files for specific microcontroller variants.

```C
Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
  stm32h743xx.h, stm32h750xx.h and stm32h753xx.h
```

--------------------------------

### RAMECC and EXTI SWIER3 Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Introduces definitions for RAMECC_MonitorTypeDef and RAMECC_TypeDef structures, along with RAMECC peripheral base addresses and register bit definitions. It also adds the IS_RAMECC_MONITOR_ALL_INSTANCE macro and EXTI SWIER3 bit definitions.

```APIDOC
Add definition of RAMECC_MonitorTypeDef and RAMECC_TypeDef structure.
Add definition of RAMECC peripheral base addresses.
Add RAMECC peripheral registers bit definitions.
Add IS_RAMECC_MONITOR_ALL_INSTANCE macro.
Add EXTI SWIER3 bit definitions.
```

--------------------------------

### ART Accelerator Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Definitions related to the ART accelerator for Cortex-M4, including structure, instance, and control bit fields.

```APIDOC
ART_TypeDef Structure:
  - Definition added for ART accelerator for Cortex-M4 available in Dual Core devices.

ART Instance:
  - Definition added for 'ART' pointer to ART_TypeDef structure.

ART Control Bit Fields:
  - ART_CTR_EN: Definition for enabling the ART accelerator.
  - ART_CTR_PCACHEADDR: Definition for the ART accelerator program cache address.
```

--------------------------------

### DMA Register and Bit Field Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Definitions for DMA registers and specific bit fields, including control and configuration bits for bufferable transfers and line offset modes.

```APIDOC
DMA_SxCR Register:
  - DMA_SxCR_TRBUFF: Bit field definition allowing to enable/disable bufferable transfers.

DMA2D Register Definitions:
  - CR_LOM: Definition for Line Ofset Mode.
  - OPFCCR_SB: Definition for Swap Bytes feature.
  - CR_MODE: Updated bit definition.
  - FGOR_LO: Updated bit definition.
  - BGOR_LO: Updated bit definition.
  - OOR_LO: Updated bit definition.
```

--------------------------------

### Update TIM12 Master Instance Define

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Modifies the IS_TIM_MASTER_INSTANCE define in STM32H7 device header files to correctly include TIM12 as a potential master timer. This ensures proper configuration for timer synchronization scenarios.

```c
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM12))
```

--------------------------------

### Fix CMSIS Device Version Definition

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects the definition of __STM32H7xx_CMSIS_DEVICE_VERSION in the stm32h7xx.h file. This ensures the version macro accurately reflects the current CMSIS-Device pack version, aiding in compatibility checks.

```c
#define __STM32H7xx_CMSIS_DEVICE_VERSION  (0x01090000) /*!< STM32H7xx CMSIS Device Version Number */
```

--------------------------------

### ETH_TypeDef Definition Fix

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Correction of a typo in the ETH_TypeDef definition related to reserved registers.

```APIDOC
ETH_TypeDef Definition:
  - Fixed typo in definition for 'RESERVED16' registers.
  - Changed type from int32_t to uint32_t.
```

--------------------------------

### EXTI and FLASH Register Definition Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Includes definitions for specific EXTI bits (EXTI8_PK to EXTI11_PK, EXTI13_PK) within SYSCFG_EXTICR3 and SYSCFG_EXTICR4. Also updates FLASH latency definitions and removes redundant bit definitions.

```APIDOC
SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK, SYSCFG_EXTICR4_EXTI13_PK definitions added.
FLASH_LATENCY_DEFAULT definition added for default safe FLASH latency.
```

--------------------------------

### Use D2_AXISRAM_BASE for Cortex-M4 VTOR

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates system initialization files for dual-core devices to use D2_AXISRAM_BASE for the Cortex-M4 VTOR when executing from RAM. This aligns with the Harvard architecture by using the instruction bus alias for better performance.

```c
/* Update system_stm32h7xx_dualcore_boot_cm4_cm7.c */
/* ... */
if (SCB->VTOR == D2_AHBSRAM_BASE) {
  SCB->VTOR = D2_AXISRAM_BASE; /* Use instruction bus alias for M4 VTOR */
}
/* ... */
```

--------------------------------

### Fix IS_SMBUS_INSTANCE Macro

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates the IS_SMBUS_INSTANCE macro definition to include the correct list of SMBUS instances for each STM32H7 line. This ensures the macro accurately validates SMBUS peripheral instances.

```c
#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == SMBUS1) || ((INSTANCE) == SMBUS2)) /* Example for a specific H7 line */
```

--------------------------------

### SYSCFG and PWRCR Register Definitions Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates the SYSCFG_TypeDef structure to include the CFGR register for controlling error connections to timer break inputs. It also adds definitions for SYSCFG_CFGR bit fields and PWRCR registers, including their bit fields, for managing power overdrive.

```APIDOC
SYSCFG_TypeDef structure update:
  Add CFGR register: Controls connection between ECC/PVD errors and Cortex-M7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs.
  Add definitions of SYSCFG_CFGR register bit fields.
  PWRCR registers: Control PWR overdrive enable/disable for Voltage Scaling zero.
  Add SYSCFG_PWRCR register bit fields.
```

--------------------------------

### FLASH Sector and Option Byte Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates the FLASH configuration by changing the sector number from 16 to 8 (per bank) and revising the FLASH user option bytes definitions. It also fixes the FLASH_BANK_SIZE definition by adding parentheses and removes redundant SNB bit definitions.

```APIDOC
Update FLASH sector number to 8 instead of 16 (8 sectors for each bank).
Remove extra bit definition: FLASH_CR_SNB_3 to FLASH_CR_SNB_7.
Update FLASH user option bytes bit definition.
Fix FLASH_BANK_SIZE definition: add parenthesis.
```

--------------------------------

### Fix SCB->SCR Register Usage for SEVONPEND

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects the usage of the SCB->SCR register by enabling SEVONPEND. This ensures that an interrupt generated by the other CPU can wake up the current CPU after a WFI/WFE instruction, even if the interrupt is disabled.

```c
/* Update system_stm32h7xx.c */
/* Enable SEVONPEND to wake up CPU on interrupt */
SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
```

--------------------------------

### OCTOSPI Register and Structure Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Definitions for the OCTOSPI peripheral, including structure updates and bit fields for multiplexed mode features.

```APIDOC
OCTOSPIM_TypeDef Structure:
  - Updated definition with 3 PCR registers instead of 8.
  - Applies to STM32H7A3/B3/B0 devices supporting OctoSPI.

OCTOSPIM_CR Register Bit Fields:
  - OCTOSPIM_CR_MUXEN: Definition to support OctoSPI IO Manager multiplexed mode feature.
  - OCTOSPIM_CR_REQ2ACK_TIME: Definition to support OctoSPI IO Manager multiplexed mode feature.
```

--------------------------------

### RCC Register Definitions and Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Definitions and modifications for RCC (Reset and Clock Control) registers, specifically related to CRYP, HASH, and other peripheral clock enables/resets.

```APIDOC
RCC_AHB2ENR, RCC_AHB2RSTR, RCC_AHB2LPENR Registers:
  - Removed definitions for RCC_AHB2ENR_CRYPEN, RCC_AHB2RSTR_CRYPRST, RCC_AHB2LPENR_CRYPLPEN, RCC_AHB2ENR_HASHEN, RCC_AHB2RSTR_HASHRST, RCC_AHB2LPENR_HASHLPEN.
  - These removals apply to H7 devices that do not support CRYP/HASH (e.g., STM32H742/43/45/47/A3).
```

--------------------------------

### HSEM Core ID Macro Fix

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Fixes the HSEM_CR_COREID_CURRENT macro by adding parentheses. This ensures the correct evaluation of the HSEM core ID, crucial for semaphore operations.

```c
#define HSEM_CR_COREID_CURRENT (0x00000000U) /*!< HSEM_CR_COREID_CURRENT: Current Core Identifier */
```

--------------------------------

### Misra-C 2012 Compliance for Mask Bits

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates the definition of mask bits within the STM32H7xx include files by appending the UL suffix to ensure compliance with Misra-C 2012 standards.

```C
Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance.
```

--------------------------------

### Update SystemCoreClockUpdate Function

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Modifies the SystemCoreClockUpdate function in system_stm32h7xx.c to set the default system clock and PLL source to HIS instead of CSI. This change aligns the function's behavior with the product specifications for initial clock configuration.

```c
/* Update SystemCoreClockUpdate implementation to use HIS as default PLL source */
void SystemCoreClockUpdate(void)
{
  uint32_t uhDivValue = 0U;
  uint32_t pllvco = 0U;

  /* PLL clock source is HIS */
  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN */
  pllvco = (HSE_VALUE / PLLM) * PLLN;

  /* System clock frequency = PLL_VCO / PLLR */
  SystemCoreClock = pllvco / PLLR;

  /* ... rest of the function ... */
}
```

--------------------------------

### Remove D3 Domain Defines from DBGMCU_CR_DBG

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Removes extraneous field definitions related to Domain D3 from the DBGMCU_CR_DBG register in STM32H7 device header files. This cleans up register definitions for devices that do not utilize or expose these specific domain features.

```c
// Removed DBGMCU_CR_DBG_D3_... fields
```

--------------------------------

### USB OTG Register Bit Field Definitions

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Additions to USB OTG (On-The-Go) register definitions, including interrupt masks, error flags, and configuration bits.

```APIDOC
USB_OTG_GAHBCFG Register:
  - Updated bit definition to align with LL_USB usage.

USB_OTG_DOEPMSK Register Bit Fields:
  - USB_OTG_DOEPMSK_AHBERRM: Added definition.
  - USB_OTG_DOEPMSK_BERRM: Added definition.
  - USB_OTG_DOEPMSK_NAKM: Added definition.
  - USB_OTG_DOEPMSK_NYETM: Added definition.

USB_OTG_DIEPINT Register Bit Fields:
  - USB_OTG_DIEPINT_AHBERR: Added definition.
  - USB_OTG_DIEPINT_INEPNM: Added definition.

USB_OTG_DOEPINT Register Bit Fields:
  - USB_OTG_DOEPINT_AHBERR: Added definition.
  - USB_OTG_DOEPINT_OUTPKTERR: Added definition.
  - USB_OTG_DOEPINT_BERR: Added definition.
  - USB_OTG_DOEPINT_NAK: Added definition.
  - USB_OTG_DOEPINT_STPKTRX: Added definition.
```

--------------------------------

### ADC Common Instance Check Macro Fix

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects the IS_ADC_COMMON_INSTANCE macro by adding necessary parentheses. This ensures the macro evaluates correctly, preventing potential compilation errors when checking ADC common instances.

```c
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2) || ((INSTANCE) == ADC3))
```

--------------------------------

### Remove FLASH Swap Bank Fields for STM32H750xx

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Removes FLASH_OPTCR_SWAP_BANK and FLASH_OPTSR_SWAP_BANK_OPT field definitions from the STM32H750xx device header file. These fields are specific to dual-bank flash devices and are not applicable to the single-bank STM32H750xx value line devices.

```c
// Removed FLASH_OPTCR_SWAP_BANK and FLASH_OPTSR_SWAP_BANK_OPT fields for STM32H750xx
```

--------------------------------

### CRYP, ADC, I2C, SAI, SPI, QUADSPI Register Bit Field Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Details specific bit field definition updates across several peripherals for STM32H7 Rev.V devices. This includes CRYP_CR_NPBLB, ADC_CR_BOOST, removal of I2C_CR1_SWRST, addition of SAI_xCR1_NODIV, renaming of SPI_TXCRC_RXCRC, and fixes for QUADSPI_SR_FLEVEL.

```APIDOC
CRYP_CR_NPBLB bit field definition added for STM32H7 Rev.V devices.
ADC_CR_BOOST bit field definition updated for STM32H7 Rev.V devices (2 bits instead of 1).
I2C_CR1_SWRST definition removed for alignment with the reference manual.
SAI_xCR1_NODIV bit field definition added upon SAI peripheral update for STM32H7 Rev.V devices.
SPI_TXCRC_RXCRC renamed to SPI_RXCRC_RXCRC (typo fix and alignment).
QUADSPI_SR_FLEVEL bit field definition fixed: Mask on 6 bits (0x3F) instead of 5 bits (0x1F), and QUADSPI_SR_FLEVEL_6 definition added.
```

--------------------------------

### SDMMC Bit Definition Fixes

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects typos in the SDMMC peripheral's bit definitions, specifically for SDIO interrupt enable bits. This ensures accurate register manipulation for SDMMC functionality.

```c
#define SDMMC_MASK_SDIOITIE_Pos (0U) /*!< SDMMC_MASK_SDIOITIE: SDIO IT Enable Position */
#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< SDMMC_MASK_SDIOITIE: SDIO IT Enable Mask */
```

--------------------------------

### PWR Register Definition Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Removes an extraneous bit definition (PWR_CR1_RLPSN) from the PWR peripheral registers and adds a new bit definition for PWR_WKUPEPR_WKUPEN.

```APIDOC
Remove useless PWR_CR1_RLPSN definition.
Add PWR bit definition PWR_WKUPEPR_WKUPEN.
```

--------------------------------

### Peripheral Bit Definition Updates

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Contains updates to bit definitions for various STM32H7 peripherals including USART, SMARTCARD, DAC, FDCAN, USB (OTEPSPRM register), CEC (RXDR register), SPI, I2S, BDMA, and FMC. These updates ensure accurate register configuration for these peripherals.

```c
// Example for USART bit definition update
#define USART_CR1_UE (1UL << 0) /*!< USART Control Register 1: UE bit */

// Example for FDCAN bit definition update
#define FDCAN_CCU_CCCR_INIT (1UL << 0) /*!< FDCAN Control Configuration: INIT bit */
```

--------------------------------

### RCC Register Definitions Update for STM32H7 Rev.V

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Modifies the RCC_TypeDef structure for STM32H7 Rev.V devices. This includes renaming ICSCR to HSICFGR with updated bit definitions, adding the new CSICFGR register and its bit definitions, and removing the RCC_Core_TypeDef structure for single-core lines.

```APIDOC
RCC_TypeDef structure update (STM32H7xx Rev.V):
  ICSCR: Renamed to HSICFGR (HSI Clock Calibration Register).
  RCC_ICSCR_XXX bit definitions: Renamed to RCC_HSICFGR_XXX.
  CSICFGR: New register (CSI Clock Calibration Register) added with dedicated bit definitions.
  RCC_Core_TypeDef structure: Removed from STM32H743xx/53xx and STM32H750xx lines, as it was only for Dual Core devices.
```

--------------------------------

### SYSCFG Bit Definition Fixes

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Addresses several typos and incorrect bit width definitions within the SYSCFG peripheral registers, including PMCR and EXTICR registers. These corrections ensure proper configuration of system control and external interrupt multiplexing.

```c
#define SYSCFG_PMCR_EPIS_SEL_Pos (0U) /*!< SYSCFG_PMCR_EPIS_SEL: EPIS Selection Position */
#define SYSCFG_PMCR_EPIS_SEL_Msk (0x3UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< SYSCFG_PMCR_EPIS_SEL: EPIS Selection Mask */

#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << 0) /*!< SYSCFG_EXTICR1_EXTI0: EXTI 0 configuration Mask */
#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << 12) /*!< SYSCFG_EXTICR1_EXTI3: EXTI 3 configuration Mask */
```

--------------------------------

### SystemCoreClockUpdate Function Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Modifies the SystemCoreClockUpdate() function in system_stm32h7xx.c to utilize direct register access. This change improves the efficiency and reliability of system clock frequency calculation.

```c
void SystemCoreClockUpdate(void) {
  /* Update the SystemCoreClock variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq();
}
```

--------------------------------

### GPIO BSRR Register Update

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Updates the definition for the GPIO BSRR (Bit Set Reset) register. This change ensures accurate bit manipulation for setting and resetting GPIO pins.

```c
typedef struct {
  __IO uint32_t MODER;
  __IO uint32_t OTYPER;
  __IO uint32_t OSPEEDR;
  __IO uint32_t PUPDR;
  __IO uint32_t IDR;
  __IO uint32_t RESERVED0;
  __IO uint32_t BRR; /*!< GPIO port output data register [0-15] */
  __IO uint32_t BSRR; /*!< GPIO port bit set/reset register */
} GPIO_TypeDef;
```

--------------------------------

### Fix RCC Registers Reset Values

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects the reset values for RCC registers within the system initialization files. This ensures that the default state of the RCC peripheral is accurately represented and handled during system startup.

```c
/* Fix RCC registers reset values */
/* Example: RCC_CR_RESET_VALUE = 0x01000000 */
```

--------------------------------

### Fix FDCAN_ECR_TEC_Msk Definition

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Corrects the FDCAN_ECR_TEC_Msk definition in STM32H7 devices header files. The bit field width has been updated from 4 bits to 8 bits to accurately reflect the register specification.

```c
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< FDCAN_ECR_TEC_Msk */
```

--------------------------------

### Disable FMC Bank1

Source: https://github.com/stmicroelectronics/cmsis-device-h7/blob/master/Release_Notes.html

Disables FMC Bank1 after reset in system initialization files. This prevents CPU speculation access that can block FMC usage for other masters like LTDC for up to 24us, improving peripheral access timing.

```c
/* Disable FMC Bank1 after reset */
FMC_Bank1->BTCR = 0x00000000;
```
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