SST Elements

https://github.com/sstsimulator/sst-elements
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SST Elements provides a modular and parallel simulation environment for exploring innovations in...
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### Install and Build GPGPU-Sim for SST

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Steps to clone the GPGPU-Sim repository, set the CUDA installation path, source the environment setup script for SST integration, and build GPGPU-Sim.

```shell
# Pull GPGPU-Sim repo
git clone git@github.com:accel-sim/gpgpu-sim_distribution.git
cd gpgpu-sim_distribution

# Make sure $CUDA_INSTALL_PATH is set
echo $CUDA_INSTALL_PATH

# Setup GPGPU-Sim in SST-integration mode
source setup_environment sst

# Build GPGPU-Sim
make -j
```

--------------------------------

### Compile and Install SST

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

These commands compile the SST core with parallel jobs and then install it, preparing the environment for running simulations.

```bash
make -j
make install
```

--------------------------------

### Setup Environment for SST-Elements

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

Instructions for sourcing environment setup scripts for SST-Elements, differentiating between builds with and without PIN, and specifying CUDA and GCC versions. This is crucial for a correct build.

```shell
source sst_env_setup_10_1.sh
# For PIN: CUDA 10.1, gcc 4.9.2
source 10.1_env_setup.sh
# Without PIN: CUDA 10.1, gcc 7.5.0
```

--------------------------------

### Install GPGPU-Sim Dependencies

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Installs essential system dependencies required for building GPGPU-Sim on Ubuntu.

```shell
# GPGPU-Sim dependencies
sudo apt-get install build-essential xutils-dev bison zlib1g-dev flex libglu1-mesa-dev
```

--------------------------------

### Install and Compile CUDA API Tracer

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Instructions to clone the Accel-Sim framework, navigate to the tracer tool directory, install NVBIT, and compile the CUDA API tracer tool.

```shell
# Get the Accel-Sim framework
git clone git@github.com:accel-sim/accel-sim-framework.git

# cd into tracer tool folder
cd accel-sim-framework/util/tracer_nvbit

# Install nvbit
./install_nvbit.sh

# Compile tracer tool
# Which will generate a 'cuda_api_tracer_tool.so' file at
# './others/cuda_api_tracer_tool/cuda_api_tracer'
make -C ./others/cuda_api_tracer_tool
```

--------------------------------

### Source CUDA Environment Setup

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command sources the environment setup script for CUDA, which is necessary for builds that utilize GPU acceleration. It also mentions the prerequisite of building gpgpusim beforehand.

```shell
source SST_EXTERNAL_PATH/setup_environment
```

--------------------------------

### Source SST GPGPU-Sim External Setup Script

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command sources another script to set up the environment for external SST GPGPU-Sim components.

```bash
source ../sst-gpgpusim-external/setup_environment
```

--------------------------------

### Source SST Environment Setup Script

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command sources a script to set up the necessary environment variables for SST and GPGPU-Sim integration.

```bash
source ../env-setup/sst_env_setup.sh
```

--------------------------------

### Setup Environment for GPU Application Collection

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Clones the GPU application collection repository, checks out the `sst_support` branch, and sources the environment setup script. This requires LLVM and RISC-V toolchain paths to be set, and optionally the custom CUDA library path.

```bash
git clone git@github.com:accel-sim/gpu-app-collection.git
cd gpu-app-collection
git checkout sst_support

# Setup environ vars for apps, need to have
# env var LLVM_INSTALL_PATH and RISCV_TOOLCHAIN_INSTALL_PATH
# If you plan to compile the apps directly, you will
# also need to set SST_CUSTOM_CUDA_LIB_PATH to
# the directory of the custom CUDA library,
# which normally will be `SST-ELEMENT-SOURCE/src/sst/elements/balar/tests/vanadisLLVMRISCV`
source ./src/setup_environment sst
```

--------------------------------

### SST Elements Ramulator2 Configuration Examples

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/membackend/ramulator2/Instructions.md

These Python scripts provide example configurations for using Ramulator2 with SST Elements, demonstrating how to set up memory hierarchy tests and specific backend configurations.

```python
import sst

# Example configuration for Ramulator2 with DDR4
mem_backend = sst.Component("membackend", "memHierarchy.MemBackendRamulator2")
mem_backend.addParam("mem_config", "ddr4-ramulator2.cfg")

```

--------------------------------

### Configure SST-Elements Build with PIN and CUDA

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

Configures the SST-Elements build, specifying installation paths for SST-Core, PIN, CUDA, and GPGPU-Sim. This is the standard configuration for a full-featured build.

```shell
./configure --prefix=$SST_ELEMENTS_HOME --with-sst-core=$SST_CORE_HOME --with-pin=$PIN_HOME --with-cuda=$CUDA_INSTALL_PATH --with-gpgpusim=$GPGPUSIM_ROOT
```

--------------------------------

### Configure SST-Core Build

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command configures the build for sst-core, specifying the installation prefix and disabling MPI and memory pools. It's a fundamental step before compiling sst-core.

```shell
./configure --prefix=$SST_CORE_HOME --disable-mpi --disable-mem-pools
```

--------------------------------

### Build LLVM with RISC-V, X86, and CUDA Support

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Builds the LLVM project from source, configuring it to support RISC-V, x86, and NVPTX (CUDA) targets. It installs LLVM, Clang, and LLD to a specified directory.

```bash
## Build LLVM with RISC-V, x86, and CUDA support from source
git clone https://github.com/llvm/llvm-project.git

mkdir llvm-install
cd llvm-project
mkdir build && cd build
cmake -DLLVM_TARGETS_TO_BUILD="RISCV;X86;NVPTX" -DLLVM_DEFAULT_TARGET_TRIPLE=riscv64-unknown-linux-gnu \
      -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_PROJECTS="clang;lld" -DCMAKE_INSTALL_PREFIX=$LLVM_INSTALL_PATH ../llvm
cmake --build . -j30
cmake --build . --target install
cd ..

## Build RISC-V GCC toolchain
git clone https://github.com/riscv-collab/riscv-gnu-toolchain.git

mkdir riscv-gnu-install
cd riscv-gnu-toolchain
./configure --prefix=$RISCV_INSTALL_PATH
make linux -j
cd ..

# Set up environment vars to LLVM and RISCV GCC
export LLVM_INSTALL_PATH=$(pwd)/llvm-install
export RISCV_TOOLCHAIN_INSTALL_PATH=$(pwd)/riscv-gnu-install
# Match with the GPU config file we have
export GPU_ARCH=sm_70
```

--------------------------------

### Configure SST Elements with Ramulator2

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/membackend/ramulator2/Instructions.md

This command configures SST Elements, specifying the path to the Ramulator2 installation using the `--with-ramulator2` flag. This is a crucial step for enabling the Ramulator2 memory backend.

```bash
./configure --with-ramulator2=<path-to-ramulator2> [other options]
```

--------------------------------

### SST MemHierarchy: Four Cores, Distributed Shared LLC

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/examples/README.md

Presents a multi-core setup with four cores, private L1 caches, and a shared Last-Level Cache (LLC) that is distributed across four slices, all connected to a single memory component. This showcases distributed shared cache designs.

```Python
# example-4core-shared-distributed-llc.py : Same as 'example-4core-shared-llc' except that the shared L2 is distributed across 4 slices
```

--------------------------------

### Build and Install Osseous and vecshiftreg

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/osseous/README.md

This snippet outlines the steps to clone the repository, configure the build with SST core and PIN, compile the components, and set up the environment path for execution. It's essential for integrating the Osseous-based components with SST.

```Shell
clone the repository containing osseous

Update other Env variables as part of standard sst-elements build process(SST_ELEMENTS_HOME, SST_CORE_HOME)
cd path/to/sst-elements/
./autogen.sh
./configure --prefix=$SST_ELEMENTS_HOME --with-sst-core=$SST_CORE_HOME --with-pin=$PINHOME
make all
make install
export PATH=$SST_CORE_HOME/bin:$SST_ELEMENTS_HOME/bin:$PATH

cd src/sst/elements/osseous/tests
make all (compiles RTL testbench into executable that is fed to Ariel)
sst runstream.py
```

--------------------------------

### SST MemHierarchy: Single Core, Three Cache Levels

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/examples/README.md

Configures a single-core processor with a three-level cache hierarchy (L1, L2, L3) connected to a memory component. This example illustrates a more complex, multi-level cache system.

```Python
# example-1core-3level.py  : Single core with a three-level cache hierarchy (L1, L2, L3) and one memory
```

--------------------------------

### Create New Feature Branch (Git)

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This snippet details the Git commands and workflow for creating a new branch to implement a new feature. It follows a similar process to bug fixes, starting from the 'devel' branch.

```bash
git checkout devel
git pull origin devel
git checkout -b new-feature
# Make changes and commit
git commit -m "Implement new feature ABC"
git push origin new-feature
```

--------------------------------

### SST MemHierarchy: Four Cores, Shared LLC

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/examples/README.md

Demonstrates a multi-core configuration with four cores, each having private L1 caches, and a shared Last-Level Cache (LLC) connected to a single memory component. This highlights shared cache architectures.

```Python
# example-4core-shared-llc.py : Four cores with private L1s and a shared L2; one memory
```

--------------------------------

### SST MemHierarchy: Single Core, One Cache Level

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/examples/README.md

Sets up a single-core processor with a single level of cache (L1) connected to a memory component. This demonstrates a basic cache-enabled memory hierarchy.

```Python
# example-1core-1level.py  : Single core with one L1 cache and one memory
```

--------------------------------

### SST MemHierarchy: Single Core, No Cache

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/examples/README.md

Configures a single-core processor connected directly to a single memory component, without any cache levels. This serves as a baseline for memory hierarchy simulations.

```Python
# example-1core-nocache.py : Single core connected to a single memory; no caches
```

--------------------------------

### Modify Linker Script Memory Address

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/vanadis/tests/riscv-tests/patch.txt

This snippet illustrates the change in the memory address specified in linker scripts for various RISC-V test environments. The starting address for the .text.init section is updated from 0x80000000 to 0x10000, which is a common adjustment for embedded systems or specific memory layouts.

```linker-script
. = 0x10000;
  .text.init : { *(.text.init) }
```

--------------------------------

### Run Balar Simulation with Vanadis Core

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This snippet demonstrates running the Balar simulation with the Vanadis core, specifying the configuration file.

```bash
sst testBalar-vanadis.py --model-options='-c ariel-gpu-v100.cfg'
```

--------------------------------

### Run Balar Simulation with testCPU

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This snippet shows how to execute the Balar simulation using the testCPU core. It specifies the configuration file and the vectorAdd kernel to be used.

```bash
cd tests/
sst testBalar-testcpu.py --model-options='-c ariel-gpu-v100.cfg -v -x vectorAdd/vectorAdd'
```

--------------------------------

### Run Vanadis Handshake Binary

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command executes a Vanadis handshake binary with specific model options, demonstrating how to run a simulation with custom configurations using the `sst testBalar-vanadis.py` script.

```shell
sst testBalar-vanadis.py --model-options='-c ariel-gpu-v100.cfg'
```

--------------------------------

### Run Simple Balar Test Script

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command executes a simple Balar test script with specified model options and redirects the output to a file for analysis.

```bash
sst testBalar-simple.py --model-options="-c ariel-gpu-v100.cfg -v" > tmp.out 2>&1
```

--------------------------------

### Verify Git Remote and Branch Configuration

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

These Git commands help verify that your local repository is correctly configured to track the official SST-Elements repository and its 'devel' branch.

```git
git remote -vv
git branch -vv
```

--------------------------------

### Balar MMIO Interface for Arguments and Results

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This task involves creating an interface within Balar that utilizes Memory-Mapped I/O (MMIO) to accept arguments and send back results, likely for inter-component communication.

```c++
Create an interface in Balar using MMIO to accept arguments and send results
```

--------------------------------

### Output Graph to DOT and PNG

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This section explains how to output a graph description in DOT format and then convert it to a PNG image using the `dot` command. It's useful for visualizing simulation graphs.

```shell
sst-simulator --output-dot [filename]
dot -Tpng [File.dot] > [File.png]
```

--------------------------------

### Balar Trace-driven Mode: Compile and Run Vanadis Handshake

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This snippet shows how to compile a vanadis handshake binary and a custom CUDA API library. It then demonstrates running the simulation with the vanadis core.

```bash
make -C vanadisHandshake/
sst testBalar-vanadis.py --model-options='-c gpu-v100-mem.cfg'
```

--------------------------------

### Clone SST-Elements Repository

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This snippet shows how to clone your forked SST-Elements repository locally using Git. It assumes you have already created a fork on GitHub.

```git
git clone git@github.com:fryeguy52/sst-elements.git
```

--------------------------------

### Enable GPGPU-Sim Debug Output

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command sets an environment variable to enable detailed debug output from GPGPU-Sim, which can be helpful for troubleshooting.

```bash
export PTX_SIM_DEBUG=3
```

--------------------------------

### Balar Unittest Execution

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This command executes the Balar unittest suites, which automatically compile the GPU app collection with the LLVM and RISCV toolchain and run the tests.

```bash
sst-test-elements -w "*balar*"
```

--------------------------------

### Balar MMIO Packet Handling

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This section discusses placing a packet at a specific MMIO address and passing that address, potentially for communication between the CPU and Balar.

```python
Put the packet at mmio address + 4 location and pass the address to the mmio address
```

--------------------------------

### Balar Trace-driven Mode: Compile and Run Vector Add

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This snippet demonstrates compiling a sample CUDA vector add program and generating a trace file. It then shows how to run the SST simulator in trace-driven mode using the generated trace file.

```bash
cd SST_ELEMENTS_SRC/src/sst/elements/balar
cd tests/
make -C vectorAdd
LD_PRELOAD=PATH/TO/cuda_api_tracer_tool.so ./vectorAdd/vectorAdd
```

```python
sst testBalar-testcpu.py --model-options='-c gpu-v100-mem.cfg -v -x vectorAdd/vectorAdd -t cuda_calls.trace'
```

--------------------------------

### Configure SST-Elements Build without PIN (MMIO Only)

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

Configures the SST-Elements build for MMIO (Memory-Mapped I/O) balancing without PIN, specifying paths for SST-Core, CUDA, and GPGPU-Sim. This is a specialized configuration.

```shell
./configure --prefix=$SST_ELEMENTS_HOME --with-sst-core=$SST_CORE_HOME --with-cuda=$CUDA_INSTALL_PATH --with-gpgpusim=$GPGPUSIM_ROOT
```

--------------------------------

### Create and Push New Feature Branch

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This Git workflow demonstrates creating a new feature branch from 'devel', making changes, committing them, and pushing the new branch to your fork's origin.

```git
git checkout devel
git pull
git checkout -b my-new-feature-branch
git push --set-upstream origin my-new-feature-branch
<making changes ...>
git add <approprite files>
git commit
git push
```

--------------------------------

### Run CUDA API Tracer

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Command to run the CUDA API tracer tool on a CUDA executable, preloading the tracer library. This generates trace files for CUDA API calls and data transfers.

```shell
LD_PRELOAD=PATH/TO/cuda_api_tracer_tool.so CUDA_EXE
```

--------------------------------

### Fetch All Updates and Prune Remote Branches

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This Git command fetches all updates from all remotes and removes any stale remote-tracking references, helping to keep your local repository clean.

```git
git checkout devel
git fetch --all --prune
```

--------------------------------

### Compile CUDA for Balar + Vanadis

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

Explains the need for a custom CUDA library `libcudart_vanadis` for direct-execution mode with Balar and Vanadis. It points to the Makefile for compilation instructions and mentions the required compiler and linker flags.

```bash
# For compiler and linker flags, you can refer to the `vecadd` target in `vanadisLLVMRISCV/Makefile`.
```

--------------------------------

### Balar Vanadis Mode: Compile and Run CPU-only RISCV Program

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This snippet demonstrates compiling RISCV programs using the vanadisLLVMRISCV toolchain and running a CPU-only 'helloworld' program in Vanadis mode.

```bash
cd SST_ELEMENTS_SRC/src/sst/elements/balar/tests/
make -C vanadisLLVMRISCV
VANADIS_EXE=./vanadisLLVMRISCV/helloworld VANADIS_ISA=RISCV64 sst testBalar-vanadis.py --model-options='-c gpu-v100-mem.cfg'
```

--------------------------------

### Set Up Official Repository Tracking

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This sequence of Git commands configures your local repository to track the official SST-Elements 'devel' branch. It involves adding a new remote and setting the upstream branch.

```git
git checkout devel
git remote add sst-official git@github.com:sstsimulator/sst-elements.git
git pull --all
git branch devel --set-upstream-to sst-official/devel
```

--------------------------------

### Balar Response Packet Handling

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This describes how the response packet from Balar should be placed at the same MMIO address where the request packet was sent.

```python
Also the packet response should be put at the same address as well
```

--------------------------------

### Balar GPU Benchmark: Run Rodinia BFS

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This snippet details how to set up and run the Rodinia 2.0 BFS benchmark using CUDA 11.7 with the Balar component. It includes setting environment variables for the custom CUDA library path and the GPU application.

```bash
export SST_CUSTOM_CUDA_LIB_PATH=SST_ELEMENTS_SRC/src/sst/elements/balar/tests/vanadisLLVMRISCV
cd gpu-app-collection
make rodinia_2.0-ft -i -j -C ./src
make data -C ./src
cd ..
cd SST_ELEMENTS_SRC/src/sst/elements/balar/tests
VANADIS_EXE=$GPUAPPS_ROOT/bin/11.7/release/bfs-rodinia-2.0-ft \
VANADIS_EXE_ARGS=$GPUAPPS_ROOT/data_dirs/cuda/rodinia/2.0-ft/bfs-rodinia-2.0-ft/data/SampleGraph.txt \
VANADIS_ISA=RISCV64 \
BALAR_CUDA_EXE_PATH=$GPUAPPS_ROOT/bin/11.7/release/bfs-rodinia-2.0-ft sst \
testBalar-vanadis.py --model-options='-c gpu-v100-mem.cfg'
```

--------------------------------

### Ramulator2 CMakeLists.txt Modification

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/membackend/ramulator2/Instructions.md

This snippet shows how to add the SST frontend source file to Ramulator2's build system by modifying the `CMakeLists.txt` file. It ensures that the SST-specific wrapper is compiled as part of Ramulator2.

```c++
target_sources(ramulator2
    impl/external_wrapper/sst_frontend.cpp
)
```

--------------------------------

### Balar Vanadis Mode: Compile and Run RISCV Vector Add

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/README.md

This snippet shows compiling and running a sample vector add program with RISCV ISA in Vanadis mode, specifying the CUDA executable path.

```bash
cd SST_ELEMENTS_SRC/src/sst/elements/balar/tests/
make -C vanadisLLVMRISCV
VANADIS_EXE=./vanadisLLVMRISCV/vecadd VANADIS_ISA=RISCV64 BALAR_CUDA_EXE_PATH=./vanadisLLVMRISCV/vecadd sst testBalar-vanadis.py --model-options='-c gpu-v100-mem.cfg'
```

--------------------------------

### Create Issue Fix Branch (Git)

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This snippet outlines the Git commands and workflow for creating a new branch to address an issue. It involves forking the repository, creating a new branch from 'devel', committing changes, and opening a pull request.

```bash
git checkout devel
git pull origin devel
git checkout -b issue-fix
# Make changes and commit
git commit -m "Fix for issue #XYZ"
git push origin issue-fix
```

--------------------------------

### Compare Filtered Memory Statistics

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This command uses `git diff` to compare two files (`mmio_mem.out` and `prev_mem.out`) with word-level differences highlighted in color. It's used to analyze changes in memory statistics.

```shell
git diff --word-diff=color --no-index mmio_mem.out prev_mem.out
```

--------------------------------

### Precompute Edge Index Array using embertricount_setup

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/mpi/motifs/README-tricount.txt

The `embertricount_setup` executable precomputes the 'Vertices' array, which is crucial for determining the communication pattern in the triangle counting workload. It takes several arguments including seed, scale, edge ratio, constants A, B, C, and an output filename.

```bash
Usage: <seed> <scale> <edge ratio> <A> <B> <C> <filename>
```

--------------------------------

### Pull Updates from Official Repository

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This command fetches the latest updates from the official SST-Elements 'devel' branch to your local 'devel' branch, assuming the upstream has been set correctly.

```git
git checkout devel
git pull
```

--------------------------------

### Coherence Controller Forwarding Logic

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This code snippet points to the `forwardByAddress` function within the `CoherenceController` class. It suggests that the `linkDown_` member might not be finding the target destination, potentially due to incorrect cache range configuration.

```c++
CoherenceController::forwardByAddress()
```

--------------------------------

### Filter Memory Subsystem Statistics

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

These commands use `grep` to filter specific memory subsystem statistics from the `stats.out` file and a reference file, creating `mmio_mem.out` and `prev_mem.out` for comparison.

```shell
grep -E -e '(l1gcache_.*)|(l2gcache_.*)|(Simplehbm_.*)' stats.out > mmio_mem.out
grep -E -e '(l1gcache_.*)|(l2gcache_.*)|(Simplehbm_.*)' refFiles/test_gpgpu_vectorAdd.out > prev_mem.out
```

--------------------------------

### Synchronize Master Branch with Official Repo

Source: https://github.com/sstsimulator/sst-elements/blob/master/CONTRIBUTING.md

This Git command sets your local 'master' branch to track the official SST-Elements 'master' branch and pulls the latest updates.

```git
git checkout master
git branch master --set-upstream-to sst-official/master
git pull
```

--------------------------------

### Golem: Integrating CrossSim with SST

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/golem/README.md

This section details how to integrate the CrossSim simulator with the Golem SST element. CrossSim is searched for within the PYTHONPATH. It's recommended to use the same Python interpreter for both SST core and CrossSim to ensure compatibility, although different configurations might work if Python versions match.

```Python
import simulator
```

--------------------------------

### Osseous C-Testbench APIs for RTL Simulation

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/osseous/README.md

This section details the User and Supporting APIs within the Osseous testbench (testbench.c). These APIs facilitate the initiation, updating, and management of RTL simulations, including signal updates and parameter configurations.

```C
// User APIs:
// start_RTL_sim(shmem) - To begin RTL simulation and pass the virtual addresses of RTL inputs(shmem) to send it to DUT. Ariel sends an event to DUT (RTL Component) to initiate simulation
// update_RTL_sig(shmem) - To update the RTL input signals while simulation progresses.

// Supporting APIs (Definition in tb_header.c):
// RTL_shmem_info(): mem malloc space to store RTL inputs into memH (intercepted by PIN)
// Update_RTL_params(): Updates RTL params to defaults

// perform_update(upd_inp, upd_ctrl, upd_eval_args, upd_reg, verbose, done_rst, sim_done, sim_cycles): RTL parameters specified as arguments
// bool upd_inp: Update RTL inputs?
// bool upd_ctrl: Update control data?
// bool upd_eval_args: Update eval() API arguments? eval() is primary API of C-model header

// storetomem(): Updates the RTL parameters in memH (stores are intercepted by PIN)
```

--------------------------------

### Enable SST-Core Debug Output

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This configure option enables memory hierarchy debug output in sst-core, which is invaluable for diagnosing issues within the memory subsystem during simulations.

```shell
./configure --enable-debug
```

--------------------------------

### SST Memory Reply Push

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This function is used to push memory reply packets from SST cache to GPGPUSim, a critical step for handling memory requests originating from the GPU.

```c++
SST_pop_mem_reply
```

--------------------------------

### Modify RISCV_PREFIX and Comment RV32 Templates in isa/Makefile

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/vanadis/tests/riscv-tests/patch.txt

This snippet shows the changes made to the `riscv-tests/isa/Makefile`. It includes commenting out the inclusion of RV32-specific Makefrag files and changing the default RISCV_PREFIX from 'riscv$(XLEN)-unknown-elf-' to 'riscv$(XLEN)-linux-'. This affects how RISC-V tests are compiled and linked.

```makefile
--- riscv-tests/isa/Makefile	2023-12-11 14:14:41.862356748 -0700
+++ /home/mjleven/sstGIT/riscv-tests-orig/isa/Makefile	2023-11-29 16:57:39.913422568 -0700
@@ -19,15 +19,15 @@
 include $(src_dir)/rv64mi/Makefrag
 include $(src_dir)/rv64mzicbo/Makefrag
 endif
-include $(src_dir)/rv32ui/Makefrag
-include $(src_dir)/rv32uc/Makefrag
-include $(src_dir)/rv32um/Makefrag
-include $(src_dir)/rv32ua/Makefrag
-include $(src_dir)/rv32uf/Makefrag
-include $(src_dir)/rv32ud/Makefrag
-include $(src_dir)/rv32uzfh/Makefrag
-include $(src_dir)/rv32si/Makefrag
-include $(src_dir)/rv32mi/Makefrag
+##include $(src_dir)/rv32ui/Makefrag
+##include $(src_dir)/rv32uc/Makefrag
+##include $(src_dir)/rv32um/Makefrag
+##include $(src_dir)/rv32ua/Makefrag
+##include $(src_dir)/rv32uf/Makefrag
+##include $(src_dir)/rv32ud/Makefrag
+##include $(src_dir)/rv32uzfh/Makefrag
+##include $(src_dir)/rv32si/Makefrag
+##include $(src_dir)/rv32mi/Makefrag
 
 default: all
 
@@ -35,7 +35,7 @@
 # Build rules
 #--------------------------------------------------------------------
 
-RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
+RISCV_PREFIX ?= riscv$(XLEN)-linux-
 RISCV_GCC ?= $(RISCV_PREFIX)gcc
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
@@ -61,9 +61,9 @@
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_p_tests)
 
-$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
-
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo $$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
-$(1)_tests += $$($(1)_v_tests)
+##$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
+##	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo $$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
+##$(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
 
@@ -79,15 +79,15 @@
 
 endef
 
-$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
-$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
-$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
+##$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
+##$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
 ifeq ($(XLEN),64)
 $(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64))

```

--------------------------------

### Stream Operation in Stream Manager

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This code snippet refers to the `push` function within the `stream_manager` class, specifically when handling `stream_operation` objects. It highlights a potential issue where the function might not wait for stream 0 to be empty, leading to skipped D2H copies.

```c++
void stream_manager::push( stream_operation op )
```

--------------------------------

### SST Memory Reply Reception

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This function is used to receive memory reply packets from SST, which are then pushed to the GPGPU-Sim's instruction count (icnt) for access by the GPU. This is crucial for load and store operations.

```c++
SST_receive_mem_reply()
```

--------------------------------

### Run Tricount Motif in SST

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/mpi/motifs/README-tricount.txt

This Python command adds the Tricount motif to an SST simulation. It specifies the input file ('vertices4.txt') and the debug level for the execution. A sample input file can be found in the test directory.

```python
ep.addMotif("TriCount vertices_filename=vertices4.txt debug_level=1")
```

--------------------------------

### Eval API Arguments for C-model Header

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/osseous/README.md

This describes the arguments for the `_eval` API, a key part of the C-model header. These arguments control aspects of the simulation, such as register updates, verbosity, and the total number of simulation cycles.

```C
// _eval(upd_reg, verbose, done_rst) API Arguments (Part of C-model header):
// bool upd_reg: Update C-model registers?
// bool verbose: Print debug information?
// bool done_rst: NA (Not used)
// bool sim_done: simulation done? ("true" marks end of simulation after specified cycles)
// uint64_t sim_cyles: specifies number of SST cycles RTL C-model should simulate with provided inputs (shmem)

// Eval API arguments are passed along with rest of the RTL inputs to be stored into memH.
```

--------------------------------

### Update Source Directory in Top-Level Makefile

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/vanadis/tests/riscv-tests/patch.txt

This snippet shows the modification in the main `riscv-tests/Makefile`. The `abs_top_src_dir` variable is updated to point to the new location of the RISC-V tests source code, ensuring that the build system correctly references the test files.

```makefile
--- riscv-tests/Makefile	2023-12-11 14:16:45.181795784 -0700
+++ /home/mjleven/sstGIT/riscv-tests-orig/Makefile	2023-10-30 13:27:04.274260797 -0600
@@ -1,5 +1,5 @@
 prefix          := /home/mjleven/tools/target
-abs_top_src_dir := /home/mjleven/sstGIT/sst-elements-mjleven-3/src/sst/elements/vanadis/tests/riscv-tests/riscv-tests
+abs_top_src_dir := /home/mjleven/sstGIT/riscv-tests-orig
 XLEN            := 64
 target_alias    := 
 ifeq ($(target_alias),)

```

--------------------------------

### SST Memory Request Injection

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/devNote.md

This function appears to be responsible for injecting memory request packets from the GPU to the SST simulation environment, likely for cache handling.

```c++
icnt_inject_request_packet_to_SST()
```

--------------------------------

### Adjust RISCV_TEST_CODE_END Macro

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/vanadis/tests/riscv-tests/patch.txt

This snippet shows modifications to the RVTEST_CODE_END macro definition within the riscv_test.h header file. The original macro was defined as 'unimp', and the updated version includes undefining and redefining the RVTEST_CODE_BEGIN and RVTEST_CODE_END macros, likely to handle specific test scenarios or to ensure clean macro states.

```c
#define RVTEST_CODE_END                                                unimp

#undef RVTEST_CODE_BEGIN                                               
#define RVTEST_CODE_BEGIN                                               
#undef RVTEST_CODE_END
#define RVTEST_CODE_END
```

--------------------------------

### Update RISCV_GCC_OPTS in Makefile

Source: https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/vanadis/tests/riscv-tests/patch.txt

This snippet shows the modification of the RISCV_GCC_OPTS variable in the riscv-tests benchmarks Makefile. The change involves updating the March option from 'rv$(XLEN)gcv' to 'rv$(XLEN)gc', potentially affecting the target architecture's instruction set extensions used during compilation.

```makefile
RISCV_PREFIX ?= riscv$(XLEN)-linux-
RISCV_GCC ?= $(RISCV_PREFIX)gcc
RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gc -mabi=lp64d
RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
```
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