### Installing Git LFS for Large File Support

Source: https://github.com/slaclab/surf/blob/main/README.md

This command initializes Git Large File Storage (LFS) for the repository. Git LFS is used to handle large binary files, such as .dcp files, by replacing them with text pointers in Git, while the actual file contents are stored on a remote server. This setup is crucial for managing large files efficiently within the Git repository.

```sh
$ git lfs install
```

--------------------------------

### Building and Uploading Conda Package - Bash

Source: https://github.com/slaclab/surf/blob/main/conda-recipe/README.md

This snippet demonstrates the process of building a conda package from a recipe, activating the conda environment, and then uploading the built package to Anaconda. It specifies channels for dependencies and an output folder for the build artifacts, followed by environment activation and the upload command.

```Bash
$ conda build --debug conda-recipe --output-folder bld-dir -c tidair-packages -c tidair-tag -c conda-forge
$ conda activate
$ anaconda upload bld-dir/linux-64/rogue-.....
```

--------------------------------

### Opening Vivado Design Checkpoint (.dcp) in Bash

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/lvdsUltraScale/ip/README.md

This command initiates the Vivado tool and opens a specified Design Checkpoint (.dcp) file. It is the prerequisite step for performing any modifications or analysis on the design within the Vivado environment.

```bash
vivado surf/ethernet/GigEthCore/lvdsUltraScale/ip/GigEthLvdsUltraScaleCore.dcp
```

--------------------------------

### Enabling Real XVC Debug Bridge in Makefile (Shell)

Source: https://github.com/slaclab/surf/blob/main/xilinx/xvc-udp/README.md

This snippet demonstrates how to set the `USE_XVC_DEBUG` environment variable within an application's Makefile. Setting this variable to `1` instructs the firmware to instantiate and use the 'true' Axis Debug Bridge, providing actual JTAG debugging capabilities, as opposed to the default stub module.

```Shell
export USE_XVC_DEBUG = 1
```

--------------------------------

### Saving Modified Vivado Design Checkpoint in Tcl

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/lvdsUltraScale/ip/README.md

This Tcl command saves the current state of the open Vivado design, including any modifications made, back to the specified Design Checkpoint (.dcp) file. The `-force` option ensures that the existing file is overwritten, persisting the changes for future use.

```tcl
write_checkpoint surf/ethernet/GigEthCore/lvdsUltraScale/ip/GigEthLvdsUltraScaleCore.dcp -force
```

--------------------------------

### Removing Placement Constraints for GTY Channel Primitives (Tcl)

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/gtyUltraScale+/images/README.md

This snippet targets `GTYE4_CHANNEL_PRIM_INST` cells, unfixing their BEL (Block Element) and location constraints, and then explicitly unplacing them. This allows the Vivado placer to re-evaluate and optimize the physical placement of these GTY channel primitives, which is crucial for achieving timing closure and optimal resource utilization.

```Tcl
set_property is_bel_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*]
set_property is_loc_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*]
unplace_cell [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*]
```

--------------------------------

### Removing IO Lock Constraints for GTY Ports (Tcl)

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/gtyUltraScale+/images/README.md

This snippet uses `set_property` to unfix the I/O location constraints for specific GTY transceiver ports (`rxp`, `rxn`, `txp`, `txn`). Setting `is_loc_fixed` to `false` allows the Vivado placer to freely assign their physical locations, which can be useful for optimizing routing or placement.

```Tcl
set_property is_loc_fixed false [get_ports [list  rxp]]
set_property is_loc_fixed false [get_ports [list  rxn]]
set_property is_loc_fixed false [get_ports [list  txp]]
set_property is_loc_fixed false [get_ports [list  txn]]
```

--------------------------------

### Adjusting MMCM Clock Properties for Ultrascale+ in Tcl

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/lvdsUltraScale/ip/README.md

These Tcl commands modify the clocking properties of an MMCM (Mixed-Mode Clock Manager) instance within the opened Vivado design. The adjustments, including `CLKFBOUT_MULT_F` and output divides, are crucial to change the VCO frequency from 625MHz to 1250MHz, ensuring compatibility with Ultrascale+ devices which have a minimum VCO frequency of 800MHz.

```tcl
set_property CLKFBOUT_MULT_F 4.000 [get_cells U0/core_clocking_i/mmcme3_adv_inst]
set_property CLKOUT0_DIVIDE_F 10.000 [get_cells U0/core_clocking_i/mmcme3_adv_inst]
set_property CLKOUT1_DIVIDE 4 [get_cells U0/core_clocking_i/mmcme3_adv_inst]
set_property CLKOUT2_DIVIDE 2 [get_cells U0/core_clocking_i/mmcme3_adv_inst]
```

--------------------------------

### Removing IO Package Pin Constraints for GTY Ports (Tcl)

Source: https://github.com/slaclab/surf/blob/main/ethernet/GigEthCore/gtyUltraScale+/images/README.md

This snippet clears the `package_pin` property for the specified GTY transceiver ports (`rxp`, `rxn`, `txp`, `txn`). By setting the property to an empty string, any fixed pin assignments are removed, enabling the Vivado tool to select appropriate package pins based on design requirements and available resources.

```Tcl
set_property package_pin "" [get_ports [list  rxp]]
set_property package_pin "" [get_ports [list  rxn]]
set_property package_pin "" [get_ports [list  txp]]
set_property package_pin "" [get_ports [list  txn]]
```

=== COMPLETE CONTENT === This response contains all available snippets from this library. No additional content exists. Do not make further requests.