### String Length Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc

An example demonstrating the use of unit-stride fault-only-first instructions for calculating string length.

```assembly
strlen example using unit-stride fault-only-first instruction

include::example/strlen.s[lines=4..-1]
```

--------------------------------

### Vector Register Gather Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example demonstrating `viota.m` and `vrgather.vv` for expanding a vector based on a mask.

```assembly
viota.m v10, v0                 # Calc iota from mask in v0
vrgather.vv v11, v1, v10, v0.t  # Expand into destination
```

--------------------------------

### vsetvli Examples with Different vtype Settings

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Examples demonstrating how to configure SEW and LMUL using the `vsetvli` instruction with different immediate values for `vtypei`.

```assembly
vsetvli t0, a0, e8, m1, ta, ma      # SEW= 8, LMUL=1
vsetvli t0, a0, e8, m2, ta, ma      # SEW= 8, LMUL=2
vsetvli t0, a0, e32, mf2, ta, ma    # SEW=32, LMUL=1/2
```

--------------------------------

### Install GPG on Ubuntu/Debian

Source: https://github.com/riscv/riscv-isa-manual/blob/main/CONTRIBUTING.md

Install GnuPG on Ubuntu or Debian-based systems using apt. This command installs the necessary GPG tools.

```bash
sudo apt-get install gnupg
```

--------------------------------

### Memcpy Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/vector-examples.adoc

An assembly code example for a memcpy operation using vector instructions.

```assembly
include::example/memcpy.s[lines=4..-1]
```

--------------------------------

### Indexed-Unordered Segment Load Example (3-field, 8-bit)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example of loading bytes at addresses `x5+v3[i]`, `x5+v3[i]+1`, and `x5+v3[i]+2` into `v4[i]`, `v5[i]`, and `v6[i]` respectively, using indexed-unordered access.

```assembly
vsetvli a1, t0, e8, m1, ta, ma
vluxseg3ei8.v v4, (x5), v3   # Load bytes at addresses x5+v3[i]   into v4[i],
                                #  and bytes at addresses x5+v3[i]+1 into v5[i],
                                #  and bytes at addresses x5+v3[i]+2 into v6[i].
```

--------------------------------

### Vector-Vector Add Example (int32)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/vector-examples.adoc

Demonstrates a simple vector-vector addition for 32-bit integers.

```assembly
include::example/vvaddint32.s[lines=4..-1]
```

--------------------------------

### PUSH Instruction Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zcmp.adoc

Demonstrates the syntax for the cm.push instruction, specifying registers to push and the immediate offset for stack pointer adjustment.

```asm
cm.push  {ra, s0-s5}, -64
```

--------------------------------

### strlen example using fault-only-first instruction

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

An example demonstrating the use of a unit-stride fault-only-first instruction for string length calculation. Note the security concerns associated with fault-on-first loads.

```assembly
include::example/strlen.s[lines=4..-1]
```

--------------------------------

### Constant-Stride Segment Load Example (3-field, 8-bit)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example of loading bytes at addresses `x5+i*x6`, `x5+i*x6+1`, and `x5+i*x6+2` into `v4[i]`, `v5[i]`, and `v6[i]` respectively.

```assembly
vsetvli a1, t0, e8, m1, ta, ma
vlsseg3e8.v v4, (x5), x6   # Load bytes at addresses x5+i*x6   into v4[i],
                            #  and bytes at addresses x5+i*x6+1 into v5[i],
                            #  and bytes at addresses x5+i*x6+2 into v6[i].
```

--------------------------------

### Build Documentation Locally

Source: https://github.com/riscv/riscv-isa-manual/blob/main/CONTRIBUTING.md

Build the documentation using the local toolchain. This command initiates the default build process.

```bash
make build
```

--------------------------------

### Build Specific Documentation Formats

Source: https://github.com/riscv/riscv-isa-manual/blob/main/CONTRIBUTING.md

Build the documentation in specific formats like PDF, HTML, or EPUB. These commands are useful for generating particular output types.

```bash
make build-pdf
```

```bash
make build-html
```

```bash
make build-epub
```

--------------------------------

### Install GPG on macOS

Source: https://github.com/riscv/riscv-isa-manual/blob/main/CONTRIBUTING.md

Install GnuPG on macOS using Homebrew. This is a prerequisite for signing commits with GPG.

```bash
brew install gnupg
```

--------------------------------

### Build RISC-V Specification PDF (Make)

Source: https://context7.com/riscv/riscv-isa-manual/llms.txt

Make command to build the complete RISC-V specification PDF, including all three volumes. Also provides links to online HTML snapshots and official released PDFs.

```bash
# Build the full specification including all three volumes:
make build-pdf
# Produces: build/riscv-spec.pdf

# Online HTML snapshots (no build required):
# Unprivileged: https://riscv.github.io/riscv-isa-manual/snapshot/spec/#vol:unpriv
# Privileged:   https://riscv.github.io/riscv-isa-manual/snapshot/spec/#vol:priv
# Profiles:     https://riscv.github.io/riscv-isa-manual/snapshot/spec/#vol:profiles

# Official released PDFs (ratified versions):
# https://riscv.org/specifications/
# https://github.com/riscv/riscv-isa-manual/releases/latest
```

--------------------------------

### Synthesizing vdecompress Functionality

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc

This example illustrates how to synthesize the functionality of a 'vdecompress' operation using iota and a masked vrgather, as there is no direct vdecompress instruction.

```assembly
7 6 5 4 3 2 1 0     # vid

      e d c b a     # packed vector of 5 elements
1 0 0 1 1 1 0 1     # mask vector of 8 elements
p q r s t u v w     # destination register before vdecompress

e q r d c b v a     # result of vdecompress
```

--------------------------------

### C Standard Library strcmp Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/vector-examples.adoc

A C standard library function example for string comparison.

```c
#include <string.h>

int main() {
    const char *s1 = "hello";
    const char *s2 = "world";
    int result = strcmp(s1, s2);
    return 0;
}
```

--------------------------------

### Example Use of vcompress.vm

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Demonstrates the vcompress.vm instruction with specific register values and a mask. The result shows elements from v1 packed into v2 according to the mask in v0.

```assembly
                        vsetivli     t0, 9, e8, m1, tu, ma
                        vcompress.vm v2, v1, v0
```

--------------------------------

### Vectorize strncpy Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example demonstrating vectorization of the strncpy function. Ensure the source and destination registers do not overlap.

```assembly
include::example/strncpy.s[lines=4..-1]
```

--------------------------------

### Vectorize strcpy Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example demonstrating vectorization of the strcpy function. Ensure the source and destination registers do not overlap.

```assembly
include::example/strcpy.s[lines=4..-1]
```

--------------------------------

### Square Root Approximation Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/vector-examples.adoc

Placeholder for an assembly code example demonstrating square root approximation using vector instructions.

```assembly

```

--------------------------------

### Build and Check Commands (Makefile)

Source: https://context7.com/riscv/riscv-isa-manual/llms.txt

Commands for cloning the repository, pulling the Docker container, building documentation in various formats, checking cross-references, and cleaning build artifacts. Use `RELEASE_TYPE` for draft, intermediate, or official builds.

```bash
# Clone with submodules (required — docs-resources is a submodule)
git clone --recurse-submodules https://github.com/riscv/riscv-isa-manual.git
cd riscv-isa-manual

# Pull the official build container
docker pull ghcr.io/riscv/riscv-docs-base-container-image:latest

# Build everything: PDF + HTML + EPUB + normative tags JSON/HTML + cross-ref check
make build

# Build only PDF
make build-pdf

# Build only HTML
make build-html

# Build only EPUB
make build-epub

# Build normative rules JSON and HTML reports
make build-norm-rules

# Build with an official release stamp (no watermark, sets revnumber to today)
make build RELEASE_TYPE=official

# Build with a specific date stamp
make build RELEASE_TYPE=official DATE=20250508

# Check for broken cross-references (exits non-zero on invalid xref)
make check-xrefs

# Validate that normative tag names haven't changed unexpectedly vs. ref/ snapshots
make check-tags

# Regenerate ref/ snapshots after intentional tag changes
make update-ref

# Clean all build artifacts
make clean
```

--------------------------------

### Initialize Submodules

Source: https://github.com/riscv/riscv-isa-manual/blob/main/CONTRIBUTING.md

Update and initialize submodules if the repository has already been cloned. Run this command to ensure all submodule content is present.

```bash
git submodule update --init --recursive
```

--------------------------------

### Vector Register Move Specific Examples

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Specific examples of `vmv<nr>r.v` instructions for copying different numbers of vector registers.

```assembly
vmv1r.v v1, v2   #  Copy v1=v2
```

```assembly
vmv2r.v v10, v12 #  Copy v10=v12; v11=v13
```

```assembly
vmv4r.v v4, v8   #  Copy v4=v8; v5=v9; v6=v10; v7=v11
```

```assembly
vmv8r.v v0, v8   #  Copy v0=v8; v1=v9; ...;  v7=v15
```

--------------------------------

### Unit-Stride Segment Load Example (8-bit)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example of loading eight vector registers with eight byte fields using unit-stride segment load.

```assembly
vlseg8e8.v vd, (rs1), vm   # Load eight vector registers with eight byte fields.
```

--------------------------------

### Build Normative Rules Documentation (Make)

Source: https://context7.com/riscv/riscv-isa-manual/llms.txt

Make commands to generate machine-readable JSON and human-readable HTML reports for normative rules, and to check tag consistency.

```bash
# Generate machine-readable JSON of all normative rules:
make build-norm-rules-json
# Output: build/norm-rules.json

# Generate human-readable HTML normative rules report:
make build-norm-rules-html
# Output: build/norm-rules.html

# Check that tags haven't changed vs. committed snapshots in ref/:
make check-tags

# Update ref/ snapshots after intentional tag changes:
make update-ref
```

--------------------------------

### Constant-Stride Segment Store Example (2-field, 32-bit)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example of storing words from `v2[i]` to address `x5+i*x6` and words from `v3[i]` to address `x5+i*x6+4`.

```assembly
vsetvli a1, t0, e32, m1, ta, ma
vssseg2e32.v v2, (x5), x6   # Store words from v2[i] to address x5+i*x6
                            #   and words from v3[i] to address x5+i*x6+4
```

--------------------------------

### Standard Instructions for Pseudoinstructions

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/priv/pages/hypervisor.adoc

Illustrates the encoding of standard load and store instructions that correspond to special pseudoinstructions used in hypervisor contexts. These are typically used for memory access emulation.

```assembly
0x00002003
0x00002023
```

```assembly
lw x0,0(x0)
sw x0,0(x0)
```

```assembly
0x00003003
0x00003023
```

```assembly
ld x0,0(x0)
sd x0,0(x0)
```

--------------------------------

### Hypervisor Load/Store Instructions

Source: https://context7.com/riscv/riscv-isa-manual/llms.txt

Assembly instructions for hypervisor memory access. These include loading and storing words/doublewords from/to guest virtual addresses, and specialized loads for instruction fetching.

```assembly
hlv.w   t0, (a0)               # load  32-bit word from guest virtual address a0
```

```assembly
hlv.d   t0, (a0)               # load  64-bit dword (RV64)
```

```assembly
hlvx.wu t0, (a0)               # load  32-bit word as if executing (for fetch)
```

```assembly
hsv.w   t0, (a0)               # store 32-bit word to guest virtual address a0
```

--------------------------------

### Unit-Stride Segment Store Example (3-field, 32-bit)

Source: https://github.com/riscv/riscv-isa-manual/blob/main/modules/unpriv/pages/v-st-ext.adoc

Example of storing a packed vector of 3*4-byte segments from `vs3`, `vs3+1`, `vs3+2` to memory using unit-stride segment store.

```assembly
vsseg3e32.v vs3, (rs1), vm  # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory
```

--------------------------------

### RISC-V System Instructions

Source: https://context7.com/riscv/riscv-isa-manual/llms.txt

Instructions for environment calls, breakpoints, and memory ordering.

```asm
ecall                       # environment call (syscall / SBI call)
ebreak                      # breakpoint trap
fence iorw, iorw            # memory ordering: predecessor=IORW, successor=IORW
```

--------------------------------

### Division Approximation Example

Source: https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/vector-examples.adoc

Demonstrates an iterative method to approximate division (v1 / v2) to nearly 23 bits of precision using reciprocal estimates.

```assembly
# v1 = v1 / v2 to almost 23 bits of precision.

vfrec7.v v3, v2             # Estimate 1/v2
  li t0, 0x3f800000
vmv.v.x v4, t0              # Splat 1.0
vfnmsac.vv v4, v2, v3       # 1.0 - v2 * est(1/v2)
vfmadd.vv v3, v4, v3        # Better estimate of 1/v2
vmv.v.x v4, t0              # Splat 1.0
vfnmsac.vv v4, v2, v3       # 1.0 - v2 * est(1/v2)
vfmadd.vv v3, v4, v3        # Better estimate of 1/v2
vfmul.vv v1, v1, v3         # Estimate of v1/v2

```