### Spike GDB Debugging Setup and Example Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Steps and code examples for debugging a RISC-V program using spike with GDB and OpenOCD. ```APIDOC 1. Compile the C program: ```bash $ cat rot13.c char text[] = "Vafgehpgvba frgf jnag gb or serr!"; // Don't use the stack, because sp isn't set up. volatile int wait = 1; int main() { while (wait) ; // Doesn't actually go on the stack, because there are lots of GPRs. int i = 0; while (text[i]) { char lower = text[i] | 32; if (lower >= 'a' && lower <= 'm') text[i] += 13; else if (lower > 'm' && lower <= 'z') text[i] -= 13; i++; } done: while (!wait) ; } ``` 2. Create a linker script: ```bash $ cat spike.lds OUTPUT_ARCH( "riscv" ) SECTIONS { . = 0x10110000; .text : { *(.text) } .data : { *(.data) } } ``` 3. Compile and link the program: ```bash $ riscv64-unknown-elf-gcc -g -Og -o rot13-64.o -c rot13.c $ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64.o ``` 4. Run spike, listening for a remote bitbang connection: ```bash $ spike --rbb-port=9824 -m0x10100000:0x20000 rot13-64 Listening for remote bitbang connection on port 9824. ``` 5. Configure and run OpenOCD: ```bash $ cat spike.cfg adapter driver remote_bitbang remote_bitbang host localhost remote_bitbang port 9824 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME gdb_report_data_abort enable init halt ``` ```bash $ openocd -f spike.cfg Open On-Chip Debugger 0.10.0-dev-00002-gc3b344d (2017-06-08-12:14) ... riscv.cpu: target state: halted ``` 6. Start the GDB session: ```bash $ riscv64-unknown-elf-gdb rot13-64 GNU gdb (GDB) 8.0.50.20170724-git ... (gdb) target remote localhost:3333 Remote debugging using localhost:3333 0x0000000010010004 in main () at rot13.c:8 8 while (wait) (gdb) print wait $1 = 1 (gdb) print wait=0 $2 = 0 (gdb) print text $3 = "Vafgehpgvba frgf jnag gb or serr!" (gdb) b done Breakpoint 1 at 0x10110064: file rot13.c, line 22. (gdb) c Continuing. Disabling abstract command writes to CSRs. Breakpoint 1, main () at rot13.c:23 23 while (!wait) (gdb) print wait $4 = 0 (gdb) print text ... ``` ``` -------------------------------- ### Build Spike Simulator Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Instructions for building the Spike RISC-V ISA Simulator on a Linux system. This includes installing dependencies, configuring the build, and installing the simulator. ```bash $ apt-get install device-tree-compiler libboost-regex-dev libboost-system-dev $ mkdir build $ cd build $ ../configure --prefix=$RISCV $ make $ [sudo] make install ``` -------------------------------- ### Build Spike Simulator on OpenBSD Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Instructions for building the Spike RISC-V ISA Simulator on OpenBSD. This involves installing necessary packages, setting environment variables, and using gmake for the build process. ```bash $ pkg_add bash gmake dtc $ exec bash $ export CC=cc; export CXX=c++ $ mkdir build $ cd build $ ../configure --prefix=$RISCV $ gmake $ [doas] make install ``` -------------------------------- ### Add a New Instruction to Spike Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Guide on how to add a new custom instruction to the Spike RISC-V ISA Simulator. This involves defining the instruction's behavior in a header file and updating the opcode definitions. ```bash 1. Describe the instruction's functional behavior in the file riscv/insns/.h. Examine other instructions in that directory as a starting point. 2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively, add it to the riscv-opcodes package, and it will do so for you: ``` $ cd ../riscv-opcodes $ vi opcodes // add a line for the new instruction $ make install ``` ``` -------------------------------- ### Compile and Run a C Program with Spike Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Steps to compile a C program for RISC-V and simulate it using Spike and the riscv-pk proxy kernel. This involves using the RISC-V GCC toolchain and executing the simulation. ```bash $ riscv64-unknown-elf-gcc -o hello hello.c $ spike pk hello ``` -------------------------------- ### Clone and Configure Spike for RISC-V Arch Tests Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/README.md Steps to clone the RISC-V architectural test framework and copy the Spike configuration file. This involves modifying the Makefile.include to point to the Spike target directory. ```bash git clone https://github.com/riscv/riscv-arch-test.git cd riscv-arch-test cp /riscv-isa-sim/arch_test_target/spike/Makefile.include . ``` -------------------------------- ### Execute RISC-V Architectural Tests with Spike Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/README.md Commands to compile, simulate, and verify RISC-V architectural tests using the configured Spike target. ```makefile make compile simulate verify ``` -------------------------------- ### Spike Interactive Debug Mode Commands Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/README.md Commands for interacting with the spike simulator in debug mode. Allows inspection of registers, memory, and controlling program execution. ```APIDOC : reg - Displays the content of an integer register. - Example: : reg 0 a0 : fregs - Displays the content of a floating-point register (single-precision). - Example: : fregs 0 ft0 : fregd - Displays the content of a floating-point register (double-precision). - Example: : fregd 0 ft0 : mem
- Displays the content of memory at a physical address (hex). - Example: : mem 2020 : mem
- Displays the content of memory at a virtual address. - Example: : mem 0 2020 - Advances execution by one instruction. : until - Executes until a specified condition is met. - Examples: - : until pc 0 2020 (stop when pc=2020) - : until reg 0 mie a (stop when register mie=0xa) - : until mem 2020 50a9907311096993 (stop when mem[2020]=50a9907311096993) : while - Executes as long as a specified condition is true. - Example: : while mem 2020 50a9907311096993 : r - Continues execution indefinitely. - - Enters interactive debug mode or exits the simulation from the debug prompt. : q - Ends the simulation from the debug prompt. ``` -------------------------------- ### riscv-isa-sim Runtime and Debug Features Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/ChangeLog.md This section details runtime and debug-related features and changes in the riscv-isa-sim project, including support for vectored interrupts, dynamic linking, privilege mode control, and various command-line options for debugging. ```APIDOC Version 1.0.1-dev: - Support S-mode vectored interrupts (i.e. `stvec[0]` is now writable). - Added support for dynamic linking of libraries containing MMIO devices. - Added `--priv` flag to control which privilege modes are available. - When the commit log is enabled at configure time (`--enable-commitlog`), it must also be enabled at runtime with the `--log-commits` option. - Several debug-related additions and changes: - Added `hasel` debug feature. - Added `--dm-no-abstract-csr` command-line option. - Added `--dm-no-halt-groups` command line option. - Renamed `--progsize` to `--dm-progsize`. - Renamed `--debug-sba` to `--dm-sba`. - Renamed `--debug-auth` to `--dm-auth`. - Renamed `--abstract-rti` to `--dm-abstract-rti`. - Renamed `--without-hasel` to `--dm-no-hasel`. ``` -------------------------------- ### RISC-V ISA Extensions Support Source: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/ChangeLog.md This entry summarizes the support for various RISC-V Instruction Set Architecture (ISA) extensions across different versions of the riscv-isa-sim project. It includes scalar cryptography extensions, virtual entropy, Vector (V), and others. ```APIDOC Version 1.1.0: - Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0 - Zkr virtual entropy source emulation, v1.0 - V extension, v1.0 - P extension, v0.9.2 - Zba extension, v1.0 - Zbb extension, v1.0 - Zbc extension, v1.0 - Zbs extension, v1.0 - Hypervisor extension, v1.0 - Svnapot extension, v1.0 - Svpbmt extension, v1.0 - Svinval extension, v1.0 Version 1.0.1-dev: - Preliminary support for a subset of the Vector Extension, v0.7.1. Version 1.0.0 (2019-03-30): - First versioned release. ``` === COMPLETE CONTENT === This response contains all available snippets from this library. No additional content exists. Do not make further requests.