### Widening Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of widening instruction intrinsics with operand mnemonics encoded for distinction.

```APIDOC
## Widening Instructions

### Description
Widening instruction intrinsics (e.g. `vwadd`) have the same return type but different types of arguments. The operand mnemonics are encoded into their overloaded versions to help distinguish them.

### Code Examples

```c
vint32m1_t __riscv_vwadd_vv(vint16mf2_t vs2, vint16mf2_t vs1, size_t vl);
vint32m1_t __riscv_vwadd_vx(vint16mf2_t vs2, int16_t rs1, size_t vl);
vint32m1_t __riscv_vwadd_wv(vint32m1_t vs2, vint16mf2_t vs1, size_t vl);
vint32m1_t __riscv_vwadd_wx(vint32m1_t vs2, int16_t rs1, size_t vl);
```
```

--------------------------------

### Vector Unsigned Addition with Saturation (vasubu)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/overloaded_intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

The `__riscv_vasubu` intrinsic performs unsigned addition with saturation on vector elements. It supports various vector types (e.g., `vuint16m1_t`, `vuint32m1_t`, `vuint64m1_t`) and can operate with either a vector or a scalar second operand. The `vm` argument is a mask, `vs2` is the first source vector, `vs1` or `rs1` is the second source operand, `vxrm` specifies the rounding mode, and `vl` is the vector length.

```APIDOC
## __riscv_vasubu

Performs unsigned addition with saturation on vector elements.

### Function Signatures:

* `vuint16m1_t __riscv_vasubu(vbool16_t vm, vuint16m1_t vs2, vuint16m1_t vs1, unsigned int vxrm, size_t vl);`
* `vuint16m1_t __riscv_vasubu(vbool16_t vm, vuint16m1_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl);`
* `vuint16m2_t __riscv_vasubu(vbool8_t vm, vuint16m2_t vs2, vuint16m2_t vs1, unsigned int vxrm, size_t vl);`
* `vuint16m2_t __riscv_vasubu(vbool8_t vm, vuint16m2_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl);`
* `vuint16m4_t __riscv_vasubu(vbool4_t vm, vuint16m4_t vs2, vuint16m4_t vs1, unsigned int vxrm, size_t vl);`
* `vuint16m4_t __riscv_vasubu(vbool4_t vm, vuint16m4_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl);`
* `vuint16m8_t __riscv_vasubu(vbool2_t vm, vuint16m8_t vs2, vuint16m8_t vs1, unsigned int vxrm, size_t vl);`
* `vuint16m8_t __riscv_vasubu(vbool2_t vm, vuint16m8_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl);`
* `vuint32mf2_t __riscv_vasubu(vbool64_t vm, vuint32mf2_t vs2, vuint32mf2_t vs1, unsigned int vxrm, size_t vl);`
* `vuint32mf2_t __riscv_vasubu(vbool64_t vm, vuint32mf2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);`
* `vuint32m1_t __riscv_vasubu(vbool32_t vm, vuint32m1_t vs2, vuint32m1_t vs1, unsigned int vxrm, size_t vl);`
* `vuint32m1_t __riscv_vasubu(vbool32_t vm, vuint32m1_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);`
* `vuint32m2_t __riscv_vasubu(vbool16_t vm, vuint32m2_t vs2, vuint32m2_t vs1, unsigned int vxrm, size_t vl);`
* `vuint32m2_t __riscv_vasubu(vbool16_t vm, vuint32m2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);`
* `vuint32m4_t __riscv_vasubu(vbool8_t vm, vuint32m4_t vs2, vuint32m4_t vs1, unsigned int vxrm, size_t vl);`
* `vuint32m4_t __riscv_vasubu(vbool8_t vm, vuint32m4_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);`
* `vuint32m8_t __riscv_vasubu(vbool4_t vm, vuint32m8_t vs2, vuint32m8_t vs1, unsigned int vxrm, size_t vl);`
* `vuint32m8_t __riscv_vasubu(vbool4_t vm, vuint32m8_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);`
* `vuint64m1_t __riscv_vasubu(vbool64_t vm, vuint64m1_t vs2, vuint64m1_t vs1, unsigned int vxrm, size_t vl);`
* `vuint64m1_t __riscv_vasubu(vbool64_t vm, vuint64m1_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);`
* `vuint64m2_t __riscv_vasubu(vbool32_t vm, vuint64m2_t vs2, vuint64m2_t vs1, unsigned int vxrm, size_t vl);`
* `vuint64m2_t __riscv_vasubu(vbool32_t vm, vuint64m2_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);`
* `vuint64m4_t __riscv_vasubu(vbool16_t vm, vuint64m4_t vs2, vuint64m4_t vs1, unsigned int vxrm, size_t vl);`
* `vuint64m4_t __riscv_vasubu(vbool16_t vm, vuint64m4_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);`
* `vuint64m8_t __riscv_vasubu(vbool8_t vm, vuint64m8_t vs2, vuint64m8_t vs1, unsigned int vxrm, size_t vl);`
* `vuint64m8_t __riscv_vasubu(vbool8_t vm, vuint64m8_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);`

### Parameters:

* `vm` (vboolX_t): Mask to control which elements are operated on.
* `vs2` (vuintXmY_t): The first source vector.
* `vs1` (vuintXmY_t or uintX_t): The second source operand (vector or scalar).
* `vxrm` (unsigned int): The rounding mode.
* `vl` (size_t): The vector length.

### Description:

Performs element-wise unsigned addition of `vs2` and `vs1` (or `rs1`). If the result exceeds the maximum representable value for the element type, it saturates. The operation is controlled by the mask `vm` and the rounding mode `vxrm`. The `vl` parameter specifies the number of elements to process.
```

--------------------------------

### Narrowing BF16/FP32 to OFP8 Type-Convert Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of narrowing BF16/FP32 to OFP8 type-convert instructions.

```APIDOC
## Narrowing BF16/FP32 to OFP8 Type-Convert Instructions

### Code Examples

```c
vfloat8e4m3mf8_t __riscv_vfncvt_f_f8e4m3(vbfloat16mf4_t vs2, size_t vl);
vfloat8e4m3mf8_t __riscv_vfncvt_sat_f_f8e4m3(vbfloat16mf4_t vs2, size_t vl);
vfloat8e5m2mf8_t __riscv_vfncvt_f_f8e5m2(vbfloat16mf4_t vs2, size_t vl);
vfloat8e5m2mf8_t __riscv_vfncvt_sat_f_f8e5m2(vbfloat16mf4_t vs2, size_t vl);
```
```

--------------------------------

### Unsigned Addition with Saturation (VASUBU)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/policy_funcs/overloaded_intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

These intrinsics perform unsigned addition with saturation. They support various vector element widths (8, 16, 32 bits) and different vector lengths (mf2, m1, m2, m4, m8). The saturation ensures that the result does not exceed the maximum representable value for the given unsigned integer type. The `vxrm` parameter specifies the rounding mode, and `vl` specifies the vector length.

```APIDOC
## __riscv_vasubu_mu

### Description
Performs unsigned addition with saturation on vector elements. The operation saturates at the maximum representable value for the unsigned integer type.

### Function Signatures

**For 8-bit elements:**
- `vuint8mf2_t __riscv_vasubu_mu(vbool16_t vm, vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint8mf2_t __riscv_vasubu_mu(vbool16_t vm, vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, unsigned int vxrm, size_t vl)`
- `vuint8m1_t __riscv_vasubu_mu(vbool8_t vm, vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint8m1_t __riscv_vasubu_mu(vbool8_t vm, vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, unsigned int vxrm, size_t vl)`
- `vuint8m2_t __riscv_vasubu_mu(vbool4_t vm, vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint8m2_t __riscv_vasubu_mu(vbool4_t vm, vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, unsigned int vxrm, size_t vl)`
- `vuint8m4_t __riscv_vasubu_mu(vbool2_t vm, vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint8m4_t __riscv_vasubu_mu(vbool2_t vm, vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, unsigned int vxrm, size_t vl)`
- `vuint8m8_t __riscv_vasubu_mu(vbool1_t vm, vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint8m8_t __riscv_vasubu_mu(vbool1_t vm, vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, unsigned int vxrm, size_t vl)`

**For 16-bit elements:**
- `vuint16mf4_t __riscv_vasubu_mu(vbool64_t vm, vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16mf4_t __riscv_vasubu_mu(vbool64_t vm, vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16mf2_t __riscv_vasubu_mu(vbool32_t vm, vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16mf2_t __riscv_vasubu_mu(vbool32_t vm, vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m1_t __riscv_vasubu_mu(vbool16_t vm, vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m1_t __riscv_vasubu_mu(vbool16_t vm, vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m2_t __riscv_vasubu_mu(vbool8_t vm, vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m2_t __riscv_vasubu_mu(vbool8_t vm, vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m4_t __riscv_vasubu_mu(vbool4_t vm, vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m4_t __riscv_vasubu_mu(vbool4_t vm, vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m8_t __riscv_vasubu_mu(vbool2_t vm, vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m8_t __riscv_vasubu_mu(vbool2_t vm, vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`

**For 32-bit elements:**
- `vuint32mf2_t __riscv_vasubu_mu(vbool64_t vm, vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32mf2_t __riscv_vasubu_mu(vbool64_t vm, vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m1_t __riscv_vasubu_mu(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m1_t __riscv_vasubu_mu(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m2_t __riscv_vasubu_mu(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m2_t __riscv_vasubu_mu(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m4_t __riscv_vasubu_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m4_t __riscv_vasubu_mu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m8_t __riscv_vasubu_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m8_t __riscv_vasubu_mu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`

### Parameters

- **vm** (vboolX_t): Mask vector. Elements are activated according to the mask.
- **vd** (vuintXmY_t): Destination vector register.
- **vs2** (vuintXmY_t): The first source vector register.
- **vs1** (vuintXmY_t or scalar type): The second source vector register or scalar value.
- **vxrm** (unsigned int): The rounding mode. Must be one of `__RISCV_VXRM_RN`, `__RISCV_VXRM_RD`, `__RISCV_VXRM_RU`, `__RISCV_VXRM_RZ`.
- **vl** (size_t): The vector length.

### Return Value

A vector of the same type as `vd` containing the results of the saturation addition.

### Example

```c
// Example for 8-bit unsigned addition with saturation
size_t vl = 16;
vuint8m1_t vd, vs2, vs1;
// ... initialize vd, vs2, vs1 ...
vuint8m1_t result = __riscv_vasubu_mu(vm, vd, vs2, vs1, __RISCV_VXRM_RN, vl);
```
```

--------------------------------

### Widening OFP8 to BF16 Type-Convert Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of widening OFP8 to BF16 type-convert instructions.

```APIDOC
## Widening OFP8 to BF16 Type-Convert Instructions

### Code Examples

```c
vbfloat16mf4_t __riscv_vfwcvt_f_bf16(vfloat8e4m3mf8_t vs2, size_t vl);
vbfloat16mf4_t __riscv_vfwcvt_f_bf16(vfloat8e5m2mf8_t vs2, size_t vl);
```
```

--------------------------------

### Vector Addition (VV and VX)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/intrinsic_funcs/02_vector_integer_arithmetic_intrinsics.adoc

These functions perform element-wise addition. `__riscv_vadd_vv` adds two vectors, while `__riscv_vadd_vx` adds a scalar to each element of a vector. They support various unsigned integer types and vector lengths.

```APIDOC
## Vector Addition (VV and VX)

These functions perform element-wise addition. `__riscv_vadd_vv` adds two vectors, while `__riscv_vadd_vx` adds a scalar to each element of a vector.

### `vuint8mf8_t __riscv_vadd_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl);`
### `vuint8mf8_t __riscv_vadd_vx_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl);`
### `vuint8mf4_t __riscv_vadd_vv_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl);`
### `vuint8mf4_t __riscv_vadd_vx_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl);`
### `vuint8mf2_t __riscv_vadd_vv_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl);`
### `vuint8mf2_t __riscv_vadd_vx_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl);`
### `vuint8m1_t __riscv_vadd_vv_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl);`
### `vuint8m1_t __riscv_vadd_vx_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl);`
### `vuint8m2_t __riscv_vadd_vv_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl);`
### `vuint8m2_t __riscv_vadd_vx_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl);`
### `vuint8m4_t __riscv_vadd_vv_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl);`
### `vuint8m4_t __riscv_vadd_vx_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl);`
### `vuint8m8_t __riscv_vadd_vv_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl);`
### `vuint8m8_t __riscv_vadd_vx_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl);`
### `vuint16mf4_t __riscv_vadd_vv_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl);`
### `vuint16mf4_t __riscv_vadd_vx_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl);`
### `vuint16mf2_t __riscv_vadd_vv_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl);`
### `vuint16mf2_t __riscv_vadd_vx_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl);`
```

--------------------------------

### Type-convert Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of type-convert instruction intrinsics, showing how suffixes distinguish different conversion types.

```APIDOC
## Type-convert Instructions

### Description
Type-convert instruction intrinsics (e.g. `vfcvt.x.f`, `vfcvt.xu.f`, `vfcvt.rtz.xu.f`) encode the returning type mnemonics into their overloaded variants to help distinguish them.

The following shows how `_x`, `_rtz_x`, `_xu`, and `_rtz_xu` are appended to the suffix for distinction.

### Code Examples

```c
vint32m1_t __riscv_vfcvt_x (vfloat32m1_t src, size_t vl);
vint32m1_t __riscv_vfcvt_rtz_x (vfloat32m1_t src, size_t vl);
vuint32m1_t __riscv_vfcvt_xu (vfloat32m1_t src, size_t vl);
vuint32m1_t __riscv_vfcvt_rtz_xu (vfloat32m1_t src, size_t vl);
```
```

--------------------------------

### Vector Unsigned Addition with Saturate and Masked Operations (vasubu_tumu)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/policy_funcs/overloaded_intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

These functions perform vector unsigned addition with saturation, supporting various data types (uint16, uint32, uint64) and vector lengths (mf4, mf2, m1, m2, m4, m8). They also support masked operations where applicable.

```APIDOC
## Vector Unsigned Addition with Saturate and Masked Operations (vasubu_tumu)

These functions perform vector unsigned addition with saturation. They support different data types and vector lengths, and can operate under a mask.

### Function Signatures

- `vuint16mf4_t __riscv_vasubu_tumu(vbool64_t vm, vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16mf2_t __riscv_vasubu_tumu(vbool32_t vm, vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16mf2_t __riscv_vasubu_tumu(vbool32_t vm, vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m1_t __riscv_vasubu_tumu(vbool16_t vm, vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m1_t __riscv_vasubu_tumu(vbool16_t vm, vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m2_t __riscv_vasubu_tumu(vbool8_t vm, vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m2_t __riscv_vasubu_tumu(vbool8_t vm, vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m4_t __riscv_vasubu_tumu(vbool4_t vm, vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m4_t __riscv_vasubu_tumu(vbool4_t vm, vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint16m8_t __riscv_vasubu_tumu(vbool2_t vm, vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint16m8_t __riscv_vasubu_tumu(vbool2_t vm, vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32mf2_t __riscv_vasubu_tumu(vbool64_t vm, vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32mf2_t __riscv_vasubu_tumu(vbool64_t vm, vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m1_t __riscv_vasubu_tumu(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m1_t __riscv_vasubu_tumu(vbool32_t vm, vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m2_t __riscv_vasubu_tumu(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m2_t __riscv_vasubu_tumu(vbool16_t vm, vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m4_t __riscv_vasubu_tumu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m4_t __riscv_vasubu_tumu(vbool8_t vm, vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint32m8_t __riscv_vasubu_tumu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint32m8_t __riscv_vasubu_tumu(vbool4_t vm, vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl)`
- `vuint64m1_t __riscv_vasubu_tumu(vbool64_t vm, vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, unsigned int vxrm, size_t vl)`
- `vuint64m1_t __riscv_vasubu_tumu(vbool64_t vm, vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl)`
- `vuint64m2_t __riscv_vasubu_tumu(vbool32_t vm, vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, unsigned int vxrm, size_t vl)`
- `vuint64m2_t __riscv_vasubu_tumu(vbool32_t vm, vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl)`
- `vuint64m4_t __riscv_vasubu_tumu(vbool16_t vm, vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, unsigned int vxrm, size_t vl)`
- `vuint64m4_t __riscv_vasubu_tumu(vbool16_t vm, vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl)`
- `vuint64m8_t __riscv_vasubu_tumu(vbool8_t vm, vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, unsigned int vxrm, size_t vl)`
- `vuint64m8_t __riscv_vasubu_tumu(vbool8_t vm, vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl)`

### Parameters

- `vm` (vboolX_t): Mask vector. Elements are activated based on this mask.
- `vd` (vuintXXmY_t): Destination vector. The result of the addition is stored here.
- `vs2` (vuintXXmY_t): The first source vector operand.
- `vs1` (vuintXXmY_t or uintXX_t): The second source operand. Can be a vector or a scalar.
- `vxrm` (unsigned int): The rounding mode for saturation.
- `vl` (size_t): The vector length.

### Description

Performs element-wise unsigned addition of `vs2` and `vs1`, saturating the result to the maximum representable value if overflow occurs. The operation is performed under the control of the mask `vm`. If `vs1` is a scalar, it is broadcast to all elements of the vector. The `vxrm` parameter specifies the rounding mode for saturation.
```

--------------------------------

### Unsigned Addition with Saturation (VX)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

Performs unsigned addition on a vector operand and a scalar operand with saturation. The `vxrm` parameter specifies the rounding mode, and `vl` determines the vector length.

```c
vuint32m1_t __riscv_vasubu_vx_u32m1_m(vbool32_t vm, vuint32m1_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);
vuint32m2_t __riscv_vasubu_vx_u32m2_m(vbool16_t vm, vuint32m2_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);
vuint32m4_t __riscv_vasubu_vx_u32m4_m(vbool8_t vm, vuint32m4_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);
vuint32m8_t __riscv_vasubu_vx_u32m8_m(vbool4_t vm, vuint32m8_t vs2, uint32_t rs1, unsigned int vxrm, size_t vl);
vuint64m1_t __riscv_vasubu_vx_u64m1_m(vbool64_t vm, vuint64m1_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);
vuint64m2_t __riscv_vasubu_vx_u64m2_m(vbool32_t vm, vuint64m2_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);
vuint64m4_t __riscv_vasubu_vx_u64m4_m(vbool16_t vm, vuint64m4_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);
vuint64m8_t __riscv_vasubu_vx_u64m8_m(vbool8_t vm, vuint64m8_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);
```

--------------------------------

### Narrowing BFloat Type-Convert Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of narrowing BFloat type-convert instructions, using the `_bf16` suffix for disambiguation.

```APIDOC
## Narrowing BFloat Type-Convert Instructions

### Description
Add `_bf16` suffix to disambiguate between `zvfhmin` instructions, e.g. `vfloat16mf4_t __riscv_vfncvt_f(vfloat32mf2_t vs2, size_t vl);`.

### Code Examples

```c
vbfloat16mf4_t __riscv_vfncvt_f_bf16(vfloat32mf2_t vs2, size_t vl);
vbfloat16mf4_t __riscv_vfncvt_rod_f_bf16(vfloat32mf2_t vs2, size_t vl);
```
```

--------------------------------

### Vector Unsigned Addition with Saturation (TUM)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/policy_funcs/intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

Performs unsigned addition with saturation for vector elements. Use `vasubu_vv` for vector-vector operations and `vasubu_vx` for vector-scalar operations. The `vxrm` argument specifies the rounding mode.

```c
vuint64m8_t __riscv_vasubu_vv_u64m8_tum(vbool8_t vm, vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, unsigned int vxrm, size_t vl);
vuint64m8_t __riscv_vasubu_vx_u64m8_tum(vbool8_t vm, vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, unsigned int vxrm, size_t vl);
```

--------------------------------

### Widening BFloat Type-Convert Instructions

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of widening BFloat type-convert instructions, using the `_bf16` suffix for disambiguation.

```APIDOC
## Widening BFloat Type-Convert Instructions

### Description
Add `_bf16` suffix to disambiguate between `zvfhmin` instructions, e.g. `vfloat16mf4_t __riscv_vfwcvt_f(vint8mf8_t vs2, size_t vl);`.

### Code Examples

```c
vbfloat16mf4_t __riscv_vfwcvt_f_bf16(vint8mf8_t vs2, size_t vl);
```
```

--------------------------------

### `vreinterpret`, LMUL truncate/extension, and `vset`/`vget`

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc

Examples of `vreinterpret` pseudo-intrinsics that encode the return type into their overloaded variants for distinction.

```APIDOC
## `vreinterpret`, LMUL truncate/extension, and `vset`/`vget`

### Description
These pseudo intrinsics encode the return type (e.g. `__riscv_vreinterpret_b8`) into their overloaded variants to help distinguish them.

The following shows how the return type is appended to the suffix for distinction.

### Code Examples

```c
vfloat32m1_t __riscv_vreinterpret_f32m1 (vint32m1_t src);
vuint32m1_t __riscv_vreinterpret_u32m1 (vint32m1_t src);
vint8m1_t __riscv_vreinterpret_i8m1 (vint32m1_t src);
vint16m1_t __riscv_vreinterpret_i16m1 (vint32m1_t src);
vint64m1_t __riscv_vreinterpret_i64m1 (vint32m1_t src);
vbool64_t __riscv_vreinterpret_b64 (vint32m1_t src);
vbool32_t __riscv_vreinterpret_b32 (vint32m1_t src);
vbool16_t __riscv_vreinterpret_b16 (vint32m1_t src);
vbool8_t __riscv_vreinterpret_b8 (vint32m1_t src);
vbool4_t __riscv_vreinterpret_b4 (vint32m1_t src);
```
```

--------------------------------

### Unsigned Addition with Saturation (Vector-Scalar)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/intrinsic_funcs/03_vector_fixed-point_arithmetic_intrinsics.adoc

These functions perform unsigned addition with saturation on vector elements, where one operand is a scalar. They take a mask, a source vector, a scalar value, a rounding mode, and a vector length as input, returning the saturated result vector.

```APIDOC
## `__riscv_vasubu_vx` Intrinsics

Performs unsigned addition with saturation on vector elements. The operation is performed element-wise between the vector `vs2` and the scalar `rs1`.

### Parameters

- `vm` (vboolX_t): Mask vector. Elements are activated based on this mask.
- `vs2` (vuintXmY_t): The source vector.
- `rs1` (uintX_t): The source scalar value.
- `vxrm` (unsigned int): The rounding mode. (Not directly used in saturation, but part of the signature).
- `vl` (size_t): The vector length.

### Return Value

- `vuintXmY_t`: The destination vector containing the saturated results.

### Examples

```c
vuint8mf8_t result = __riscv_vasubu_vx_u8mf8_m(vm, vs2, rs1, vxrm, vl);
vuint16mf4_t result = __riscv_vasubu_vx_u16mf4_m(vm, vs2, rs1, vxrm, vl);
vuint32mf2_t result = __riscv_vasubu_vx_u32mf2_m(vm, vs2, rs1, vxrm, vl);
// ... and so on for other types and lengths
```
```

--------------------------------

### Vector AES Key Expansion (vaeskf2_vi)

Source: https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/blob/main/auto-generated/vector-crypto/intrinsic_funcs/03_zvkned_-_nist_suite:_vector_aes_block_cipher.adoc

Performs AES key expansion for a vector of 32-bit unsigned integers. Supports different vector lengths (m1, m2, m4, m8).

```APIDOC
## vaeskf2_vi - Vector AES Key Expansion

### Description
Performs the AES key expansion round for a vector of 32-bit unsigned integers.

### Function Signature
```c
vuint32m1_t __riscv_vaeskf2_vi_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t uimm, size_t vl);
vuint32m2_t __riscv_vaeskf2_vi_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t uimm, size_t vl);
vuint32m4_t __riscv_vaeskf2_vi_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t uimm, size_t vl);
vuint32m8_t __riscv_vaeskf2_vi_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t uimm, size_t vl);
```

### Parameters
* `vd` (vuint32mX_t): Destination vector register.
* `vs2` (vuint32mX_t): Source vector register containing the key material.
* `uimm` (size_t): An unsigned immediate value used in the key expansion process.
* `vl` (size_t): The vector length.
```