### RTX5 Level 1 Migration: Application Main Thread Example Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_MigrationGuide.txt Example C code demonstrating how to structure the main function for CMSIS-RTOS v1 compatibility with RTX5. It includes system initialization, kernel setup, thread creation, and scheduler start. ```c #include "RTE_Components.h" #include CMSIS_device_header /* Renamed main() function */ void app_main (void const *argument) { // contents of old "main" } osThreadDef(app_main, osPriorityNormal, 1, 0); int main (void) { // System Initialization SystemCoreClockUpdate(); // ... osKernelInitialize(); osThreadCreate(osThread(app_main), NULL); osKernelStart(); for (;;); } ``` -------------------------------- ### Cortex-A9 Startup File Example Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Template.txt An example of a tool-chain specific startup file for an Armv7-A processor like Cortex-A9. This file handles exception vectors, the reset handler, and stack pointer setup. It's part of the CMSIS (Cortex Microcontroller Software Interface Standard). ```c /* ========================== * STARTUP FILE * ========================== */ #include "Device.h" #ifdef __STARTUP_CLEAR_BSS /* This is a special flag to clear the BSS section. * It is defined in the startup file for the toolchain and * is used in the linker script. */ #define CLEAR_BSS #endif #ifndef __NO_SYSTEM_INIT /* * The SystemInit function is called from startup code. * You can add your own code to it. */ extern void SystemInit (void); #endif /* ========================== * DEFAULT STACK * ========================== */ /* stack init */ /* ========================== * WEAK DEFINITIONS * ========================== */ __attribute__ ((weak)) void Default_Handler(void) { while(1); } /* ========================== * VECTOR TABLE * ========================== */ /* The vector table is an array of uint32_t. * The first entry is the stack pointer, * the second entry is the reset handler. */ __attribute__ ((section(".vectors"))) const uint32_t Vectors[] = { (uint32_t) &__StackTop, /* Top of Stack */ (uint32_t) Reset_Handler, /* Reset Handler */ (uint32_t) NMI_Handler, /* NMI Handler */ (uint32_t) HardFault_Handler, /* Hard Fault Handler */ (uint32_t) MemManage_Handler, /* MPU Fault Handler */ (uint32_t) BusFault_Handler, /* Bus Fault Handler */ (uint32_t) UsageFault_Handler,/* Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ (uint32_t) SVC_Handler, /* SVCall Handler */ (uint32_t) DebugMon_Handler, /* Debug Monitor Handler */ 0, /* Reserved */ (uint32_t) PendSV_Handler, /* PendSV Handler */ (uint32_t) SysTick_Handler, /* SysTick Handler */ /* Interrupts */ (uint32_t) WDT_IRQHandler, /* Watchdog Timer */ (uint32_t) TIMER0_IRQHandler, /* Timer 0 */ (uint32_t) TIMER1_IRQHandler, /* Timer 1 */ (uint32_t) TIMER2_IRQHandler, /* Timer 2 */ (uint32_t) TIMER3_IRQHandler, /* Timer 3 */ (uint32_t) PWM0_IRQHandler, /* PWM 0 */ (uint32_t) PWM1_IRQHandler, /* PWM 1 */ (uint32_t) PWM2_IRQHandler, /* PWM 2 */ (uint32_t) PWM3_IRQHandler, /* PWM 3 */ (uint32_t) PWM4_IRQHandler, /* PWM 4 */ (uint32_t) PWM5_IRQHandler, /* PWM 5 */ (uint32_t) PWM6_IRQHandler, /* PWM 6 */ (uint32_t) PWM7_IRQHandler, /* PWM 7 */ (uint32_t) DMA0_IRQHandler, /* DMA 0 */ (uint32_t) DMA1_IRQHandler, /* DMA 1 */ (uint32_t) DMA2_IRQHandler, /* DMA 2 */ (uint32_t) DMA3_IRQHandler, /* DMA 3 */ (uint32_t) DMA4_IRQHandler, /* DMA 4 */ (uint32_t) DMA5_IRQHandler, /* DMA 5 */ (uint32_t) DMA6_IRQHandler, /* DMA 6 */ (uint32_t) DMA7_IRQHandler, /* DMA 7 */ (uint32_t) DMA8_IRQHandler, /* DMA 8 */ (uint32_t) DMA9_IRQHandler, /* DMA 9 */ (uint32_t) DMA10_IRQHandler, /* DMA 10 */ (uint32_t) DMA11_IRQHandler, /* DMA 11 */ (uint32_t) DMA12_IRQHandler, /* DMA 12 */ (uint32_t) DMA13_IRQHandler, /* DMA 13 */ (uint32_t) DMA14_IRQHandler, /* DMA 14 */ (uint32_t) DMA15_IRQHandler, /* DMA 15 */ (uint32_t) DMA16_IRQHandler, /* DMA 16 */ (uint32_t) DMA17_IRQHandler, /* DMA 17 */ (uint32_t) DMA18_IRQHandler, /* DMA 18 */ (uint32_t) DMA19_IRQHandler, /* DMA 19 */ (uint32_t) DMA20_IRQHandler, /* DMA 20 */ (uint32_t) DMA21_IRQHandler, /* DMA 21 */ (uint32_t) DMA22_IRQHandler, /* DMA 22 */ (uint32_t) DMA23_IRQHandler, /* DMA 23 */ (uint32_t) DMA24_IRQHandler, /* DMA 24 */ (uint32_t) DMA25_IRQHandler, /* DMA 25 */ (uint32_t) DMA26_IRQHandler, /* DMA 26 */ (uint32_t) DMA27_IRQHandler, /* DMA 27 */ (uint32_t) DMA28_IRQHandler, /* DMA 28 */ (uint32_t) DMA29_IRQHandler, /* DMA 29 */ (uint32_t) DMA30_IRQHandler, /* DMA 30 */ (uint32_t) DMA31_IRQHandler, /* DMA 31 */ (uint32_t) CCAN_IRQHandler, /* CCAN */ (uint32_t) CLK_CTRL_IRQHandler, /* CLK_CTRL */ (uint32_t) PWR_CTRL_IRQHandler, /* PWR_CTRL */ (uint32_t) UART0_IRQHandler, /* UART0 */ (uint32_t) UART1_IRQHandler, /* UART1 */ (uint32_t) UART2_IRQHandler, /* UART2 */ (uint32_t) UART3_IRQHandler, /* UART3 */ (uint32_t) UART4_IRQHandler, /* UART4 */ (uint32_t) UART5_IRQHandler, /* UART5 */ (uint32_t) UART6_IRQHandler, /* UART6 */ (uint32_t) UART7_IRQHandler, /* UART7 */ (uint32_t) SPI0_IRQHandler, /* SPI0 */ (uint32_t) SPI1_IRQHandler, /* SPI1 */ (uint32_t) SPI2_IRQHandler, /* SPI2 */ (uint32_t) SPI3_IRQHandler, /* SPI3 */ (uint32_t) SPI4_IRQHandler, /* SPI4 */ (uint32_t) SPI5_IRQHandler, /* SPI5 */ (uint32_t) SPI6_IRQHandler, /* SPI6 */ (uint32_t) SPI7_IRQHandler, /* SPI7 */ (uint32_t) I2C0_IRQHandler, /* I2C0 */ (uint32_t) I2C1_IRQHandler, /* I2C1 */ (uint32_t) I2C2_IRQHandler, /* I2C2 */ (uint32_t) I2C3_IRQHandler, /* I2C3 */ (uint32_t) I2C4_IRQHandler, /* I2C4 */ (uint32_t) I2C5_IRQHandler, /* I2C5 */ (uint32_t) I2C6_IRQHandler, /* I2C6 */ (uint32_t) I2C7_IRQHandler, /* I2C7 */ (uint32_t) USB_IRQHandler, /* USB */ (uint32_t) SDIO_IRQHandler, /* SDIO */ (uint32_t) LCD_IRQHandler, /* LCD */ (uint32_t) ETH_IRQHandler, /* ETH */ (uint32_t) CSI_IRQHandler, /* CSI */ (uint32_t) AES_IRQHandler, /* AES */ (uint32_t) SHA_IRQHandler, /* SHA */ (uint32_t) TRNG_IRQHandler, /* TRNG */ (uint32_t) CRC_IRQHandler, /* CRC */ (uint32_t) SDRAM_IRQHandler, /* SDRAM */ (uint32_t) DMA_MEM_TO_PERIPH_IRQHandler, /* DMA_MEM_TO_PERIPH */ (uint32_t) DMA_PERIPH_TO_MEM_IRQHandler, /* DMA_PERIPH_TO_MEM */ (uint32_t) DMA_MEM_TO_MEM_IRQHandler, /* DMA_MEM_TO_MEM */ (uint32_t) DMA_SDIO_IRQHandler, /* DMA_SDIO */ (uint32_t) DMA_AES_IRQHandler, /* DMA_AES */ (uint32_t) DMA_SHA_IRQHandler, /* DMA_SHA */ (uint32_t) DMA_TRNG_IRQHandler, /* DMA_TRNG */ (uint32_t) DMA_CRC_IRQHandler, /* DMA_CRC */ (uint32_t) DMA_USB_IRQHandler, /* DMA_USB */ (uint32_t) DMA_SDIO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM */ (uint32_t) DMA_SDIO_MEM_TO_SDIO_IRQHandler, /* DMA_SDIO_MEM_TO_SDIO */ (uint32_t) DMA_SDIO_PERIPH_TO_SDIO_IRQHandler, /* DMA_SDIO_PERIPH_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_SDIO_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_SDIO */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_MEM_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_PERIPH_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_SDIO_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_SDIO_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_SDIO_TO_SDIO_TO_PERIPH */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_SDIO_TO_MEM_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM_IRQHandler, /* DMA_SDIO_SDIO_TO_MEM_TO_PERIPH_TO_MEM_TO_MEM_TO_MEM */ (uint32_t) DMA_SDIO_SDIO_TO_PERIPH_TO_PERIPH_TO_MEM_ ``` -------------------------------- ### Initialize and Start RTOS Kernel (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt This code example illustrates the essential steps for initializing and starting the RTOS kernel. It involves calling osKernelInitialize() to set up the kernel, configuring peripherals and creating RTOS objects, and finally calling osKernelStart() to begin thread execution. This is a fundamental pattern for any RTOS-based application. ```c int main (void) { osKernelInitialize (); // initialize CMSIS-RTOS // initialize peripherals here // create 'thread' functions that start executing, // example: tid_name = osThreadCreate (osThread(name), NULL); osKernelStart (); // start thread execution } ``` -------------------------------- ### Middleware SPI Initialization Example (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Driver/src/General.txt Demonstrates how to initialize middleware components by passing a specific SPI driver instance, such as Driver_SPI1 or Driver_SPI2, to a middleware setup function. This allows the middleware to communicate via the selected SPI interface. ```c void init_middleware (ARM_DRIVER_SPI *Drv_spi) ... \ inside the middleware the SPI driver functions are called with: \ Drv_spi->function (...); init_middleware (&Driver_SPI1); // connect middleware to SPI1 interface : init_middleware (&Driver_SPI2); // connect middleware to SPI2 interface ``` -------------------------------- ### Shared I/O Pins Example Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Driver/src/General.txt Demonstrates how different CMSIS-Drivers can share the same I/O pins by following the start and stop sequences for each driver independently. This example shows sequential usage of SPI1 and USART1. ```c SPI1drv->Initialize (...); // Start SPI1 SPI1drv->PowerControl (ARM_POWER_FULL); ... // Do operations with SPI1 SPI1drv->PowerControl (ARM_POWER_OFF); // Stop SPI1 SPI1drv->Uninitialize (); ... USART1drv->Initialize (...); // Start USART1 USART1drv->PowerControl (ARM_POWER_FULL); ... // Do operations with USART1 USART1drv->PowerControl (ARM_POWER_OFF); // Stop USART1 USART1drv->Uninitialize (); ``` -------------------------------- ### Example: Build and Run GCC, Cortex-M3, Low Optimization (Bash) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/CoreValidation/README.md An example demonstrating the build and run command for a specific configuration: GCC compiler, Cortex-M3 device, and low optimization level. Shows the expected output during the process. ```bash CMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c GCC -d CM3 -o low build run [GCC][Cortex-M3][low](build:csolution) csolution convert -s Validation.csolution.yml -c Validation.GCC_low+CM3 [GCC][Cortex-M3][low](build:csolution) csolution succeeded with exit code 0 [GCC][Cortex-M3][low](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj [GCC][Cortex-M3][low](build:cbuild) cbuild succeeded with exit code 0 [GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf [GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0 Matrix Summary ============== compiler device optimize build clean extract run ---------- --------- ---------- ------- ------- --------- ----- GCC Cortex-M3 low success (skip) (skip) 35/35 ``` -------------------------------- ### Create a Simple Thread - C Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Thread.txt Demonstrates the creation of a basic thread using default settings for attributes and memory allocation. It initializes the RTOS kernel, creates the thread, and then starts the kernel. This is a fundamental example for thread instantiation. ```c __NO_RETURN void thread1 (void *argument) { // ... for (;;) {} } int main (void) { osKernelInitialize(); ; osThreadNew(thread1, NULL, NULL); // Create thread with default settings ; osKernelStart(); } ``` -------------------------------- ### CMSIS-RTOS Message Queue Example (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Message.txt Demonstrates the creation and usage of a message queue in CMSIS-RTOS. It shows how to create a queue, spawn threads that put and get messages, and handle potential errors. This example is suitable for embedded systems using the CMSIS-RTOS API. ```c #include "cmsis_os2.h" // CMSIS RTOS header file /*----------------------------------------------------------------------------* * Message Queue creation & usage *---------------------------------------------------------------------------*/ #define MSGQUEUE_OBJECTS 16 // number of Message Queue Objects typedef struct { // object data type uint8_t Buf[32]; uint8_t Idx; } MSGQUEUE_OBJ_t; osMessageQueueId_t mid_MsgQueue; // message queue id osThreadId_t tid_Thread_MsgQueue1; // thread id 1 osThreadId_t tid_Thread_MsgQueue2; // thread id 2 void Thread_MsgQueue1 (void *argument); // thread function 1 void Thread_MsgQueue2 (void *argument); // thread function 2 int Init_MsgQueue (void) { mid_MsgQueue = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(MSGQUEUE_OBJ_t), NULL); if (mid_MsgQueue == NULL) { ; // Message Queue object not created, handle failure } tid_Thread_MsgQueue1 = osThreadNew(Thread_MsgQueue1, NULL, NULL); if (tid_Thread_MsgQueue1 == NULL) { return(-1); } tid_Thread_MsgQueue2 = osThreadNew(Thread_MsgQueue2, NULL, NULL); if (tid_Thread_MsgQueue2 == NULL) { return(-1); } return(0); } void Thread_MsgQueue1 (void *argument) { MSGQUEUE_OBJ_t msg; while (1) { ; // Insert thread code here... msg.Buf[0] = 0x55U; // do some work... msg.Idx = 0U; osMessageQueuePut(mid_MsgQueue, &msg, 0U, 0U); osThreadYield(); // suspend thread } } void Thread_MsgQueue2 (void *argument) { MSGQUEUE_OBJ_t msg; osStatus_t status; while (1) { ; // Insert thread code here... status = osMessageQueueGet(mid_MsgQueue, &msg, NULL, 0U); // wait for message if (status == osOK) { ; // process data } } } ``` -------------------------------- ### CMSIS-RTOS Thread Creation and Kernel Management (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS/src/cmsis_os.txt This C code example demonstrates the fundamental usage of the CMSIS-RTOS API. It includes defining multiple threads with different priorities, creating these threads, initializing the RTOS kernel, and starting its execution. It highlights the use of 'osDelay' for thread pausing and 'osThreadCreate' for thread instantiation. ```c #include "cmsis_os.h" // CMSIS-RTOS header file void job1 (void const *argument) { // thread function 'job1' while (1) { : // execute some code osDelay (10); // delay execution for 10 milliseconds } } osThreadDef(job1, osPriorityAboveNormal, 1, 0); // define job1 as thread function void job2 (void const *argument) { // thread function 'job2' osThreadCreate(osThread(job1),NULL); // create job1 thread while (1) { : // execute some code } } osThreadDef(job2, osPriorityNormal, 1, 0); // define job2 as thread function void job3 (void const *argument) { // thread function 'job3' while (1) { : // execute some code osDelay (20); // delay execution for 20 milliseconds } } osThreadDef(job3, osPriorityNormal, 1, 0); // define job3 as thread function int main (void) { // program execution starts here osKernelInitialize (); // initialize RTOS kernel : // setup and initialize peripherals osThreadCreate (osThread(job2)); osThreadCreate (osThread(job3)); osKernelStart (); // start kernel with job2 execution } ``` -------------------------------- ### Initialize and Start RTOS Kernel (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Kernel.txt Demonstrates how to initialize and start the RTOS kernel. It first checks if the kernel is inactive using osKernelGetState, then initializes it with osKernelInitialize if necessary. Finally, it starts the kernel execution with osKernelStart if the kernel is ready. ```c int main (void) { // System Initialization SystemCoreClockUpdate(); // ... if(osKernelGetState() == osKernelInactive) { // Is the kernel initialized? osKernelInitialize(); // Initialize CMSIS-RTOS kernel } ; // ... Start Threads if (osKernelGetState() == osKernelReady) { // If kernel is ready to run... osKernelStart(); // ... start thread execution } while(1); // only reached in case of error } ``` -------------------------------- ### System Initialization and Clock Configuration Example (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt This code example demonstrates the usage of SystemCoreClock variable and the SystemInit and SystemCoreClockUpdate functions. It shows how to retrieve the current system core clock, update it after potential changes, and store the new value. This is crucial for systems with variable clock speeds. ```c #include "ARMCA9.h" uint32_t coreClock_1 = 0; /* Variables to store core clock values */ uint32_t coreClock_2 = 0; int main (void) { coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */ SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */ coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */ if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */ // Error Handling } while(1); } ``` -------------------------------- ### Interrupt Number Definition Example (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core/src/Template.txt Provides an example of defining interrupt request (IRQn) numbers for a device, including Cortex-M processor exceptions and device-specific interrupts. This is essential for interrupt handling in embedded systems. ```c typedef enum IRQn { /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SVC Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 PendSV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ /****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/ WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */ ``` -------------------------------- ### Configure SAU Address Regions (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core/src/Template.txt This C code example illustrates the configuration of Security Attribution Unit (SAU) address regions. It defines the maximum number of regions, and for each region, specifies whether to initialize it, its start and end addresses, and its Non-Secure Callable (NSC) attribute. These settings are essential for defining memory protection and access control in embedded systems. ```c #define SAU_REGIONS_MAX 8 #define SAU_INIT_REGION0 1 #define SAU_INIT_START0 0x00000000 #define SAU_INIT_END0 0x001FFFE0 #define SAU_INIT_NSC0 1 #define SAU_INIT_REGION1 1 #define SAU_INIT_START1 0x00200000 #define SAU_INIT_END1 0x003FFFE0 #define SAU_INIT_NSC1 0 #define SAU_INIT_REGION2 1 #define SAU_INIT_START2 0x20200000 #define SAU_INIT_END2 0x203FFFE0 #define SAU_INIT_NSC2 0 #define SAU_INIT_REGION3 1 #define SAU_INIT_START3 0x40000000 #define SAU_INIT_END3 0x40040000 #define SAU_INIT_NSC3 0 #define SAU_INIT_REGION4 0 #define SAU_INIT_START4 0x00000000 #define SAU_INIT_END4 0x00000000 #define SAU_INIT_NSC4 0 #define SAU_INIT_REGION5 0 #define SAU_INIT_START5 0x00000000 #define SAU_INIT_END5 0x00000000 #define SAU_INIT_NSC5 0 #define SAU_INIT_REGION6 0 #define SAU_INIT_START6 0x00000000 #define SAU_INIT_END6 0x00000000 #define SAU_INIT_NSC6 0 #define SAU_INIT_REGION7 0 #define SAU_INIT_START7 0x00000000 ``` -------------------------------- ### OS2 Migration Guide Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Migration.txt Provides an overview and guides for migrating from the older API version 1 to the newer API version 2. ```APIDOC ## Migration from API v1 to API v2 To use the API version 2 functions follow the steps described in: - Steps to migrate from API version 1 to API version 2 - List of function differences ``` -------------------------------- ### Thread Management with RTOS API v1 and v2 Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_MigrationGuide.txt Demonstrates the coexistence of threads created with both RTOS API v1 and v2. It includes examples of thread creation, signal waiting, and event flag manipulation. This snippet is crucial for understanding dual API usage within the same application. ```c /*---------------------------------------------------------------------------- * Thread 4 'phaseD': Phase D output - API v2 thread *---------------------------------------------------------------------------*/ void phaseD (void *argument) { for (;;) { osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever); /* wait for an event flag 0x0001 */ Switch_On (LED_D); signal_func(tid_phaseA); /* call common signal function */ Switch_Off(LED_D); } } /*---------------------------------------------------------------------------- * Thread 5 'clock': Signal Clock - API v1 thread *---------------------------------------------------------------------------*/ void clock (void const *argument) { for (;;) { osSignalWait(0x0100, osWaitForever); /* Wait for event send by API v2 function osThreadFlagsSet() */ Switch_On (LED_CLK); osDelay(80); /* delay ticks */ Switch_Off(LED_CLK); } } /* Define the API v1 thread */ osThreadDef(clock, osPriorityNormal, 1, 0); /*---------------------------------------------------------------------------- * Main: Initialize and start RTX Kernel *---------------------------------------------------------------------------*/ void app_main (void *argument) { ; //... /* Create the API v2 thread */ tid_phaseD = osThreadNew(phaseD, NULL, NULL); /* Create the API v1 thread */ tid_clock = osThreadCreate(osThread(clock), NULL); osThreadFlagsSet(tid_phaseA, 0x0001); /* set signal to phaseA thread */ osDelay(osWaitForever); while(1); } ``` -------------------------------- ### C Doxygen API Documentation Example Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/How2Doc.txt Example of a C header file demonstrating Doxygen-style comments for documenting API functions. It includes descriptions for initialization, status retrieval, data read/write operations, error handling, and specific device data retrieval for USB HID classes. ```c /// \brief Called during \ref USBD_Initialize to initialize the USB Device class. /// \return none extern void USBD_HIDn_Initialize (void); // ==== USB Host Human Interface Device Functions ==== /// \brief Get status of the Human Interface Device. /// \param[in] index instance index of HID. /// \return true device is configured and initialized. /// \return false device not ready. extern bool USBH_HID_GetStatus (uint8_t index); /// \brief Read data received from Human Interface Device. /// \param[in] index instance index of HID. /// \param[out] ptr_data data to be read. /// \return value >= 0 number of bytes read. /// \return value -1 communication error. extern int USBH_HID_Read (uint8_t index, uint8_t *ptr_data); /// \brief Write data to Human Interface Device. /// \param[in] index instance index of HID. /// \param[in] ptr_data data to be written. /// \param[in] data_len number of data bytes to be written. /// \return number of bytes written. extern int USBH_HID_Write (uint8_t index, uint8_t *ptr_data, uint16_t data_len); /// \brief Get last error that happened on the Human Interface Device. /// \param[in] index instance index of HID. /// \return error code. extern uint32_t USBH_HID_GetLastError (uint8_t index); /// \brief Retrieve state change since last call of HID Mouse. /// \param[in] index instance index of HID. /// \param[out] button pointer to variable that receives button state. /// \param[out] x pointer to variable that receives x position change. /// \param[out] y pointer to variable that receives y position change. /// \param[out] wheel pointer to variable that receives wheel change. /// \return true state change since last call. /// \return false no state change since last call. extern bool USBH_HID_GetMouseData (uint8_t index, uint8_t *button, int8_t *x, int8_t *y, int8_t *wheel); // ==== USB Device Human Interface Device Functions ==== #ifdef __DOXYGEN__ // following functions are available for each instance of a HID class. // generic prefix USBD_HIDn is USBD_HID0 for HID class instance 0. /// \brief Prepare HID report data to be sent. /// \param[in] rtype Report type /// - HID_REPORT_INPUT = Input report requested. /// - HID_REPORT_FEATURE = Feature report requested. /// \param[in] rid Report ID (0 if only one report exists) ``` -------------------------------- ### RTX Kernel Initialization and Startup Sequence Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt Provides the recommended order for initializing hardware and starting the RTX kernel within the main function. It emphasizes initializing hardware, setting the system core clock, initializing the kernel, optionally creating a main thread, and finally starting the scheduler. ```c // Initialization and configuration of hardware // Update the system core clock osKernelInitialize(); // Initialize the CMSIS-RTOS kernel // Optionally, create one thread osKernelStart (); // Start the RTOS scheduler ``` -------------------------------- ### Install Python Requirements (Bash) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/CoreValidation/README.md Installs the necessary Python packages for the build script. This is a prerequisite for running the validation tests. ```bash CMSIS_5/CMSIS/CoreValidation/Project $ pip install -r requirements.txt ``` -------------------------------- ### Basic CMSIS Example for STM32F10x Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core/src/Using.txt A fundamental example demonstrating the use of the CMSIS layer on an STM32F10x device. It includes necessary headers, a millisecond tick counter, and the SysTick interrupt handler for timing. ```c #include // File name depends on device used uint32_t volatile msTicks; // Counter for millisecond Interval void SysTick_Handler (void) { // SysTick Interrupt Handler msTicks++; // Increment Counter } void WaitForTick (void) { uint32_t curTicks; curTicks = msTicks; // Save Current SysTick Value while (msTicks == curTicks) { // Wait for next SysTick Interrupt ``` -------------------------------- ### IRQ Controller API Usage Example (C) Source: https://github.com/phil496/uv-k5-firmware-custom/blob/main/external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt Demonstrates how to initialize the interrupt controller, register a custom interrupt handler, configure interrupt properties (priority, mode, trigger), enable, trigger, and disable an interrupt. This example uses ARM Cortex-M specific concepts and functions. ```c void SGI0_Handler() { /* * Handle Interrupt */ IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn); } void main() { /* Initialize the Interrupt Controller */ IRQ_Initialize(); /* Register the user defined handler function */ IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler); /* Set the priority considering the priority grouping */ const uint32_t subprio = IRQ_GetPriorityGroupBits(); IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio); /* Set interrupt mode to falling edge */ IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING); IRQ_Enable((IRQn_ID_t)SGI0_IRQn); /* Trigger interrupt */ IRQ_SetPending((IRQn_ID_t)SGI0_IRQn); IRQ_Disable((IRQn_ID_t)SGI0_IRQn); } ```