### Programmatic OpenVAF Compilation using Rust

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

This Rust code showcases programmatic compilation of OpenVAF models using the `openvaf` crate. It includes examples for configuring compilation options such as input/output paths, defines, optimization levels, and target specifications. The code demonstrates handling successful compilation and compilation failures with diagnostics, and also includes an example utilizing a cache for faster recompilation.

```rust
use openvaf::{compile, CompilationDestination, CompilationTermination, Opts, OptLevel};
use camino::Utf8PathBuf;
use target::spec::Target;

fn compile_model() -> anyhow::Result<()> {
    // Configure compilation options
    let opts = Opts {
        dry_run: false,
        defines: vec!["TEMPERATURE=300".to_string()],
        codegen_opts: vec![],
        lints: vec![],
        input: Utf8PathBuf::from("bjt.va"),
        output: CompilationDestination::Path {
            lib_file: Utf8PathBuf::from("libbjt.so")
        },
        include: vec![],
        opt_lvl: OptLevel::Aggressive,
        target: Target::search("x86_64-unknown-linux-gnu")?,
        target_cpu: "native".to_string(),
    };

    // Compile model
    match compile(&opts)? {
        CompilationTermination::Compiled { lib_file } => {
            println!("Successfully compiled: {}", lib_file);
            Ok(())
        }
        CompilationTermination::FatalDiagnostic => {
            eprintln!("Compilation failed with diagnostics");
            Err(anyhow::anyhow!("Compilation failed"))
        }
    }
}

// Use cache for faster recompilation
fn compile_with_cache() -> anyhow::Result<Utf8PathBuf> {
    let opts = Opts {
        input: Utf8PathBuf::from("mosfet.va"),
        output: CompilationDestination::Cache {
            cache_dir: Utf8PathBuf::from("/tmp/openvaf_cache")
        },
        opt_lvl: OptLevel::Default,
        target: Target::search(&openvaf::host_triple())?,
        target_cpu: "generic".to_string(),
        ..Default::default()
    };

    match compile(&opts)? {
        CompilationTermination::Compiled { lib_file } => Ok(lib_file),
        CompilationTermination::FatalDiagnostic => {
            Err(anyhow::anyhow!("Compilation failed"))
        }
    }
}

```

--------------------------------

### Install LLVM on Fedora

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Installs LLVM and its development headers from the default repositories on Fedora 37 and newer. This command ensures the necessary LLVM libraries are available for compiling OpenVAF.

```shell
sudo dnf install clang llvm-devel
```

--------------------------------

### Install LLVM on Debian/Ubuntu

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Installs LLVM using the official LLVM Project provided packages for Debian and Ubuntu systems. This script ensures compatibility with required LLVM versions for building OpenVAF.

```shell
sudo bash -c "$(wget -O - https://apt.llvm.org/llvm.sh)"
```

--------------------------------

### Run OpenVAF Tests

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Executes the test suite for OpenVAF using the default Cargo test runner. This command requires no additional installation and verifies the correctness of the project's components.

```shell
cargo test
```

--------------------------------

### Run OpenVAF Tests with cargo-nextest

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Executes the OpenVAF test suite using `cargo-nextest`, a faster alternative to the default test runner. This requires `cargo-nextest` to be installed separately.

```shell
cargo nextest run
```

--------------------------------

### Build OpenVAF with Shared LLVM Libraries

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Builds OpenVAF using shared LLVM system libraries instead of static ones, which can be preferable for portability or when managing multiple LLVM installations. The `LLVM_LINK_SHARED` environment variable enables this, and `LLVM_CONFIG` specifies the correct `llvm-config` binary.

```shell
LLVM_LINK_SHARED=1 LLVM_CONFIG="llvm-config-15" cargo build --release
```

--------------------------------

### Build OpenVAF with Docker

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Instructions to build OpenVAF using the official Docker image. This process involves cloning the repository, pulling the necessary Docker image, running a Docker container with volume mounting, and then executing the build command within the container. The compiled binary will be available in the target/release/openvaf directory.

```shell
git clone https://github.com/pascalkuthe/OpenVAF.git && cd OpenVAF
docker pull ghcr.io/pascalkuthe/ferris_ci_build_x86_64-unknown-linux-gnu:latest
docker run -ti -v $(pwd):/io ghcr.io/pascalkuthe/ferris_ci_build_x86_64-unknown-linux-gnu:latest
cd /io
cargo build --release
```

--------------------------------

### Load VerilogAE Models from C/C++ using VerilogAE C API

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

This C code demonstrates how to load VerilogAE models from a specified path using the `verilogae_load` function. It configures compilation options, accesses model metadata like module name and parameters, retrieves function pointers, sets up input data, and calls a VerilogAE function. Error handling for loading and function retrieval is included. It requires the `verilogae.h` header.

```c
#include <stdio.h>
#include "verilogae.h"

int main() {
    // Create options structure
    Opts* opts = verilogae_new_opts();

    // Configure compilation options
    opts->opt_lvl = OptLevel_Aggressive;
    const char* cache_dir = "/tmp/cache";
    opts->cache_dir.ptr = (uint8_t*)cache_dir;
    opts->cache_dir.len = strlen(cache_dir);

    // Load model
    Slice path = {.ptr = (uint8_t*)"diode.va", .len = 8};
    void* lib = verilogae_load(path, true, opts);
    if (!lib) {
        fprintf(stderr, "Failed to load model\n");
        return 1;
    }

    // Access model metadata
    const char* module = verilogae_module_name(lib);
    size_t param_cnt = verilogae_real_param_cnt(lib);
    const char** params = verilogae_real_params(lib);

    printf("Module: %s\n", module);
    printf("Parameters: %zu\n", param_cnt);

    // Get function pointer
    VaeFun fun = verilogae_fun_ptr(lib, "fun.0");
    if (!fun) {
        fprintf(stderr, "Function not found\n");
        return 1;
    }

    // Setup input arrays
    FatPtr voltages[2];
    double v_data[] = {0.7, 0.0};
    voltages[0].ptr = &v_data[0];
    voltages[0].meta.stride = 0;

    FatPtr real_params[2];
    double is_val = 1e-14;
    real_params[0].ptr = &is_val;
    real_params[0].meta.stride = 0;

    double output;

    // Call function
    verilogae_call_fun_parallel(
        fun, 1,
        voltages, NULL,
        real_params, NULL, NULL,
        NULL, NULL, NULL,
        &output
    );

    printf("Result: %e\n", output);

    verilogae_free_opts(opts);
    return 0;
}

```

--------------------------------

### Build OpenVAF (Release)

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Compiles the entire OpenVAF project in release mode, optimizing for performance. This is the standard command to build the final executable with all features enabled.

```shell
cargo build --release
```

--------------------------------

### VerilogAE Python - Load and Evaluate Models

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

Python library for loading Verilog-A models and evaluating equations with parameter sweeps.

```APIDOC
## VerilogAE Python API

### Description
Python library for loading Verilog-A models and evaluating their equations, offering functionalities for model compilation, metadata access, and function evaluation.

### Method
Python Function Call

### Endpoint
N/A (Python Library)

### Parameters
#### `verilogae.load()`
- **file_path** (string) - Required - Path to the Verilog-A model file.
- **cache_dir** (string) - Optional - Directory for caching compilation artifacts.
- **opt_lvl** (integer) - Optional - Optimization level for compilation (e.g., 0, 1, 2, 3).
- **include_dirs** (list of strings) - Optional - List of directories to include for model imports.
- **macro_flags** (list of strings) - Optional - List of preprocessor macro definitions (e.g., `"TEMPERATURE=300"`).

#### `verilogae.load_info()`
- **file_path** (string) - Required - Path to the Verilog-A model file.
- **cache_dir** (string) - Optional - Directory for caching compilation artifacts.

### Request Example
```python
import verilogae
import numpy as np

# Load a Verilog-A model with full compilation
model = verilogae.load(
    "diode.va",
    cache_dir="~/.cache/verilogae",
    opt_lvl=3,
    include_dirs=["./includes"],
    macro_flags=["TEMPERATURE=300"]
)
```

### Response
#### Success Response (`verilogae.load()`)
- **model** (object) - An object representing the loaded Verilog-A model with attributes like `module_name`, `params`, `nodes`, `opvars`, and `functions`.

#### Success Response (`verilogae.load_info()`)
- **info** (object) - An object containing metadata about the model, such as `functions`.

#### Example Response (`model` object attributes)
```python
# Access model metadata
print(f"Module: {model.module_name}")
print(f"Parameters: {model.params.real}")
print(f"Nodes: {model.nodes}")
print(f"Operating point variables: {model.opvars}")

# Evaluate a specific function (e.g., diode current)
voltages = np.linspace(0, 1.0, 1000)
temperature = np.full(1000, 300.0)

currents = model.functions['I_diode'](
    voltages={'anode': voltages, 'cathode': np.zeros(1000)},
    real_params={'is': 1e-14, 'n': 1.2},
    temperature=temperature
)
```

#### Example Response (`info` object attributes)
```python
# Load model info only
info = verilogae.load_info(
    "transistor.va",
    cache_dir="~/.cache/verilogae"
)
print(f"Available functions: {info.functions}")
```
```

--------------------------------

### OpenVAF CLI - Compile Verilog-A to OSDI

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

Command-line interface for compiling Verilog-A files into shared libraries compatible with OSDI-based circuit simulators.

```APIDOC
## OpenVAF CLI - Compile Verilog-A to OSDI

### Description
Command-line interface for compiling Verilog-A files into shared libraries compatible with OSDI-based circuit simulators.

### Method
CLI Command

### Endpoint
N/A (Command-line tool)

### Parameters
#### Command-line Arguments
- **input.va** (string) - Required - Path to the Verilog-A input file.
- **-o [output_file]** (string) - Optional - Specifies the output shared library file name.
- **--opt-lvl [level]** (integer) - Optional - Sets the optimization level (e.g., 0, 1, 2, 3).
- **--target [target_triple]** (string) - Optional - Specifies the compilation target triple (e.g., x86_64-unknown-linux-gnu).
- **--cache-dir [path]** (string) - Optional - Sets the directory for caching compilation artifacts.
- **-D [MACRO]** (string) - Optional - Defines a preprocessor macro.
- **-I [INCLUDE_DIR]** (string) - Optional - Adds a directory to the include search path.
- **--print-expansion** - Optional - Prints the preprocessed output after macro expansion.
- **--target-cpu [cpu_name]** (string) - Optional - Specifies the target CPU architecture.

### Request Example
```bash
openvaf diode.va -o libdiode.so --opt-lvl 3 --target x86_64-unknown-linux-gnu
```

### Response
#### Success Response (0)
- **[output_file]** (shared library) - The compiled shared library file.
```

--------------------------------

### Load OSDI Models in C Simulator

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

Loads and interacts with OSDI-compiled models within a C-based circuit simulator. It dynamically links to the OSDI shared library, checks the version, accesses model descriptors, and initializes/evaluates model instances. Requires the OSDI library and its header files.

```c
#include <dlfcn.h>
#include <stdio.h>
#include "osdi.h"

void load_osdi_model(const char* lib_path) {
    // Load shared library
    void* handle = dlopen(lib_path, RTLD_NOW | RTLD_LOCAL);
    if (!handle) {
        fprintf(stderr, "Failed to load: %s\n", dlerror());
        return;
    }

    // Check OSDI version
    uint32_t* major = dlsym(handle, "OSDI_VERSION_MAJOR");
    uint32_t* minor = dlsym(handle, "OSDI_VERSION_MINOR");
    printf("OSDI Version: %u.%u\n", *major, *minor);

    // Access descriptors
    uint32_t* num_desc = dlsym(handle, "OSDI_NUM_DESCRIPTORS");
    OsdiDescriptor** descriptors = dlsym(handle, "OSDI_DESCRIPTORS");

    for (uint32_t i = 0; i < *num_desc; i++) {
        OsdiDescriptor* desc = descriptors[i];
        printf("Model: %s\n", desc->name);
        printf("Nodes: %zu\n", desc->num_nodes);
        printf("Parameters: %zu\n", desc->num_params);

        // Initialize model instance
        void* model_data = malloc(desc->model_data_size);
        desc->setup_model(model_data);

        // Create instance
        void* inst_data = malloc(desc->instance_data_size);
        desc->setup_instance(inst_data, model_data);

        // Evaluate model
        desc->eval(inst_data, model_data);

        free(inst_data);
        free(model_data);
    }

    dlclose(handle);
}

```

--------------------------------

### Verilog-A Model Parameter Initialization and Defaults

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code snippet shows the initialization of variables within the 'initializeInstance' branch and the setting of default values for model parameters. It also includes adjustments for compatibility with older model parameter sets.

```Verilog-A
introduced initialization of IWnqs0_A, Inqs0_A, Inqs0_K, Q_nqs_A, Q_nqs_K and W_nqs_A into initializeInstance branch of diode_cmc.va
Set default of NJH to 1 for compatibility with old model parameter sets
```

--------------------------------

### Configure Verilog-A Lints and Diagnostics in Bash

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

This bash script demonstrates how to configure compiler warnings and errors for Verilog-A code quality using the 'openvaf' command. It shows how to deny specific lint warnings (e.g., unused variables), warn about deprecated syntax, allow certain patterns (e.g., implicit port direction), and print preprocessor expansion for debugging.

```bash
# Deny specific lint warnings
openvaf model.va \
    --deny unused_variables \
    --deny unreachable_code \
    --warn deprecated_syntax \
    -o libmodel.so

# Allow certain patterns
openvaf legacy_model.va \
    --allow implicit_port_direction \
    --allow missing_discipline \
    -o liblegacy.so

# Preprocessor debugging
openvaf complex_model.va --print-expansion > expanded.va

```

--------------------------------

### Run OpenVAF Debug Build

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Creates a debug build of OpenVAF and immediately runs it with the specified VerilogAE file. This command is convenient for quickly testing code changes during development.

```shell
cargo run --bin opnevaf test.va
```

--------------------------------

### Build and Simulate Circuits with Melange in Rust

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

This Rust code demonstrates building and simulating electronic circuits using the Melange library. It defines a circuit description, adds components like resistors, capacitors, and Verilog-A devices, elaborates the circuit, and then performs DC operating point and AC analyses. Requires the 'melange' and 'anyhow' crates.

```rust
use melange::core::{Circuit, CircuitDescription};

fn simulate_amplifier() -> anyhow::Result<()> {
    // Create circuit description
    let mut circuit = CircuitDescription::new();

    // Add components
    circuit.add_resistor("R1", "vdd", "out", 10e3)?;
    circuit.add_resistor("R2", "out", "gnd", 10e3)?;
    circuit.add_capacitor("C1", "in", "gate", 1e-6)?;

    // Add transistor from Verilog-A model
    circuit.add_veriloga_device(
        "M1",
        "bsim6.va",
        vec![("drain", "out"), ("gate", "gate"), ("source", "gnd")]
    )?;

    // Add voltage sources
    circuit.add_vsource("VDD", "vdd", "gnd", 5.0)?;
    circuit.add_vsource("VIN", "in", "gnd", 0.0)?;

    // Elaborate circuit
    let circuit = circuit.elaborate()?;

    // Run DC operating point
    let op = circuit.dc_operating_point()?;
    println!("Output voltage: {} V", op.get_voltage("out")?);

    // Run AC analysis
    let ac = circuit.ac_analysis(1.0, 1e6, 100)?;
    for (freq, gain) in ac.frequency_response("in", "out") {
        println!("f={:.2e} Hz, gain={:.2} dB", freq, 20.0 * gain.log10());
    }

    Ok(())
}

```

--------------------------------

### Configure LLVM Backend and Cross-Compilation in Bash Script

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

This bash script configures the build process for cross-platform model compilation using LLVM. It sets environment variables for LLVM configuration and targets, builds the 'openvaf' binary with Cargo, and then compiles Verilog-A models for multiple architectures (Linux x86_64, Windows x86_64, Linux ARM64). Finally, it executes workspace tests.

```bash
#!/bin/bash
# Build script for cross-platform model compilation

# Set LLVM configuration
export LLVM_CONFIG=/usr/bin/llvm-config-15
export LLVM_LINK_SHARED=0  # Static linking for portability

# Build OpenVAF
cargo build --release --bin openvaf

# Compile models for multiple targets
targets=(
    "x86_64-unknown-linux-gnu"
    "x86_64-pc-windows-msvc"
    "aarch64-unknown-linux-gnu"
)

for target in "${targets[@]}"; do
    echo "Compiling for $target..."
    ./target/release/openvaf \
        models/diode.va \
        --target "$target" \
        --target-cpu generic \
        --opt-lvl 3 \
        -o "output/diode_${target}.so"
done

# Run tests
cargo test --workspace
RUN_SLOW_TESTS=1 cargo nextest run

```

--------------------------------

### Load and Evaluate Verilog-A Models with VerilogAE Python

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

The VerilogAE Python library allows loading Verilog-A models for evaluation and parameter sweeps. It supports full compilation with options for cache directory, optimization level, include paths, and macro flags. Metadata such as module name, parameters, nodes, and operating point variables can be accessed. Specific model functions can be called by providing inputs as NumPy arrays.

```python
import verilogae
import numpy as np

# Load a Verilog-A model with full compilation
model = verilogae.load(
    "diode.va",
    cache_dir="~/.cache/verilogae",
    opt_lvl=3,
    include_dirs=["./includes"],
    macro_flags=["TEMPERATURE=300"]
)

# Access model metadata
print(f"Module: {model.module_name}")
print(f"Parameters: {model.params.real}")
print(f"Nodes: {model.nodes}")
print(f"Operating point variables: {model.opvars}")

# Evaluate a specific function (e.g., diode current)
# Setup parameters as numpy arrays
n_instances = 1000
voltages = np.linspace(0, 1.0, n_instances)
temperature = np.full(n_instances, 300.0)

# Call model function
currents = model.functions['I_diode'](
    voltages={'anode': voltages, 'cathode': np.zeros(n_instances)},
    real_params={'is': 1e-14, 'n': 1.2},
    temperature=temperature
)

# Load model info only (faster, no function compilation)
info = verilogae.load_info(
    "transistor.va",
    cache_dir="~/.cache/verilogae"
)
print(f"Available functions: {info.functions}")
```

--------------------------------

### Verilog-A Implementation of Recovery Equations and NQS Contributions

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code introduces comprehensive support for device recovery, including new equations and Non-Quasi-Static (NQS) node contributions. It also adds a recovery charge ('qrr') for operational point information.

```Verilog-A
Added CORECOVERY as a model flag for recovery equations
Added recovery equations
Added recovery charge "qrr" for OPinfo
```

--------------------------------

### Compile Verilog-A to OSDI Shared Library using OpenVAF CLI

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

The OpenVAF command-line interface compiles Verilog-A files into shared libraries compatible with OSDI-based circuit simulators. Options include specifying output, optimization levels, target architecture, cache directories, preprocessor macros, include paths, and printing preprocessed output. It supports cross-compilation for different platforms.

```bash
# Basic compilation - produces a shared library
openvaf input.va -o libmodel.so

# Compilation with optimization level and target specification
openvaf diode.va -o libdiode.so --opt-lvl 3 --target x86_64-unknown-linux-gnu

# Use cache directory for faster recompilation
openvaf bsim6.va --cache-dir ~/.cache/openvaf

# Define preprocessor macros and include directories
openvaf model.va -D TEMPERATURE=300 -D DEBUG -I ./includes -o libmodel.so

# Print preprocessed output (macro expansion)
openvaf model.va --print-expansion

# Cross-compilation for different target
openvaf model.va --target x86_64-pc-windows-msvc --target-cpu haswell -o model.dll
```

--------------------------------

### Build OpenVAF (Debug)

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Compiles OpenVAF in debug mode, which results in faster build times compared to release builds. This is recommended for active development cycles.

```shell
cargo build
```

--------------------------------

### Verilog-A Code Simplification and Model Unification

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code demonstrates simplification by removing redundant variables and consolidating DC and recovery models. It introduces new parameters for high-injection conditions and temperature dependence, aiming for a more unified and accurate model.

```Verilog-A
Removed redundant variables (here_DIO_beta, TNOM_i, TTEMP)
Unified DC and recovery models by substituting idmultbot for exp_A
Added TAUT for temp. co of carrier lifetime
Added INJT for temp. co of carrier density under high-inj. condition
```

--------------------------------

### Verilog-A Initialization and Parameter Updates

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code initializes several variables before an if statement and updates model parameters like LEVEL and VERSION. It also introduces new model parameters such as FREV for post-breakdown current.

```Verilog-A
put initialization of VRS, Vtotal, idmultbot, idmultgat and idmultsti before if statement (if SWJUNEXP_i ==1 ...)
updated LEVEL from 1002 to 2002 and VERSION from 1 to 2
```

--------------------------------

### Build OpenVAF Binary Only (Release)

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Compiles only the `openvaf` binary in release mode, excluding other components like melange and VerilogAE. This is useful when only the core OpenVAF executable is needed.

```shell
cargo build --release --bin openvaf
```

--------------------------------

### Check Source Code with cargo clippy

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Analyzes the OpenVAF source code for common errors and style issues using `cargo clippy` without performing a full build. This is a fast way to catch potential problems during development.

```shell
cargo clippy
```

--------------------------------

### OpenVAF: Add New Parameters for Leakage and Charge Models

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/PSP103/releasenotesPSP103p7.txt

This snippet details the addition of numerous new parameters in OpenVAF, particularly within PSP103_parlist.include and PSP103_scaling.include. These parameters enhance the model's ability to describe gate leakage currents and charge model behavior, including factors like saturation and partitioning.

```Verilog-A
// PSP103_parlist.include
// Addition of new parameters SWQSAT, SWQPART, CFAC, THESATAC, AXAC, ALPAC, GC2OV, GC3OV, CFACL, CFACLEXP, CFACW, THESATACO, THESATACL, THESATACLEXP, THESATACW, THESATACLW, AXACO, AXACL, ALPACL, ALPACLEXP, ALPACW, GC2OVO, GC3OVO, POCFAC, PLCFAC, PWCFAC, PLWCFAC, POTHESATAC, PLTHESATAC, PWTHESATAC, PLWTHESATAC, POAXAC, PLAXAC, PWAXAC, PLWAXAC, POGC2OV, POGC3OV, KVSATAC

```

```Verilog-A
// PSP103_scaling.include
// Addition of new internal local parameters, associated scaling rules and clipped variables: CFAC_p, THESATAC_p, AXAC_p, ALPAC_p, GC2OV_p, GC3OV_p, CFAC_i, THESATAC_i, AXAC_i, ALPAC_i, GC2OV_i, GC3OV_i

```

--------------------------------

### Run Slow Integration Tests

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Enables and runs the slow integration tests for OpenVAF, which typically involve compiling entire compact models. This is controlled by the `RUN_SLOW_TESTS` environment variable and is useful for thorough testing during development.

```shell
RUN_SLOW_TESTS=1 cargo nextest run
```

--------------------------------

### Decompress LLVM Archive

Source: https://github.com/pascalkuthe/openvaf/blob/master/README.md

Decompresses a `.tar.zst` archive containing prebuilt LLVM binaries, typically used on systems where LLVM-15 packages are not readily available. This command is essential for setting up the LLVM environment manually.

```shell
zstd -d -c --long=31 <path/to/archive.tar.zst> | tar -xf -
```

--------------------------------

### OpenVAF: Update Charge Partitioning and Leakage Current Calculations

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/PSP103/releasenotesPSP103p7.txt

Modifications in OpenVAF include a new switch parameter SWQPART for charge partitioning between drain and source, and updated calculations for overlap gate leakage currents. These changes aim to improve charge model decoupling and CV description.

```Verilog-A
// PSP103_module.include
// Addition of new variable declaration for charge model THESATAC_T
`define THESATAC_T_VAR(...)
```

```Verilog-A
// PSP103_module.include
// Modifications for overlaps leakage currents GC2_i, GC3_i and GCQ are replaced by GC2OV_i, GC3OV_i and GCQOV
// Calculation of GCQOV variable for overlap gate leakage currents

```

```Verilog-A
// PSP103_module.include
// Addition of the condition "SWQPART_i == 1.0" for charge partitioning and calculation of the new charge partitioning
if (SWQPART_i == 1.0) begin
  // Charge partitioning calculation
end

```

--------------------------------

### Export Verilog-AE VFS in Python

Source: https://context7.com/pascalkuthe/openvaf/llms.txt

Exports the virtual file system (VFS) containing preprocessed Verilog-A source files after macro expansion. This Python script utilizes the verilogae library to process a model file, supporting include directories and macro flags. The output VFS can be used for faster subsequent compilations.

```python
import verilogae

# Export preprocessed files
vfs = verilogae.export_vfs(
    "model.va",
    include_dirs=["./lib", "./disciplines"],
    macro_flags=["SIMULATOR=ngspice"]
)

# VFS is a dictionary of virtual paths to file contents
for path, content in vfs.items():
    print(f"File: {path}")
    print(f"Size: {len(content)} bytes")

    # Save to disk
    with open(f"preprocessed/{path}", 'w') as f:
        f.write(content)

# Use VFS in subsequent compilations for faster preprocessing
model = verilogae.load("model.va", vfs=vfs)

```

--------------------------------

### Verilog-A Junction Calculation and Parameter Handling

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code snippet addresses junction calculation by cleaning up globally declared arguments in macrofunctions and adding parameters for handling SBD devices. It also ensures the juncapexpress function works correctly when ideality factors are equal and adds warning messages for its limitations.

```Verilog-A
Cleaned up unwanted globally declared arguments in macrofunctions. They are in Juncap2 to facilitate source/drain junction calculation.
Added XTI/PT parameters to handle SBD
Made juncapexpress work if all the ideality factors have the same value
Added warning messages on Juncapexpress limitation
```

--------------------------------

### JUNCAP: Update Current and Charge Calculations with New Factors

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/PSP103/releasenotesPSP103p7.txt

Release notes for JUNCAP 200.6.0 indicate the addition of two multiplier factors, IFACTOR and CFACTOR, for current and charge calculations respectively. These factors are declared in JUNCAP200_parlist.include and used in the calculation of Ijprime and Qjprime.

```Verilog-A
// JUNCAP200_parlist.include
// Declaration of 2 new model parameters IFACTOR and CFACTOR
parameter real IFACTOR = 1.0;
parameter real CFACTOR = 1.0;

```

```Verilog-A
// JUNCAP200_macrodefs.include
// Addition of CFACTOR in the calculation of Qjprime: line 221
// Addition of IFACTOR in the calculation of Ijprime: line 276

```

--------------------------------

### Verilog-A High-Injection Model and Derivative Continuity

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code snippet adds directives and parameters to handle high-injection conditions and ensure derivative continuity in the junction capacitance equation. It includes a flag for the DC high-injection model and parameters for carrier lifetime temperature coefficients.

```Verilog-A
Added directive nja_dx for derivative continuity in juncap current equation
Added CODCHIGH as a model flag for DC high-injection model
Added TAUT for temp. co of carrier lifetime
```

--------------------------------

### Verilog-A Code Refactoring and Variable Management

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code snippet illustrates refactoring efforts, including commenting out redundant variable declarations and moving variable declarations to include files. This improves code organization and maintainability by centralizing variable definitions.

```Verilog-A
// commented declaration of ijunbot, ijunsti, ijungat, ijnonbot, ijnonsti and ijnongat because they are already declared in DIODE_CMC_varlist2.include
```

--------------------------------

### Verilog-A Model Parameter Adjustments and Bug Fixes

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code snippet shows adjustments to model parameters, including replacing fixed local variables and removing unused parameters. It also addresses bug fixes related to current glitches and resistor calculations.

```Verilog-A
Replaced PB and JUNCDLT with fixed local variables
Removed HSHIFT and WDEPK
Fixed a bug that caused current glitches when Imax is kicking in
When one of the resistor is zero, the total resistor is zero
```

--------------------------------

### Verilog-A ADMS Workaround and Code Tidy

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code includes a workaround for the ADMS ddx() function and general code tidying. It also adds parameters for device levels, versions, and shot noise model updates, along with a common resistor parameter.

```Verilog-A
ADMS workaround for ddx() function
Code tidy
Shot noise model update
Added rcommon resistor
```

--------------------------------

### Modified Current and Voltage Calculations in Verilog-A

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code modifies how VRS and current are calculated. It simplifies the VRS assignment and adjusts the current contribution based on MULT_i and the calculated VRS. These changes aim to improve accuracy and compatibility.

```Verilog-A
VRS = V(AIK, K);
I(AIK, K) <+ MULT_i * VRS * conducts;
vrs = TYPE * VRS;
```

--------------------------------

### Verilog-A Emission Coefficient and High Injection Updates

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code introduces a voltage-dependent emission coefficient and updates the junction capacitance equation to include high injection expressions. It also adjusts initial values for 'rnode' and introduces new parameters for injection and emission.

```Verilog-A
Introduced directive nja for voltage dependent emission coefficient
Added high injection expression in juncap current equation
Introduced NDIBOT, NDISTI and NDIGAT, and removed NDI
```

--------------------------------

### JUNCAP: Bug Fix for Express Model with MFOR2 and ISATFOR2

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/PSP103/releasenotesPSP103p7.txt

JUNCAP 200.6.0 includes a bug fix for the express model related to negative values of MFOR2 and ISATFOR2 variables. This modification ensures more stable calculations by adjusting the condition under which these variables are computed.

```Verilog-A
// JUNCAP200_macrodefs.include
// Modification of condition for calculation of MFOR2 and ISATFOR2 variables to avoid a bug on juncap express model.

```

--------------------------------

### Verilog-A Diffusion Capacitance and Current Dependency

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This Verilog-A code addresses a bug fix where diffusion capacitance was dependent on total current. The fix changes this dependency to be based on ideal current and SRH current instead, improving model accuracy.

```Verilog-A
Bug Fixes
   - Diffusion cap depends on ideal current and SRH current instead of
     total current
```

--------------------------------

### Conditional Voltage Assignment in Verilog-A

Source: https://github.com/pascalkuthe/openvaf/blob/master/integration_tests/DIODE_CMC/Updates.txt

This snippet demonstrates how to conditionally assign a voltage value based on a TYPE parameter in Verilog-A. It replaces a direct multiplication with an if-else structure for compatibility with certain simulators. This approach ensures correct voltage polarity regardless of the TYPE value.

```Verilog-A
if (TYPE == -1) begin
  VAK = -V(A, AIK);
end else begin
  VAK = V(A, AIK);
end
```

=== COMPLETE CONTENT === This response contains all available snippets from this library. No additional content exists. Do not make further requests.