### Makefile: Configuration Examples Source: https://context7.com/openxiangshan/xiangshan/llms.txt Examples demonstrating how to use configuration parameters with Makefile targets. These parameters allow customization of the build, such as specifying configurations, number of cores, or simulation threads. ```bash # Configuration examples: # make emu CONFIG=MinimalConfig NUM_CORES=1 EMU_THREADS=4 -j16 # make verilog CONFIG=DefaultConfig NUM_CORES=4 ISSUE=E.b ``` -------------------------------- ### Makefile: IDE and BSP Support Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets generate project configuration files for Integrated Development Environments (IDEs) like IntelliJ IDEA and support for the Build Server Protocol (BSP). This simplifies project setup and development workflows. ```bash # IDE support make idea # Generate IntelliJ IDEA project make bsp # Generate Build Server Protocol config ``` -------------------------------- ### Simulate with Verilator Source: https://context7.com/openxiangshan/xiangshan/llms.txt Build and run a C++ simulator using Verilator for functional verification and performance analysis. This requires setting NEMU_HOME, NOOP_HOME, and AM_HOME environment variables, then building with 'make emu' and running simulations with various options for configuration, parallelism, binary execution, and wave dumping. ```bash export NEMU_HOME=/path/to/nemu export NOOP_HOME=/path/to/xiangshan export AM_HOME=/path/to/nexus-am make emu make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin \ --diff ./ready-to-run/riscv64-nemu-interpreter-so ./build/emu -i program.bin --diff nemu-so --dump-wave ``` -------------------------------- ### Perform Difftest Co-Simulation (Bash) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Bash commands for setting up and running differential testing between the XiangShan simulator and a reference NEMU model. It includes building both simulators and executing the difftest. ```Bash # Build NEMU reference model cd $NEMU_HOME make riscv64-xs-ref # Build XiangShan with difftest enabled cd $NOOP_HOME make emu CONFIG=DefaultConfig # Run with difftest ./build/emu -i test_program.bin \ --diff $NEMU_HOME/build/riscv64-nemu-interpreter-so # Difftest checks every committed instruction # Output on mismatch: # [DIFFTEST] Mismatch at pc=0x80001234 # [DIFFTEST] REF: x1=0x0000000080002000 # [DIFFTEST] DUT: x1=0x0000000080002004 # [DIFFTEST] Simulation failed # Successful run: # [DIFFTEST] Simulation passed # HIT GOOD LOOP at pc = 0x80100000 ``` -------------------------------- ### Makefile: Simulation Build Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets build various simulators for the Xiangshan processor. They allow developers to choose between different simulation backends like Verilator, VCS, and GalaxSim for functional verification and performance analysis. ```bash # Simulation builds make emu # Build Verilator simulator make simv # Build VCS simulator make xsim # Build GalaxSim simulator ``` -------------------------------- ### Makefile: Dependency Management Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets handle the management of project dependencies, including downloading external libraries and initializing git submodules. They ensure that all necessary components are available for building and running the project. ```bash # Dependency management make deps # Download dependencies make init # Initialize git submodules make init-force # Force submodule initialization ``` -------------------------------- ### Build and Generate Verilog with Mill Source: https://context7.com/openxiangshan/xiangshan/llms.txt Generate SystemVerilog RTL from Chisel source code using the Mill build system. This process involves initializing submodules and then executing 'make verilog' with optional configuration parameters like CONFIG, NUM_CORES, L2_CACHE_SIZE, L3_CACHE_SIZE, and ISSUE version. ```bash make init make verilog make verilog CONFIG=MinimalConfig NUM_CORES=1 make verilog CONFIG=DefaultConfig NUM_CORES=4 L2_CACHE_SIZE=512 L3_CACHE_SIZE=4096 make verilog ISSUE=E.b ``` -------------------------------- ### Integrate XSCore into SoC with Peripherals (Scala) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Shows the Scala code for a top-level SoC module that integrates XSCore tiles, L2/L3 caches, memory controllers, and various peripherals like UART, CLINT, PLIC, and a Debug Module. ```Scala // Top-level SoC module class XSTop()(implicit p: Parameters) extends LazyModule { val xstiles = Seq.tabulate(NumCores) { i => LazyModule(new XSTile()(p.alterPartial { case XSTileKey => XSCoreParameters(HartId = i) })) } // L2 cache per core val l2cache = xstiles.map(_ => LazyModule(new HuanCun)) // Shared L3 cache val l3cache = LazyModule(new HuanCun) // Memory controller interface val memBus = TLXbar() // Peripheral connections val uart = LazyModule(new TLUART(UARTParams(address = 0x10000000L))) val timer = LazyModule(new TLCLINT(CLINTParams(address = 0x38000000L))) val plic = LazyModule(new TLPLIC(PLICParams(address = 0x3c000000L))) // Debug module for JTAG debugging val debugModule = LazyModule(new DebugModule) // Connections l3cache.node := TLBuffer() := memBus uart.node := TLBuffer() := memBus timer.node := memBus } ``` -------------------------------- ### Configure L1 and L2/L3 Cache Parameters (Scala) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Defines Scala case classes for configuring L1 Instruction and Data cache parameters such as the number of sets, ways, and block size. It also mentions how to set L2/L3 cache sizes using Makefile variables. ```Scala // L1 ICache configuration case class ICacheParameters( nSets: Int = 128, // 128 sets nWays: Int = 8, // 8-way associative blockBytes: Int = 64, // 64-byte cache line nPrefetchEntries: Int = 8, // Prefetch queue depth hasPrefetch: Boolean = true ) // L1 DCache configuration case class DCacheParameters( nSets: Int = 128, nWays: Int = 8, blockBytes: Int = 64, nMissEntries: Int = 16, // Miss status handling registers nProbeEntries: Int = 8, nReleaseEntries: Int = 18, nStoreReplayEntries: Int = 8 ) // Set L2/L3 cache sizes via Makefile // make verilog L2_CACHE_SIZE=512 L3_CACHE_SIZE=4096 // Sizes in KB, L2 per-core, L3 shared ``` -------------------------------- ### Access Performance Counters and Events (Scala) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Details the structure for performance events and how to connect and read performance counters using CSR instructions in Scala. It lists common performance events that can be monitored. ```Scala // Performance event structure class PerfEvent extends Bundle { val value = UInt(6.W) } // Connect performance counters val perfEvents = Wire(Vec(numCounters, new PerfEvent)) perfEvents := xscore.io.perfEvents // Performance counter CSR access def readPerfCounter(counterNum: Int): UInt = { val csr_addr = 0xB00 + counterNum // HPM counter base // Read via CSR instruction: csrr rd, 0xB03 } // Common performance events: // - Instructions retired // - Cycles // - Branch mispredictions // - Cache misses (L1I, L1D, L2, L3) // - TLB misses // - Pipeline stalls ``` -------------------------------- ### Python Debugger Integration Source: https://context7.com/openxiangshan/xiangshan/llms.txt Integrate an interactive debugger (xspdb) with a high-level Python interface. Build the bindings with 'make pdb' and run the interactive debugger with 'make pdb-run'. The session allows loading binaries, setting watchpoints, stepping through instructions, and inspecting program counters. ```bash make pdb make pdb-run # Interactive session commands: # (XiangShan) xload ready-to-run/microbench.bin # (XiangShan) xwatch_commit_pc 0x80000004 # (XiangShan) xistep 3 # (XiangShan) xpc ``` -------------------------------- ### Makefile: Code Quality Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets manage code formatting for Scala sources. They allow developers to check for style violations and automatically reformat the code to maintain consistency. ```bash # Code quality make check-format # Check Scala formatting make reformat # Apply Scala formatting ``` -------------------------------- ### Makefile: Compilation Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets are responsible for compiling the Scala source code and building the project into a standalone JAR file. They are essential for preparing the software components of the Xiangshan project. ```bash # Compilation make comp # Compile Scala sources make jar # Build standalone JAR ``` -------------------------------- ### Generate FPGA-Optimized Verilog (Bash) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Bash commands to generate Verilog files optimized for FPGA synthesis. This includes options to enable/disable specific features like assertions, performance counters, and debug modules using Makefile variables. ```Bash # Generate FPGA-optimized Verilog make verilog CONFIG=DefaultConfig RELEASE=1 # RELEASE=1 applies FPGA optimizations: # - Removes assertions # - Disables performance counters # - Optimizes memory generation # - Enables reset generation # Disable specific debug features make verilog CONFIG=DefaultConfig RELEASE=1 \ DISABLE_PERF=1DISABLE_ALWAYSDB=1 # Configure memory controller make verilog CONFIG=DefaultConfig \ SRAM_WITH_CTL=1 # Output for synthesis tools: # build/rtl/XSTop.sv # build/rtl/*.sv (split per module) ``` -------------------------------- ### Makefile: Cleanup Target Source: https://context7.com/openxiangshan/xiangshan/llms.txt This target removes build artifacts and intermediate files generated during the build process. It is useful for performing a clean build or freeing up disk space. ```bash # Cleanup make clean # Remove build artifacts ``` -------------------------------- ### Makefile: Code Generation Targets Source: https://context7.com/openxiangshan/xiangshan/llms.txt These targets are used to generate RTL (Register-Transfer Level) code for FPGA or simulation. They rely on the project's build system to produce the necessary Verilog files. ```bash # Code generation make verilog # Generate RTL for FPGA make sim-verilog # Generate RTL for simulation ``` -------------------------------- ### Instantiate XSCore Module in Chisel Source: https://context7.com/openxiangshan/xiangshan/llms.txt Instantiate the top-level XiangShan processor core (XSCore) module in Chisel. This involves connecting the core's I/O ports, including hart ID, reset vector, timer input, interrupt signals, and memory interfaces to the relevant system components like caches and interrupt controllers. ```scala // Instantiate XSCore in Chisel implicit val p: Parameters = // your parameters val xscore = Module(new XSCore()(p)) // Connect core inputs xscore.io.hartId := hartId.U xscore.io.reset_vector := 0x80000000L.U xscore.io.clintTime.valid := true.B xscore.io.clintTime.bits := timer_counter // Connect interrupt signals xscore.io.msiInfo <> msi_controller.io.msiOut msi_controller.io.msiAck := xscore.io.msiAck // Monitor core status val cpu_halted = xscore.io.cpu_halt val critical_error = xscore.io.cpu_critical_error // Memory interface connections l2cache.io <> xscore.memBlock.io uncache.io <> xscore.memBlock.io.uncache ``` -------------------------------- ### Parse Simulation Logs for Committed Instructions (Python) Source: https://context7.com/openxiangshan/xiangshan/llms.txt A Python script to parse simulation log files and extract information about committed instructions, including cycle, program counter, and instruction details. It uses regular expressions for pattern matching. ```Python # scripts/statistics.py - Parse simulation logs import sys import re def parse_commit_log(logfile): """Extract committed instructions from simulation log""" with open(logfile, 'r') as f: pattern = r'^\((\d+)\) pc=0x([0-9a-f]+) inst=0x([0-9a-f]+)' commits = [] for line in f: match = re.match(pattern, line) if match: cycle = int(match.group(1)) pc = int(match.group(2), 16) inst = int(match.group(3), 16) commits.append((cycle, pc, inst)) return commits # Usage: # python scripts/statistics.py simulation.log ``` -------------------------------- ### Analyze Performance Metrics (IPC, Branch Mispredictions) (Python) Source: https://context7.com/openxiangshan/xiangshan/llms.txt Python functions for calculating performance metrics such as Instructions Per Cycle (IPC) and Branch Mispredictions Per 1000 Instructions (MPKI). These are useful for analyzing simulation results. ```Python # scripts/perfcct.py - Performance counter analysis def calculate_ipc(commits, total_cycles): """Calculate instructions per cycle""" return len(commits) / total_cycles def calculate_branch_mpki(mispredicts, commits): """Calculate branch mispredictions per 1000 instructions""" return (mispredicts / len(commits)) * 1000 # Run simulation with performance logging: # ./build/emu -i program.bin --diff nemu-so > perf.log # python scripts/perfcct.py perf.log ``` -------------------------------- ### Define Custom Processor Configuration in Scala Source: https://context7.com/openxiangshan/xiangshan/llms.txt Define custom processor parameters using Scala configuration classes within the Chisel ecosystem. This involves extending 'BaseConfig' and using the 'alter' method to modify parameters such as decode width, ROB size, cache sizes, and enabling the vector processing unit. ```scala class MyCustomConfig(n: Int = 1) extends Config( new BaseConfig(n).alter((site, here, up) => { case XSTileKey => up(XSTileKey).map( p => p.copy( DecodeWidth = 8, // Decode 8 instructions per cycle RenameWidth = 8, // Rename 8 instructions per cycle RobCommitWidth = 10, // Commit up to 10 instructions per cycle RobSize = 256, // Reorder buffer size FtqSize = 64, // Fetch target queue size IBufSize = 48, // Instruction buffer size LoadQueueRAWSize = 64, // Load queue size StoreQueueSize = 56, // Store queue size IssueQueueSize = 16, // Issue queue entries intPreg = IntPregParams( numEntries = 192, // Integer physical registers numRead = 14, numWrite = 8 ), HasVPU = true, // Enable vector processing unit VLEN = 128 // Vector register length in bits ) ) }) ) // Build with custom configuration // make verilog CONFIG=MyCustomConfig ``` === COMPLETE CONTENT === This response contains all available snippets from this library. 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