### SystemVerilog Semaphore Example 1: Basic Key Management

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates creating a semaphore, acquiring keys using get(), and releasing them using put(). Shows how different processes interact with the semaphore.

```systemverilog
module semaphore_example_1;

  semaphore sem = new(6);

  initial begin : BEGIN_I
    $display("In first initial block At time=[%0t] ", $time);
    sem.get(4);
    $display("Thread 1: Accessing 4 keys from semaphore At time=[%0t] ", $time);
    #5;
    sem.put(4);
    $display("Thread 1: Done using 4 keys At time=[%0t] ", $time);
  end : BEGIN_I

  initial begin : BEGIN_II
    $display("In second initial block At time=[%0t] ", $time);
    sem.get(2);
    $display("Thread 2: Accessing 2 keys from semaphore At time=[%0t] ", $time);
    #10;
    sem.put(2);
    $display("Thread 2: Done using 2 keys At time=[%0t] ", $time);
  end : BEGIN_II

endmodule : semaphore_example_1
```

--------------------------------

### SystemVerilog Example: Set of Transition Bins

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Provides an example of using set transition bins in SystemVerilog to cover transitions between multiple possible values in a sequence.

```systemverilog
module single_val_trans_bin;

  bit [3:0] a;
  bit [2:0] values[$] = '{1,2,3,4,5};

  covergroup cov_grp;
    c1 : coverpoint a {
      bins tran_1 = (1,2 => 3,4);
      bins tran_2 = (3,4 => 5);
      bins tran_3 = (1,3 => 4);
    }
  endgroup

  cov_grp cg = new();

  initial
  begin
    foreach(values[i])
    begin
      a = values[i];
      cg.sample();
      $display("val = %d, cov = %.2f %%", a, cg.get_inst_coverage());
    end
  end
endmodule
```

--------------------------------

### Detailed SystemVerilog Process Resume Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Illustrates the resume() method's effect on process status, showing transitions from RUNNING to SUSPENDED and then to FINISHED. This example requires event triggers for synchronization.

```systemverilog
$display("[%0t] Seeking status:",$time);

fork:FORK_F1  
  begin:BEGIN_B2  
    p1 = process :: self();  
    #1;
    $display("[%0t] I am in process p1",$time);  
    $display("[%0t] Initial status of p1: %s",$time,p1.status());  
    ->e1;
    if(p1.status() != process :: FINISHED)  
        
    begin:BEGIN_B3  
      #1;
      $display("[%0t] Status of p1 before suspending: %s",$time,p1.status());  
      p1.suspend();  
      $display("[%0t] Status of p2 in p1 block: %s",$time,p2.status());  
    end:BEGIN_B3  

  end:BEGIN_B2  

  begin:BEGIN_B4  
    wait(e2.triggered);
    $display("[%0t] Status of p1 before resuming: %s",$time,p1.status());  
    p1.resume();  
    #1;
    $display("[%0t] Status of p1 after resuming: %s",$time,p1.status());  
    ->e3;  
  end:BEGIN_B4  

  begin:BEGIN_B6  
    p2 = process :: self();  
    #1;
    $display("[%0t] I am in process p2",$time);  
    $display("[%0t] Initial status of p2: %s",$time,p2.status());  

    if(p1.status() == process :: SUSPENDED)  
    #1 ->e2;
  end:BEGIN_B6  

  begin:BEGIN_B7  
    wait(e3.triggered);
    #1;
    $display("[%0t] Final status of p1: %s",$time,p1.status());  
    $display("[%0t] Final status of p2: %s",$time,p2.status());  
  end:BEGIN_B7  
join:FORK_F1
```

--------------------------------

### SystemVerilog Example Class: 'home'

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/15.Classes-and-oops

An example of a SystemVerilog class named 'home' with properties (light, fan, switch) and a method (open_electricity).

```systemverilog
class home;
   bit light;
   int fan ;
   string switch;

   task open_electricity();
      switch = "ON"
      $display("switch is %s so electricity is open",switch);
   endtask
endclass
```

--------------------------------

### SystemVerilog Mailbox get() Method Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates the blocking behavior of the get() method when retrieving messages from a mailbox. If the mailbox is empty, the process will block until a message is available.

```systemverilog
class A;

   int a;
   int i;
   mailbox m;

   function new(mailbox m1);
      this.m = m1;
   endfunction

   task tra_data();

      for(i = 0; i < 2; i++) begin:BEGIN_MAIN
         a++;
         m.put(a);
         $display("[%0t] 1. Transmitter: value of a = %0d", $time, a);
      end:BEGIN_MAIN

      $display("put successful");

   endtask

endclass:A

class B;

   int a;
   int i;
   mailbox m;

   function new(mailbox m2);
      this.m = m2;
   endfunction

   task rec_data();

      for(i = 0; i < 3; i++) begin:BEGIN_MAIN
         m.get(a);
         $display("[%0t] 2. Receiver: value of a = %0d", $time, a);
      end:BEGIN_MAIN

      $display("get successful");

   endtask

endclass:B

module tb();

   A a1;
   B b1;
   mailbox main = new(2);

   initial begin:BEGIN_MAIN

      a1 = new(main);
      b1 = new(main);

      repeat(2)
      begin:BEGIN_1

         a1.tra_data();
         $display("................................………………………………………………");
         b1.rec_data();

      end:BEGIN_1

   end:BEGIN_MAIN

endmodule:tb
```

--------------------------------

### SystemVerilog Bounded Mailbox Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

This example demonstrates creating a bounded mailbox of size 3 and transferring data into it. It checks if the mailbox was successfully created before putting elements.

```systemverilog
class A;

   int a;
   int i;
   mailbox  m;

   function new(mailbox m1);
      this.m = m1;
   endfunction

   task check();

      if(m == null)begin:BEGIN_1
         $display("Mailbox is not created");
      end:BEGIN_1

      else
         $display("Mailbox is created");

         for(i=0;i<3;i++)begin:BEGIN_2

            a++;
            m.put(a);
            $display("Value of a = %0d",a);

         end:BEGIN_2

    endtask

endclass:A

module  tb ();

   A a1;
   mailbox main = new(3);
   initial begin:BEGIN_MAIN

      a1= new(main);
      $display("");
      $display("");
      a1.check();

    end:BEGIN_MAIN

endmodule:tb
```

--------------------------------

### SystemVerilog wait_order() Syntax Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates the basic syntax for using the wait_order() method with three events.

```systemverilog
event e1;
event e2;
event e3;
wait_order(e1,e3,e2);
```

--------------------------------

### Static Delay Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/18.Assertion

A simple example demonstrating a static delay of 5 clock cycles between events 'a' and 'b'.

```systemverilog
a ##5 b;
```

--------------------------------

### SystemVerilog Mailbox try_peek Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates the `try_peek` method for non-destructively retrieving data from a mailbox. This snippet shows a transmitter (`A`) putting data into a mailbox and a receiver (`B`) attempting to peek at the data multiple times before getting it.

```systemverilog
class A;

   int a;
   int i;
   mailbox m;

   function new(mailbox m1);
      this.m = m1;
   endfunction

   task tra_data();
      for (i = 0; i < 1; i++) begin : BEGIN_MAIN
         a++;
         m.put(a);
         $display("[%0t] 1. Transmitter: value of a = %0d", $time, a);
      end : BEGIN_MAIN

      $display("put successful");
      $display("Messages in mailbox = %0d", m.num());
   endtask

endclass : A

class B;

   int a;
   int i;
   mailbox m;

   function new(mailbox m2);
      this.m = m2;
   endfunction

   task rec_data();
      for (i = 0; i < 2; i++) begin : BEGIN_MAIN
         if (m.try_peek(a)) begin : BEGIN_1
            $display("[%0t] Peeking value of a = %0d", $time, a);
            $display("Peek successful");
         end : BEGIN_1
         else begin
            $display("Peek failed as mailbox is empty");
            return;
         end
      end : BEGIN_MAIN

      m.get(a);
      $display("Receiver: value of a = %0d", a);
      $display("get successful");
   endtask

endclass : B

module tb ();

   A a1;
   B b1;
   mailbox main = new(2);

   initial begin : BEGIN_MAIN
      a1 = new(main);
      b1 = new(main);

      a1.tra_data();
      $display("...............................................");
      b1.rec_data();
      $display("...............................................");
      b1.rec_data();
      $display("End of program");
   end : BEGIN_MAIN

endmodule : tb

```

--------------------------------

### SystemVerilog $test$plusargs Basic Usage

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/20.Misc-Constructs

Demonstrates the basic usage of $test$plusargs to check for a command-line argument 'START'. If the argument is present, it displays 'Start process'.

```systemverilog
module CLI_testargs;
  bit x;
  
  initial begin:BEGIN-I
    x=$test$plusargs("START");
    $display("$test$plusargs returns %d",x);
    if(x)
      $display("Start process");
    else
      $display("exit");
  end:BEGIN-I

endmodule
```

--------------------------------

### Simple Task Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/08.Tasks

Demonstrates calling a simple task 'mul' with input and output arguments. The task includes a time delay and performs multiplication.

```systemverilog
int multiplicand=5,multiplicator=6,result;
initial begin
  $display("\t ----output of simple task calling----);
  mul(multiplicand,multiplicator,result);
  $display("\t @ %0t ns , %0d X %0d = %0d",$time,multiplicand,multiplicator,result);
end

task mul(input int var1,var2,output int res);
  #2;
  res=var1*var2;
endtask
```

--------------------------------

### SystemVerilog Process Kill Syntax Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Demonstrates the basic syntax for obtaining a process handle and calling the kill() method on it.

```systemverilog
Process p_handle1;
initial begin 
  fork 
    p_handle1 = process :: self();  
    p_handle1.kill(); 
  join_any  
end
```

--------------------------------

### SystemVerilog Process Resume Syntax Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Demonstrates the basic syntax for suspending and resuming processes using process handles and the resume() method.

```systemverilog
Process p_handle1,p_handle2;
initial begin 
  fork  
    begin  
      p_handle1 = process :: self();  
      p_handle1.suspend();  
    end  
    begin 
      p_handle2 = process :: self();
      p_handle1.resume();  
    end  
  join_none  
end
```

--------------------------------

### SystemVerilog Class Inheritance Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/15.Classes-and-oops

Demonstrates how a child class 'B' extends a parent class 'A', inheriting its members. The example shows how to instantiate the child class and access methods from both parent and child classes using the child's handle.

```systemverilog
class A;
  int a = 5;
  function void disp();
    $display("1.Value of a = %0d",a);
  endfunction:disp
 
endclass:A
 
class B extends A;
  int a = 6;
  function void display();
    $display("2.Value of a = %0d",a);
  endfunction:display
 
endclass:B
 
module inh_sam();
  B b1;
  initial begin
    b1 = new;
    b1.a = 10;
    b1.disp();
    b1.display();
  end
endmodule:inh_sam 
```

--------------------------------

### SystemVerilog Suspend() Method Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

This example demonstrates the suspend() method in SystemVerilog. It shows how one process can suspend another and how to check the status of a process before and after suspension. Ensure that the process is not blocked by other statements like wait or delay before suspending.

```systemverilog
$display("[%0t] Seeking status:",$time);

fork:FORK_F1  
  begin:BEGIN_B2  
    p1 = process :: self();  
    #1;
    $display("[%0t] I am in process p1",$time);
    $display("[%0t] Initial status of p1: %s",$time,p1.status());  
    ->e1;

    if(p1.status() != process :: FINISHED)  
    begin:BEGIN_B3  
      #1;
      $display("[%0t] Status of p1 before suspending: %s",$time,p1.status());  
      p1.suspend();  
      $display("[%0t] Status of p2 in p1 block: %s",$time,p2.status());  
    end:BEGIN_B3  
    
  end:BEGIN_B2  

  begin:BEGIN_B4  
    wait(e1.triggered);
    p2 = process :: self();  
    #1;
    $display("[%0t] I am in process p2",$time);
    $display("[%0t] Initial status of p2: %s",$time,p2.status());  
    #1;
    $display("[%0t] status of p1 after suspended: %s",$time,p1.status());  
    ->e2;
  end:BEGIN_B4  

  begin:BEGIN_B5  
    wait(e2.triggered);    
    $display("[%0t] Final status of p2: %s",$time,p2.status());  
  end:BEGIN_B5  
join:FORK_F1
```

--------------------------------

### SystemVerilog Example: Sequence of Transition Bins

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates how to define and use sequence transition bins in SystemVerilog to cover specific ordered transitions of a variable.

```systemverilog
module single_val_trans_bin;

  bit [3:0] a;
  bit [2:0] values[$] = '{1,2,3,4};

  covergroup cov_grp;
    c1 : coverpoint a {
      bins tran_1 = (1 => 2 => 3);
      bins tran_2 = (1 => 2 => 4);
    }
  endgroup

  cov_grp cg = new();

  initial
  begin
    foreach(values[i])
    begin
      a = values[i];
      cg.sample();
      $display("val = %d, cov = %.2f %%", a, cg.get_inst_coverage());
    end
  end
endmodule
```

--------------------------------

### SystemVerilog Covergroup Declaration and Execution Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates the declaration, instantiation, sampling, and coverage retrieval of a SystemVerilog covergroup.

```systemverilog
covergroup cgrp;
                  c1: coverpoint a;
                  c2: coverpoint b;
              endgroup
              cgrp cg =new();

              initial begin
                repeat (5)begin
                a=$random();
                b=$random();
                cg.sample();      
                $display("a=%d ; b=%d ; coverage = %.2f",a,b,cg.get_inst_coverage());
```

--------------------------------

### SystemVerilog Example of Goto Repetitions Bin

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates the 'goto repetitions' bin functionality in SystemVerilog using a covergroup to track transitions in a bit vector.

```systemverilog
module goto_repeat_bin;

  bit [3:0] a;
  bit [2:0] values[$] = '{1,2,3,4,3,4,2,3,4,5};

  covergroup cov_grp;
    c1 : coverpoint a {
      bins tran_1 = (1 => 4 [->3] => 5);
      // bins tran_2 = (1 => 3 [=3] => 4);
    }
  endgroup

  cov_grp cg = new();

  initial
  begin
    foreach(values[i])
    begin
      a = values[i];
      cg.sample();
      $display("val = %d, cov = %.2f %%", a, cg.get_inst_coverage());
    end
  end
endmodule
```

--------------------------------

### SystemVerilog Unbounded Mailbox Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

This example demonstrates creating an unbounded mailbox and transferring data into it. It shows that the mailbox can store multiple elements without overflowing, even after repeated calls to the data transfer task.

```systemverilog
class A;

   int a;
   int i;
   mailbox  m;

   function new(mailbox m1);
      this.m = m1;
   endfunction

   function void check();

      if(m == null)begin:BEGIN_1
         $display("Mailbox is not created");
      end:BEGIN_1

      else
         $display("Mailbox is created");

         $display("............................................");

   endfunction

   task tra_data();

      for(i=0; i<5; i++) begin:BEGIN_2
         m.put(a);
         a++;
         $display("Value of a = %0d", a);
      end:BEGIN_2

      $display("No of messages in mailbox = %0d", m.num());
   endtask

endclass:A

module tb ();

   A a1;
   mailbox main = new();

   initial begin:BEGIN_MAIN

      a1 = new(main);

      $display("");
      $display("");
      a1.check();

      repeat(2) begin:BEGIN_1
         $display("............................................");
         a1.tra_data();
      end:BEGIN_1

   end:BEGIN_MAIN

endmodule:tb
```

--------------------------------

### SystemVerilog Example of Wildcard Bin

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Illustrates the use of wildcard bins in SystemVerilog covergroups to match multiple states or transitions with don't care values.

```systemverilog
module wildcard_bin;

  bit [3:0] a;
  bit [3:0] values[$] = '{4'b1000, 4'b1001, 4'b1010, 4'b1011};

  covergroup cov_grp;
    c1 : coverpoint a {
      wildcard bins b1 = {4'b100x};
      wildcard bins b2 = {4'b101x};
    }
  endgroup

  cov_grp cg = new();

  initial
  begin
    foreach(values[i])
    begin
      a = values[i];
      cg.sample();
      $display("val = %d, cov = %.2f %%", a, cg.get_inst_coverage());
    end
  end
endmodule
```

--------------------------------

### Cross Coverage Example using Coverpoint Labels

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates cross coverage between two coverpoints 'c1' and 'c2' within a covergroup. This example shows how to define cross coverage using the labels of existing coverpoints.

```systemverilog
   covergroup cg;
     c1: coverpoint a;
     c2: coverpoint b;
     c3: cross c1,c2;
   endgroup
   cg = new();

```

--------------------------------

### Pure Virtual Method Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/15.Classes-and-oops

Illustrates the implementation of pure virtual methods in SystemVerilog. Pure virtual methods must be declared in the base class without definition and must be overridden in all derived classes. This example shows how derived class 'B' implements 'disp' and 'sum'.

```systemverilog
virtual class A;
  int a,b,c;
  pure virtual function void disp();
  pure virtual task sum();
endclass:A

class B extends A;
  virtual function void disp();
    a =10;
    $display("1.Value of a = %0d, b = %0d, c = %0d",a,b,c);
  endfunction:disp

  virtual task sum();
    c = a+b;
    $display("2.Value of a = %0d, b = %0d, c = %0d",a,b,c);
  endtask:sum

endclass:B

module pure_vir_fun_ex();
  B b1;
  initial begin
    b1 = new();
    b1.disp();
    b1.b = 35;
    b1.sum;
  end 
endmodule:pure_vir_fun_ex
```

--------------------------------

### SystemVerilog Example of Implicit Bins

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates the use of implicit bins in SystemVerilog. When no bins are explicitly defined for a coverpoint, SystemVerilog automatically creates bins for the possible values of the variable. This example shows a covergroup with an implicit coverpoint 'c1' for a 3-bit variable 'a'.

```systemverilog
module coverage_example;
  
  bit [2:0] a;

  covergroup cov_grp;
    c1 : coverpoint a;
  endgroup

  cov_grp cg = new();

  initial
  begin
    for (int i = 1; i <= 5; i++)
    begin
      a = $random();
      cg.sample();
      $display("a = %d, coverage = %.2f %%", a, cg.get_inst_coverage());
    end
  end
endmodule
```

--------------------------------

### SystemVerilog Bidirectional Constraint Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/14.Constraint

This example defines a class with a random variable and two constraints that limit its range. The module then instantiates the class and randomizes it multiple times to show how the constraints are applied bidirectionally.

```systemverilog
class items;
  rand bit [3:0] value1;

  constraint addr_mode1 { value1 > 5; value1 < 12; }
  constraint addr_mode2 { value1 > 6; }
endclass

module constraint_top;
  initial begin
    int i;
    items item;
    item = new();

    $display("----- Output for bidirectional constraint -----");
    $display("----- Constraint 1 & 2 limits the value to 7, 8, 9, 10, and 11 -----");
    $display("----------------------------------------------------------------");

    for (int i = 1; i < 10; i++) begin
      void'(item.randomize());
      $display("[%0t] @ iteration %0d -----> value1 = %0d", $time, i, item.value1);
    end

    $display("----------------------------------------------------------------");
  end
endmodule
```

--------------------------------

### SystemVerilog post_randomize Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/14.Constraint

Demonstrates the usage of pre_randomize and post_randomize functions. The post_randomize function is called after a successful randomization, and its execution can be observed through display statements.

```systemverilog
          function void pre_randomize();
               $display("\tI'm in pre_randomize function");
               check=0;
             endfunction
             function void post_randomize();
               $display("\tI'm in post_randomize function");
               check=1;
             endfunction  

             initial
                 begin
              
                     $display("\t[%0t]Calling Randomize....",$time);
                     check=gen.randomize();
                     #1  $display("\t[%0t] @ iteration: 1 -----> value: %0d ",$time,gen.value);
                     if(check==1)
                       $display("%c[1;32m\tRandomization is performed%c[0m",27,27);
                     else
                       $display("%c[1;31m\tRandomization is not performed%c[0m",27,27);
                     $display("\t[%0t]Calling Randomize....",$time);
                     check=gen.randomize()with{value<5;};
                      #1  $display("\t[%0t] @ iteration: 2  -----> value: %0d ",$time,gen.value);
                     if(check==1)
                       $display("%c[1;32m\tRandomization is performed%c[0m",27,27);
                     else
                       $display("%c[1;31m\tRandomization is not performed%c[0m",27,27);
 
                 end
```

--------------------------------

### Basic while loop example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/09.Loops

Demonstrates printing a statement multiple times using a while loop. Initializes a counter before the loop and increments it within the loop body.

```systemverilog
int apple = 1; //int data type and variable name is apple

initial begin  //procedural blocks
  $display("-----while loop output ---");
  while (apple <6) begin  //while loop and condition
    $display("\t value of apple = %0d", apple);
    apple++;
  end  
end
```

--------------------------------

### SystemVerilog Example: Covergroup Inside a Class

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Demonstrates a practical implementation of a covergroup within a class, including randomization of variables and covergroup instantiation.

```systemverilog
class pack;
  rand bit [1:0] a;
  rand bit [1:0] b;

  covergroup cg;
    c1: coverpoint a;
    c2: coverpoint b;
  endgroup

  function new();
    cg = new();
  endfunction
endclass
```

--------------------------------

### Get Process Status Syntax

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Demonstrates the basic syntax for obtaining the status of a process using the status() method.

```systemverilog
process p_handle;
initial begin
  begin  
    p_handle = process :: self();  
    $display("status : %s",p_handle.status());  
  end
end 

```

--------------------------------

### SystemVerilog peek Mailbox Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates the peek method for copying a message from the mailbox without removing it. This is a blocking method.

```systemverilog
class A;

   int a;
   int i;
   mailbox m;

   function new(mailbox m1);
      this.m = m1;
   endfunction

   task tra_data();
      for (i = 0; i < 1; i++) begin : BEGIN_MAIN
         a++;
         m.put(a);
         $display("[%0t] 1. Transmitter: value of a = %0d", $time, a);
      end : BEGIN_MAIN

      $display("put successful");
      $display("Messages in mailbox = %0d", m.num());
   endtask

endclass : A

class B;

   int a;
   int i;
   mailbox m;

   function new(mailbox m2);
      this.m = m2;
   endfunction

   task rec_data();
      for (i = 0; i < 2; i++) begin : BEGIN_MAIN
         m.peek(a);
         $display("[%0t] Peeking value of a = %0d", $time, a);
         $display("Peek successful");
      end : BEGIN_MAIN

      m.get(a);
      $display("[%0t] 2. Receiver: value of a = %0d", $time, a);
      $display("get successful");
      $display("Messages in mailbox = %0d", m.num());
   endtask

endclass : B

module tb();

   A a1;
   B b1;
   mailbox main = new(2);

   initial begin : BEGIN_MAIN
      a1 = new(main);
      b1 = new(main);

      a1.tra_data();
      $display("................................………………………………………………");
      b1.rec_data();
      $display("................................………………………………………………");
      b1.rec_data();
      $display("End of program");
   end : BEGIN_MAIN

endmodule : tb

```

--------------------------------

### SystemVerilog Normal Constraint Example (No Conflict)

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/14.Constraint

Demonstrates randomization with normal constraints and then with an inline constraint that overrides the class constraint when no conflict exists.

```systemverilog
class pack;
  rand bit [3:0] a;
  constraint addr_a { a > 5; }
endclass

module soft_without_conflict;

  pack pkh;

  initial begin
    pkh = new();
    $display("Without using soft constraint output");

    for (int i = 0; i < 5; i++) begin
      void'(pkh.randomize());
      $display("\n 	 a = %0d value = %0d", i, pkh.a);
    end

    pkh = new();
    $display("\n 	 Output of without conflict");

    for (int i = 0; i < 5; i++) begin
      void'(pkh.randomize() with { a < 10; });
      $display("\n 	 a = %0d value = %0d", i, pkh.a);
    end
  end
endmodule
```

--------------------------------

### SystemVerilog Unbounded Mailbox Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/19.Interprocess-Communication

Demonstrates an unbounded mailbox where the transmitter can put data without checking for fullness. The receiver gets data as it becomes available.

```systemverilog
class A;

  int a;
  int i;
  mailbox m;

  function new(mailbox m1);
    this.m = m1;
  endfunction

  task tra_data();
    for (i = 0; i < 3; i++) begin : BEGIN_MAIN
      a++;
      m.put(a);
      $display("[%0t] 1. Transmitter: value of a = %0d", $time, a);
    end : BEGIN_MAIN
  endtask

endclass : A


class B;

  int a;
  int i;
  mailbox m;

  function new(mailbox m2);
    this.m = m2;
  endfunction

  task rec_data();
    begin : BEGIN_MAIN
      m.get(a);
      $display("[%0t] 2. Receiver: value of a = %0d", $time, a);
    end : BEGIN_MAIN
  endtask

endclass : B


module tb();

  A a1;
  B b1;
  mailbox main = new();

  initial begin : BEGIN_MAIN
    a1 = new(main);
    b1 = new(main);
    
    repeat(2) begin : BEGIN_1
      a1.tra_data();
      $display("................................ רבי.");
      b1.rec_data();
    end : BEGIN_1

  end : BEGIN_MAIN

endmodule : tb
```

--------------------------------

### SystemVerilog File Handle and Display

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/20.Misc-Constructs

Demonstrates the use of $fopen, $fdisplay, and $fclose to create a file, write content into it, and then close the file. This is a basic example for file output operations.

```systemverilog
module file_handles;
  int f;
  initial begin
    f=$fopen("file_handle","w");
      
    $fdisplay(f,"fileoperations");
    $fdisplay(f,"sv course");

    $fclose(f);
  end 
endmodule

```

--------------------------------

### SystemVerilog Read Filename and Manipulate File Content

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/20.Misc-Constructs

This example shows how to read a filename from the command line using $value$plusargs, then open, read from, and append to that file. The function is used to get the filename and also to indicate success.

```systemverilog
module CLI_valargs1;
  bit x;
  string y;
  string s;
  int fd,f;
  string message;
  
  initial begin
    x=$value$plusargs("msg=%s",message);
    $display("$value$plusargs used above returns %0d",x);
    $display(message);
    void'($value$plusargs("file=%s",y));
    fd=$fopen(y,"r");
    
    $fgets(s,fd);
    $display(s);
    
    $fclose(fd);

    fd=$fopen(y,"a");
    
    $fdisplay(fd,"Hurray!");
    
    $fclose(fd);
  end

endmodule
```

--------------------------------

### Example Parameterized Interface Definition

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/13.Interface

An example of a parameterized interface named 'count_if' with a default parameter N=2 for the counter width.

```systemverilog
interface count_if #(parameter N=2) ;
  logic reset,clk;
  logic [N:0] counter;
endinterface:count_if
```

--------------------------------

### SystemVerilog Property Example with Reset Disable

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/18.Assertion

An example of a SystemVerilog property that uses 'disable iff' with a 'reset' signal. The property is only active when 'reset' is deasserted.

```systemverilog
property p;
  @(posedge clk)
  disable iff (reset) (a&&b);
endproperty
```

--------------------------------

### SystemVerilog Process Await Syntax Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Demonstrates the basic syntax for using the await() method to allow one process to wait for another to complete. This is useful for establishing dependencies between concurrent processes.

```systemverilog
Process p_handle1,p_handle2;
initial begin
  fork
    begin
      p_handle1 = process :: self();
      p_handle2.await();
    end
    begin
      p_handle2 = process :: self();
    end
  join
end
```

--------------------------------

### SystemVerilog Syntax for Set of Transition Bins

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Illustrates the syntax for defining transition bins that cover transitions between sets of values in SystemVerilog.

```systemverilog
coverpoint_name: coverpoint variable {
  bins bin 1[] = (transition_set 1 => transition_set 2);
}
```

--------------------------------

### Packed Union Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/03.Structure-and-Union

An example of a packed union declaration in SystemVerilog. It uses 'bit [7:0]' for all members, adhering to the packed union constraint of same-type and same-size elements.

```systemverilog
typedef union packed {
        bit [7:0];
        bit [7:0];
     } abc_u ;
```

--------------------------------

### Error Example: Class Declaration Without Typedef

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/04.User-defined

This example demonstrates the compilation error that occurs when a class variable is used before its class is declared, and 'typedef class' is not employed.

```SystemVerilog
class fruit1;
fruit2 f;
$display("Class 1 executed");
endclass

class fruit2;
fruit1 f;
$display("Class 2 executed");
endclass
```

--------------------------------

### SystemVerilog Queue with Push Operation

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/Choosing-an-array

Shows how to use a queue in SystemVerilog with the push_back() operation to add elements. The example demonstrates that repeated push operations can lead to excessive array growth and process termination.

```systemverilog
     module queue;
       int que[$];
       initial begin
         que = '{2,7,0,6,1,9,9,7};
         foreach(que[i])begin
           $display("verifying the values of each index, que[%0d] = %0d", i, que[i]);
           que.push_back(6);
         end
       end
     endmodule 
```

--------------------------------

### Unpacked Union Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/03.Structure-and-Union

An example of an unpacked union declaration in SystemVerilog. It includes 'int' and 'byte' members, demonstrating how the largest member ('int') dictates the shared memory size.

```systemverilog
union {
  int x;
  byte y;
} data_u;
```

--------------------------------

### SystemVerilog Process Await Detailed Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/12.Fine-Grain-Process-Control

Illustrates a detailed scenario where process p1 waits for process p2 to finish using the await() method. Observe the status changes of p1 from RUNNING to WAITING and finally to FINISHED.

```systemverilog
$display("[%0t] Seeking status:",$time);

fork:FORK_F1
  begin:BEGIN_B2
    p1 = process :: self();
    #1;
    $display("[%0t] I am in process p1",$time);
    $display("[%0t] Initial status of p1: %s",$time,p1.status());
    $display("[%0t] Status of p1 before await: %s",$time,p1.status());

    if(p1.status() != process :: FINISHED)
      p2.await();
  end:BEGIN_B2

  #2;
  $display("[%0t] Status of p1 after await: %s",$time,p1.status());

  begin:BEGIN_B4
    p2 = process :: self();
    #1;
    $display("[%0t] I am in process p2",$time);
    $display("[%0t] Initial status of p2: %s",$time,p2.status());
    #2 ->e2;
  end:BEGIN_B4

  begin:BEGIN_B5
    wait(e2.triggered);
    $display("[%0t] Final status of p2: %s",$time,p2.status());
    ->e1;
  end:BEGIN_B5

  begin:BEGIN_B6
    wait(e1.triggered);
    $display("[%0t] Final status of p1: %s",$time,p1.status());
  end:BEGIN_B6
join_any:FORK_F1
```

--------------------------------

### SystemVerilog Employee Details Packed Structure Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/03.Structure-and-Union

An example of a packed structure named 'employee_details_s' containing a byte, a 8-bit bit, and a 16-bit logic. Packed structures minimize memory footprint.

```systemverilog
typedef struct packed{
        byte id;
        bit[7:0]experience;
        logic[15:0]salary;
}employee_ details_s;
```

--------------------------------

### SystemVerilog Syntax for Goto Repetitions Bin

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Illustrates the syntax for defining a coverpoint with a goto repetitions bin, specifying a transition with a repeat range.

```systemverilog
coverpoint_name: cover-point variable {bins bin 1[] = (transition_item[->repeat_range]); }
```

--------------------------------

### SystemVerilog Parameterized Class Example (by Value)

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/15.Classes-and-oops

Demonstrates a SystemVerilog class 'mirafra' parameterized by 'branch' and 'employes' values. It shows instantiation and usage of the parameterized class with specific values for the parameters.

```systemverilog
class mirafra #(parameter branch,employes);
  bit [branch-1:0]b1;
  bit [employes-1:0]b2;
 
  function new();
    b1=13;
    b2=9;
  endfunction

  function void disp();
    $display("b1=%0d,b2=%0d",b1,b2);
  endfunction

endclass:mirafra
 
mirafra#(3,2) m;
module value;
  initial begin:BEGIN_I
    m=new();
    $display("");
    $display("contents of m ");
    m.disp();
    $display("");
  end:BEGIN_I

endmodule:value
```

--------------------------------

### SystemVerilog Virtual Task Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/15.Classes-and-oops

Illustrates the use of virtual tasks, which are similar to virtual functions but support timing constructs. The example shows how a virtual task in a base class can be overridden in derived classes.

```systemverilog
class packet;
  string a;
  int b;

  virtual task  display();
    a="Team";
    b=4;
    $display("a=%0s",a);
    $display("b=%0d",b);
  endtask 
endclass//class 1

//-----class 2-------
class pack extends packet;
  string c;
  int d;

  task display();
    c="BJT";
    d=8;
    $display("c=%0s",c);
    $display("d=%0d",d);
  endtask

endclass//class 2

packet p1;
pack p2;

module virtual_task;

  initial begin:BEGIN_I
    p2=new();
    p1=p2;
    $display("contents of p1");
    p1.display();
  end:BEGIN_I

endmodule:virtual_task
```

--------------------------------

### SystemVerilog Dynamic Array Initialization and Iteration

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/Choosing-an-array

Demonstrates how to declare, allocate memory for, initialize, and iterate through a dynamic array in SystemVerilog using the new() method and a foreach loop.

```systemverilog
module dynamic;
        int dyn [];
        initial begin
          dyn = new[8];
          dyn = '{2,7,0,6,1,9,9,7};
          foreach(dyn[i])begin
            $display("verifying the values of each index, dyn[%0d] = %0d", i, dyn[i]);
          end
        end
      endmodule 
```

--------------------------------

### Sequential Immediate Assertions Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/18.Assertion

An example of using sequential immediate assertions within an always block sensitive to the positive edge of a clock. It checks multiple conditions for A and B, displaying messages for failures and success.

```systemverilog
always @(posedge clk) begin 
  assert (A==0 && B==0) $display("%0t, A=0 and B=0, assertion failed\n",$time);

  else assert (A==0 && B==1) $display("%0t, A=0 and B=1, assertion failed\n",$time);

  else assert (A==1 && B==0) $display("%0t, A=1 and B=0, assertion failed\n",$time);

  else assert (A==1 && B==1) $display("%0t, A=1 and B=1,assertion Success\n",$time);

  else $display("%0t fail\n",$time);
end
```

--------------------------------

### SystemVerilog do-while Loop Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/09.Loops

Demonstrates the do-while loop, which executes statements once before checking the condition. Ensure the condition eventually becomes false to avoid an infinite loop.

```systemverilog
int apple = 1; //int data type and variable name is apple
initial begin //procedural block
  $display("------do while output ---");
  do //do statements
  begin
    $display("\t Value of apple = %0d", apple);
    apple = apple +1;
  end      
  while(apple<6);   //while loop condition    
end     
```

--------------------------------

### SystemVerilog Typedef Enum Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/04.User-defined

An example demonstrating the practical application of 'typedef enum' to define an enumeration type 'pen_e' with specific values. This avoids syntax errors when multiple variables need to share these values.

```systemverilog
typedef enum { 
RORITO,
FLAIRFX,
REYNOLDS
}pen_e;
```

--------------------------------

### SystemVerilog Queue with Push Operation

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/Interview-question-and-answers

Shows how to use a queue in SystemVerilog with the push_back() method to add elements. The foreach loop iterates and displays elements, including newly added ones.

```systemverilog
     module queue;
       int que[$];
       initial begin
         que = '{2,7,0,6,1,9,9,7};
         foreach(que[i])begin
           $display("verifying the values of each index, que[%0d] = %0d", i, que[i]);
           que.push_back(6);
         end
       end
     endmodule 

```

--------------------------------

### SystemVerilog Example of Clock Edge Triggered Cover Group

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Illustrates a practical implementation of a cover group triggered by the positive edge of a clock signal. This example shows how to define cover points 'a' and 'b' and associate them with a clock.

```systemverilog
bit clk;
always #5 clk=~clk;
covergroup cvgp @ (posedge clk);
  c1: coverpoint a;
  c2: coverpoint b;
endgroup
```

--------------------------------

### Control Cover Group Instances with Start and Stop

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/17.Functional-Coverage

Use the `start()` and `stop()` methods on a cover group instance to control when coverage collection is active. This is useful for conditionally enabling or disabling coverage based on certain criteria.

```systemverilog
Covergroup_name cg_inst = new;
initial begin
    if(condition)
       cg_inst.stop();
    else
       cg_inst.start();
    end
```

```systemverilog
class samp;
  randc bit [2:0] a;
  randc bit b;
endclass

samp s;

covergroup cgrp;
  c1: coverpoint s.a;
  c2: coverpoint s.b;
endgroup

cgrp c;

module cvgrp_start_stop;
  initial begin
    s = new;
    c = new();
    for (int i = 0; i < 5; i++) begin
      void'(s.randomize());
      c.sample();
      $display("a=%d ; b=%d ; coverage = %0.2f", s.a, s.b, c.get_inst_coverage());

      if (c.get_inst_coverage() > 65) begin
        c.stop;
        $display("If coverage%% is greater than 65%%, stop executing covergroup");
      end
      //if (c.get_inst_coverage() < 30) begin
      // c.start(); // Restart coverage collection if it drops below 30%
      // $display("If coverage%% is less than 30%%, restart executing covergroup")
      //end
  end
endmodule
```

--------------------------------

### SystemVerilog Inverted Inside Constraint Example

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/14.Constraint

This example demonstrates how to use the inverted inside constraint to ensure a random variable's value falls outside a specified range. The random values generated will not be between 3 and 9, inclusive.

```systemverilog
class PQR;
  rand bit [3:0] var2;
  constraint C1 { !(var2 inside {[3:9}); }
endclass

module top;
  initial begin
    int i;
    PQR pqr;
    pqr = new();

    $display("----- Output for invert inside constraint -----");

    for (int i = 1; i < 7; i++) begin
      void'(pqr.randomize());
      $display("[%0t] @ iteration: %0d -----> var2 = %0d", $time, i, pqr.var2);
    end
  end
endmodule
```

--------------------------------

### SystemVerilog Array Initialization

Source: https://github.com/mbits-mirafra/systemverilogcourse/wiki/02.Array

Initializes an array with eight elements for demonstrating ordering methods.

```systemverilog
array[8] : {2,7,1,9,9,7,0,6}
```