### Copy Example Setup Script

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/otbn/pre_syn/README_MAI.md

Copy the example setup script to a new file for local configuration. This script is automatically read by the main synthesis script.

```bash
cp syn_setup_mai.example.sh syn_setup_sec_add.sh
```

--------------------------------

### Install Dependencies and Run Help (Developer)

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/README.md

For developers working on multiple clones, install dependencies and view run script help. This is a one-time setup.

```bash
pip3 install -r requirements.txt    # install dependencies (only once)
python3 run.py --help
```

--------------------------------

### Programmer's Guide Initialization Example

Source: https://github.com/lowrisc/opentitan/blob/master/doc/contributing/doc/example_ip_block.md

This C code snippet from the Programmer's Guide demonstrates a conditional initialization sequence for an IP block.

```c
 if (...) {
   a = ...
 }

```

--------------------------------

### Configure and Build Spike Simulator

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/README.md

Configure and build the Spike ISA simulator with commit log and misaligned access support, installing it to a specified prefix. Ensure the PKG_CONFIG_PATH is set to include the Spike libraries for the co-simulation setup.

```bash
../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim
sudo make -j8 install
export PKG_CONFIG_PATH=/opt/spike-cosim/lib/pkgconfig:$PKG_CONFIG_PATH
```

--------------------------------

### Constfile Unsupported Example

Source: https://github.com/lowrisc/opentitan/blob/master/hw/top_darjeeling/dv/cov/constfile.txt

Illustrates an example of an instance declaration that is currently unsupported. This syntax may be used in future versions.

```systemverilog
instance {tb.dut.top_darjeeling.u_pinmux_aon} {mio_attr_o[0][8:4]}   {5'b00000}
```

--------------------------------

### Example Bazel Command with Override

Source: https://github.com/lowrisc/opentitan/blob/master/third_party/qemu/README.md

An example of how to use the --override_repository argument with a Bazel cquery command.

```bash
./bazelisk.sh cquery --override_repository=... @qemu_opentitan//:build/qemu-system-riscv32
```

--------------------------------

### Installing Target-Specific Standard Library

Source: https://github.com/lowrisc/opentitan/blob/master/doc/rust_for_c_devs.md

When using a target that differs from the host target, install the corresponding standard library build using `rustup component install`. For example, `rustup component install rust-std-<target>`.

```bash
rustup component install rust-std-<target>
```

--------------------------------

### Bootstrap Demo Software

Source: https://github.com/lowrisc/opentitan/blob/master/doc/getting_started/setup_fpga.md

Load the 'hello_world' demo software onto the FPGA after the bitstream has been flashed. This command bootstraps the specified binary.

```bash
bazel run //sw/host/opentitantool -- bootstrap $(ci/scripts/target-location.sh //sw/device/examples/hello_world:hello_world_fpga_${BOARD}_bin)
```

--------------------------------

### Build and Load Software onto FPGA

Source: https://github.com/lowrisc/opentitan/blob/master/doc/contributing/fpga/ref_manual_fpga.md

Builds the hello_world example and loads it onto the FPGA using opentitantool. The set-pll command needs to be run only once.

```console
$ cd ${REPO_TOP}
$ bazel run //sw/host/opentitantool fpga set-pll # This needs to be done only once.
$ bazel build //sw/device/examples/hello_world:hello_world_fpga_cw340_bin
$ bazel run //sw/host/opentitantool bootstrap $(ci/scripts/target-location.sh //sw/device/examples/hello_world:hello_world_fpga_cw340_bin)
```

--------------------------------

### Setup Synthesis Environment

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/aes/pre_syn/README.md

Source this script to set up environment variables and the output directory for synthesis. Ensure the provided path points to the synthesis output.

```bash
$ source syn_setup.sh syn_out_06_01_2020_11_19_15/
```

--------------------------------

### Calculate Minimum TSU_STA Timing Parameter

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/i2c/doc/programmers_guide.md

Calculates the minimum TSU_STA (Setup time for START condition) in clock cycles. This ensures the START condition is stable before the clock is released.

```c
TSU_STA_MIN = ceil(t_SU_STA_min / t_clk)
```

--------------------------------

### Start Parallel Benchmarking

Source: https://github.com/lowrisc/opentitan/blob/master/sw/vendor/eembc_coremark/docs/html/index/Functions.html

Initiates benchmarking in a parallel execution context. This function is part of the parallel execution setup.

```c
Start benchmarking in a parallel context.
```

--------------------------------

### Serve Documentation Locally

Source: https://github.com/lowrisc/opentitan/blob/master/doc/contributing/doc/README.md

Build and preview the documentation locally by running this script from the repository root. Ensure you have read the markdown style guide before contributing.

```sh
./util/site/build-docs.sh serve
```

--------------------------------

### Add CSR Exclusion Example

Source: https://github.com/lowrisc/opentitan/blob/master/hw/dv/sv/csr_utils/README.md

Demonstrates how to add an exclusion for CSRs or fields starting with 'key' to prevent writes. This uses glob-style matching for the scope.

```systemverilog
csr_excl.add_excl({scope, ".", "key?"}, CsrExclWrite);
```

--------------------------------

### Clone Repositories and Set Up Environment

Source: https://github.com/lowrisc/opentitan/blob/master/hw/dv/tools/z01x/README.md

Clone the necessary repositories and set environment variables for Z01X fault injection simulation. Ensure paths are correctly set before proceeding.

```bash
$ git clone git@github.com:lowRISC/opentitan_fi_z01x.git
$ git clone git@github.com:lowRISC/opentitan.git
$ export Z01X_DIR=<path to the opentitan_fi_z01x directory>
$ export OT_DIR=<path to the opentitan directory>
```

--------------------------------

### Sample .bashrc Setup for RISC-V Toolchain

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/docs/source/extension_support.rst

Configure environment variables for RISC-V GCC, objcopy, and spike simulator paths. Ensure RISCV_TOOLCHAIN points to your GCC installation directory.

```bash
export RISCV_TOOLCHAIN=<riscv_gcc_install_path>
export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc"
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy"
export SPIKE_PATH="$RISCV_TOOLCHAIN/bin"
```

--------------------------------

### Setup Local QEMU Checkout for Bazel

Source: https://github.com/lowrisc/opentitan/blob/master/third_party/qemu/README.md

Run these commands once at the root of your QEMU checkout to link it with the OpenTitan build system.

```bash
# Run the following commands at the root of your QEMU checkout.
touch REPO.bazel
ln -s "/path/to/your/opentitan/repo/third_party/qemu/BUILD.qemu_opentitan.bazel" "BUILD.bazel"
```

--------------------------------

### Build and Run UART Smoketest with Verilator

Source: https://github.com/lowrisc/opentitan/blob/master/doc/getting_started/build_sw.md

Use this command to install Bazel, build the software, and run a single test with Verilator. This is a good first step to verify your OpenTitan setup.

```bash
$REPO_TOP/bazelisk.sh test --test_output=streamed --disk_cache=~/bazel_cache //sw/device/tests:uart_smoketest_sim_verilator
```

--------------------------------

### ISS Integration Example

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/docs/source/configuration.rst

This example shows how to add a new Instruction Set Simulator (ISS) by defining its name, path, and command in the `iss.yaml` file.

```yaml
- iss: new_iss_name
  path_var: ISS_PATH
  cmd: >
```

--------------------------------

### Build and Run OpenTitanTool

Source: https://github.com/lowrisc/opentitan/blob/master/sw/host/opentitantool/README.md

Build the OpenTitanTool using Bazel and run it with the 'help' command to see available options.

```sh
bazel build //sw/host/opentitantool
```

```sh
bazel run //sw/host/opentitantool -- help
```

--------------------------------

### OTBN Program for Modular Arithmetic

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/otbn/doc/developers_guide.md

An example OTBN program that computes (a + b << 16) mod m. Execution starts from the .text.start label. Use bn.lid for wide-register loads and bn.sid for wide-register stores. The loopi instruction is used for modular doubling.

```armasm
.section .text.start
main:
  /* Load the operands.
       w10 <= dmem[input_a]
       w11 <= dmem[input_b] */
  la        x2, input_a
  li        x3, 10
  bn.lid    x3++, 0(x2)
  la        x2, input_b
  bn.lid    x3++, 0(x2)

  /* Load the modulus and write it to the MOD register.
       MOD <= dmem[input_m] */
  la        x2, input_m
  bn.lid    x3, 0(x2)
  bn.wsrw   0x0, w12 /* special register 0 = MOD */

  /* Compute (b << 16) mod m by repeatedly doubling b.

     Loop invariants at start of loop (i=0..15):
       w11 = (b << i) mod m */
  loopi     16, 1
    bn.addm   w11, w11, w22

  /* Add to the first operand.
       w10 <= (w10 + w11) mod m = (a + b << 16) mod m */
  bn.addm   w10, w10, w11

  /* Store the result. */
  la        x2, result
  li        x3, 10
  bn.sid    x3, 0(x2)

  /* End the program. */
  ecall

.bss

/* Input buffer for the first operand, a (256 bits). */
input_a:
.zero 32

/* Input buffer for the second operand, b (256 bits). */
input_b:
.zero 32

/* Input buffer for the modulus (256 bits). */
input_m:
.zero 32

/* Output buffer. */
result:
.zero 32

```

--------------------------------

### Install Verilator from Source

Source: https://github.com/lowrisc/opentitan/blob/master/doc/getting_started/setup_verilator.md

Installs Verilator version 4.210 using GCC 11. Ensure GCC 12 or later is not used for this specific version. The installation is configured with a prefix and then installed.

```bash
sudo apt install gcc-11 g++-11

export VERILATOR_VERSION={{#tool-version verilator }}

git clone https://github.com/verilator/verilator.git
cd verilator
git checkout v$VERILATOR_VERSION

autoconf
CC=gcc-11 CXX=g++-11 ./configure --prefix=/tools/verilator/$VERILATOR_VERSION
CC=gcc-11 CXX=g++-11 make
sudo CC=gcc-11 CXX=g++-11 make install
```

--------------------------------

### Install Prerequisites with apt-get and pip

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/dv/riscv_compliance/README.md

Installs necessary tools like srecord and fusesoc for compiling and running the simulation. Ensure Python 3 and pip are available.

```sh
sudo apt-get install srecord python3-pip
pip3 install --user -U fusesoc
```

--------------------------------

### Install Required Packages

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/pygen/experimental/README.md

Installs the necessary Python packages for the RISC-V DV generator. Ensure you have pip3 installed.

```bash
pip3 install python-constraint
pip3 install numpy
pip3 install bitstring
```

--------------------------------

### Set Up Python Virtual Environment

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/aes/pre_sca/alma_post_syn/README.md

Navigate to the CocoAlma directory, create, activate a Python virtual environment, and install dependencies.

```sh
cd coco-alma
python3 -m venv dev
source dev/bin/activate
pip3 install -r requirements.txt
```

--------------------------------

### Install yapf and isort with pip

Source: https://github.com/lowrisc/opentitan/blob/master/doc/contributing/style_guides/python_coding_style.md

Install the yapf and isort Python packages using pip3. The --user flag installs them for the current user.

```console
$ pip3 install --user yapf
$ pip3 install --user isort
```

--------------------------------

### Open Existing FPGA Project in Vivado GUI

Source: https://github.com/lowrisc/opentitan/blob/master/doc/getting_started/setup_fpga.md

Launch the Vivado GUI with the generated project. Ensure Vivado is sourced correctly.

```bash
. /tools/Xilinx/Vivado/{{#tool-version vivado }}/settings64.sh
cd $REPO_TOP
make -C $(dirname $(find bazel-out/* -wholename '*synth-vivado/Makefile')) build-gui
```

--------------------------------

### SETUP Transaction Enable Bits

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/usbdev/doc/registers.md

These bits control whether SETUP transactions are enabled for reception on specific endpoints. Setting a bit enables SETUP transactions for the corresponding endpoint; clearing it will cause SETUP packets to be ignored. These bits should only be set for control endpoints.

```APIDOC
## Fields

### setup_11

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 11
- **Type**: rw
- **Reset**: 0x0

### setup_10

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 10
- **Type**: rw
- **Reset**: 0x0

### setup_9

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 9
- **Type**: rw
- **Reset**: 0x0

### setup_8

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 8
- **Type**: rw
- **Reset**: 0x0

### setup_7

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 7
- **Type**: rw
- **Reset**: 0x0

### setup_6

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 6
- **Type**: rw
- **Reset**: 0x0

### setup_5

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 5
- **Type**: rw
- **Reset**: 0x0

### setup_4

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 4
- **Type**: rw
- **Reset**: 0x0

### setup_3

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 3
- **Type**: rw
- **Reset**: 0x0

### setup_2

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 2
- **Type**: rw
- **Reset**: 0x0

### setup_1

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 1
- **Type**: rw
- **Reset**: 0x0

### setup_0

- **Description**: This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).
- **Bits**: 0
- **Type**: rw
- **Reset**: 0x0
```

--------------------------------

### Create a stub AST initialization library

Source: https://github.com/lowrisc/opentitan/blob/master/hw/top/doc/top_desc.md

This example demonstrates creating a stub implementation for `ast_init` and a corresponding `cc_library` target.

```c
// In sw/device/lib/testing/test_rom/ast_lib_stub.c

void ast_init(void) {
  // Stub: does nothing.
}
```

```python
# In sw/device/lib/testing/test_rom/BUILD
cc_library(
    name = "ast_lib_stub",
    srcs = ["ast_lib_stub.c"],
)
```

--------------------------------

### SystemVerilog Package Example

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/keymgr/dv/README.md

Illustrates common types and methods defined at the package level within the keymgr_env_pkg. These are frequently used in test sequences.

```systemverilog
keymgr_env_pkg;
```

--------------------------------

### Install System Dependencies on Ubuntu

Source: https://github.com/lowrisc/opentitan/blob/master/doc/getting_started/README.md

Installs required system packages using apt on Ubuntu 20.04. This command filters out comments from the requirements file before installation.

```bash
sed '/^#/d' ./apt-requirements.txt | xargs sudo apt install -y
```

--------------------------------

### Instantiate Ibex Core with Parameters

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/doc/02_user/integration.rst

This Verilog code shows how to instantiate the Ibex core, specifying various configuration parameters. Ensure all parameters are set according to your system's requirements.

```verilog
    .PMPEnable            ( 0                                ),
      .PMPGranularity       ( 0                                ),
      .PMPNumRegions        ( 4                                ),
      .MHPMCounterNum       ( 0                                ),
      .MHPMCounterWidth     ( 40                               ),
      .RV32E                ( 0                                ),
      .RV32M                ( ibex_pkg::RV32MFast              ),
      .RV32B                ( ibex_pkg::RV32BNone              ),
      .RV32ZC               ( ibex_pkg::RV32ZcaZcbZcmp         ),
      .RegFile              ( ibex_pkg::RegFileFF              ),
      .ICache               ( 0                                ),
      .ICacheECC            ( 0                                ),
      .ICacheTweakInfection ( 0                                ),
      .ICacheScramble       ( 0                                ),
      .BranchPrediction     ( 0                                ),
      .SecureIbex           ( 0                                ),
      .RndCnstLfsrSeed      ( ibex_pkg::RndCnstLfsrSeedDefault ),
      .RndCnstLfsrPerm      ( ibex_pkg::RndCnstLfsrPermDefault ),
      .DbgTriggerEn         ( 0                                ),
      .DmBaseAddr           ( 32'h1A110000                     ),
      .DmAddrMask           ( 32'h00000FFF                     ),
      .DmHaltAddr           ( 32'h1A110800                     ),
      .DmExceptionAddr      ( 32'h1A110808                     )
  ) u_top (
      // Clock and reset
      .clk_i                    (),
      .rst_ni                   (),
      .test_en_i                (),
      .scan_rst_ni              (),
      .ram_cfg_i                (),

      // Configuration
      .hart_id_i                (),
      .boot_addr_i              (),

      // Instruction memory interface
      .instr_req_o              (),
      .instr_gnt_i              (),
      .instr_rvalid_i           (),
      .instr_addr_o             (),
      .instr_rdata_i            (),
      .instr_rdata_intg_i       (),
      .instr_err_i              (),

      // Data memory interface
      .data_req_o               (),
      .data_gnt_i               (),
      .data_rvalid_i            (),
      .data_we_o                (),
      .data_be_o                (),
      .data_addr_o              (),
      .data_wdata_o             (),
      .data_wdata_intg_o        (),
      .data_rdata_i             (),
      .data_rdata_intg_i        (),
      .data_err_i               (),

      // Interrupt inputs
      .irq_software_i           (),
      .irq_timer_i              (),
      .irq_external_i           (),
      .irq_fast_i               (),
      .irq_nm_i                 (),

      // Debug interface
      .debug_req_i              (),
      .crash_dump_o             (),

      // Special control signals
      .fetch_enable_i           (),
      .alert_minor_o            (),
      .alert_major_internal_o   (),
      .alert_major_bus_o        (),
      .core_sleep_o             (),

      // Lockstep signals
      .lockstep_cmp_en_o        (),

      // Shadow core data interface outputs
      .data_req_shadow_o        (),
      .data_we_shadow_o         (),
      .data_be_shadow_o         (),
      .data_addr_shadow_o       (),
      .data_wdata_shadow_o      (),
      .data_wdata_intg_shadow_o (),

      // Shadow core instruction interface outputs
      .instr_req_shadow_o       (),
      .instr_addr_shadow_o      ()
  );
```

--------------------------------

### Install RISCV-DV as a Python Package

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/docs/source/getting_started.rst

For general users, install RISCV-DV as a Python package. Add the local bin directory to your PATH and then install the package in editable mode.

```bash
export PATH=$HOME/.local/bin/:$PATH
```

```bash
pip3 install --user -e .
```

```bash
run --help
```

```bash
cov --help
```

--------------------------------

### I2C Timing Parameter Calculation Examples

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/i2c/doc/programmers_guide.md

Examples for calculating timing register parameters for Fast-mode Plus devices. These examples assume specific datarates and clock periods.

```text
TIMING0.THIGH   | 260              | 120        | 360            | Chosen to satisfy SCL Period Minimum          
TIMING0.TLOW    | 500              | 167        | 501            | Spec. t<sub>LOW</sub> Minimum                 
TIMING1.T_F     | 20ns * (VDD/5.5V)| 7          | 21             | Signal slew-rate should be controlled         
TIMING1.T_R     | 0                | 40         | 120            | Based on pull-up resistance, line capacitance 
SCL Period      | 1000             | N/A        | 1002           | Constraint on THIGH+TLOW+T_R+T_F              
TIMING2.THD_STA | 260              | 87         | 261            | Spec. Minimum                                 
TIMING2.TSU_STA | 260              | 87         | 261            | Spec. Minimum                                 
TIMING3.THD_DAT | 0                | 0          | 0              | Spec. Minimum                                 
TIMING3.TSU_DAT | 260              | 87         | 261            | Spec. Minimum                                 
TIMING4.T_BUF   | 500              | 167        | 501            | Spec. Minimum                                 
TIMING4.T_STO   | 260              | 87         | 161            | Spec. Minimum                                 
```

```text
TIMING0.THIGH   | 260              | 87         | 261            | Spec. t<sub>HIGH</sub> Minimum                
TIMING0.TLOW    | 500              | 167        | 501            | Spec. t<sub>LOW</sub> Minimum                 
TIMING1.T_F     | 20ns * (VDD/5.5V)| 7          | 21             | Signal slew-rate should be controlled         
TIMING1.T_R     | 0                | 134        | 402            | Atypically high line capacitance             
SCL Period      | 1000             | N/A        | 1185           | Forced longer than minimum by long T_R        
```

--------------------------------

### ePMP Configuration Example

Source: https://github.com/lowrisc/opentitan/blob/master/sw/device/silicon_creator/rom_ext/doc/si_val.md

This console output shows an example of how the SiVal ROM_EXT configures the ePMP. It details memory region lockouts and access permissions for various components.

```console
 0: 40130000 NAPOT L--- sz=00001000     ; OTP MMIO lockout.
 1: 40480000 NAPOT L--- sz=00000400     ; AST MMIO lockout.
 2: 20010400 ----- ---- sz=00000000     ; OWNER code start.
 3: 20013cac   TOR -X-R sz=000038ac     ; OWNER code end.
 4: 00000000 ----- ---- sz=00000000     ; OWNER data (if using remap window, else unused).
 5: 00000000 ----- ---- sz=00000000
 6: 00000000 ----- ---- sz=00000000
 7: 00000000 ----- ---- sz=00000000
 8: 00000000 ----- ---- sz=00000000
 9: 00000000 ----- ---- sz=00000000
10: 20000400 ----- ---- sz=00000000     ; ROM_EXT code start.
11: 20005bc8   TOR -X-R sz=000057c8     ; ROM_EXT code end.
12: 20000000 NAPOT ---R sz=00100000     ; FLASH data (1 MB).
13: 00010000 NAPOT -XWR sz=00001000     ; RvDM region (not PROD, RMA/DEV only).
14: 40000000 NAPOT --WR sz=10000000     ; MMIO region.
15: 10000000 NAPOT --WR sz=00020000     ; RAM region.
mseccfg = 00000002                      ; RLB=0, MMWP=1, MML=0.
```

--------------------------------

### SystemVerilog Package Example

Source: https://github.com/lowrisc/opentitan/blob/master/hw/dv/doc/dv_doc_template.md

Illustrates common types and methods defined at the package level in `foo_env_pkg`. These are frequently used by test sequences.

```systemverilog
class foo_env_pkg extends uvm_pkg;
  // ...
endpackage

```

--------------------------------

### USB Device SETUP Transaction Enable Fields

Source: https://github.com/lowrisc/opentitan/blob/master/hw/ip/usbdev/doc/registers.md

These bits control the reception of SETUP transactions on the endpoint. They should be set for control endpoints only. If a bit is clear, the SETUP packet will be ignored.

```wavejson
{"reg": [{"name": "setup_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_9", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_10", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "setup_11", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
```

--------------------------------

### Install Dependencies

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/pygen/pygen_src/README.md

Install the necessary Python dependencies for RISCV-DV-PyFlow using pip.

```bash
pip3 install -r requirements.txt    # install dependencies (only once)
```

--------------------------------

### Get Help for Ibex Configuration Tool

Source: https://github.com/lowrisc/opentitan/blob/master/hw/vendor/lowrisc_ibex/doc/02_user/configuration.rst

Display help information for the `ibex_config.py` tool. This is useful for understanding available command-line options and usage.

```bash
# Get help on using ibex_config.py
./util/ibex_config.py -h
```