### Build TabGen Tool

Source: https://github.com/jitx-inc/jsl/blob/main/tabgen/README.md

Run 'make' to build the TabGen tool. This is the initial setup step.

```bash
$> make
```

--------------------------------

### Example CSV Data

Source: https://github.com/jitx-inc/jsl/blob/main/tabgen/README.md

This is an example of the CSV file format expected by TabGen. Ensure fields do not contain commas.

```csv
"Name", "Length", "Width", "Lead-Length", "Lead-Width", "Aliases"
"009005", 0.3 +/- 0.01, 0.15 +/- 0.01, 0.11 +/- 0.01, 0.15 +/- 0.01, "0301m"
"01005", 0.4 +/- 0.02, 0.2 +/- 0.02, 0.1 +/- 0.03, 0.2 +/- 0.02, "0402m"
"0201", 0.6 +/- 0.03, 0.3 +/- 0.03, 0.15 +/- 0.05, 0.3 +/- 0.03, "0603m"
"0202", 0.6 +/- 0.03, 0.6 +/- 0.03, 0.15 +/- 0.05, 0.6 +/- 0.03, "0606m"
...
```

--------------------------------

### Generated Stanza Table Structure

Source: https://github.com/jitx-inc/jsl/blob/main/tabgen/README.md

This is an example of the Stanza table generated by TabGen from a CSV file. It includes package definition, imports, header, and row data.

```stanza
; Auto-Generated File created by 'tabgen'
; Do not manually edit this file.
defpackage jsl/landpatterns/two-pin-table:
  import core
  import jitx

val header:Tuple<String> = ["Name",  "Length",  "Width",  "Lead-Length",  "Lead-Width",  "Aliases"]
val rows:Tuple = [
  [  "009005",     0.3 +/- 0.01,    0.15 +/- 0.01,     0.11 +/- 0.01,    0.15 +/- 0.01,             "0301m"]
  [   "01005",     0.4 +/- 0.02,     0.2 +/- 0.02,      0.1 +/- 0.03,     0.2 +/- 0.02,             "0402m"]
  [    "0201",     0.6 +/- 0.03,     0.3 +/- 0.03,     0.15 +/- 0.05,     0.3 +/- 0.03,             "0603m"]
  [    "0202",     0.6 +/- 0.03,     0.6 +/- 0.03,     0.15 +/- 0.05,     0.6 +/- 0.03,             "0606m"]
  ...
]
```

--------------------------------

### Instantiate and Connect Quad AND Gates in a PCB Module

Source: https://context7.com/jitx-inc/jsl/llms.txt

Creates a test design module that instantiates the QuadAND component and connects two of its gates. Use this to test component functionality and connectivity.

```stanza
pcb-module test-design:
  inst U1 : QuadAND
  place(U1) at loc(0.0, 0.0) on Top

  require G1 : gate(2) from U1
  require G2 : gate(2) from U1

  net (G1.out, G2.in[1])   ; chain gates together

set-current-design("QuadAND-Test")
set-rules(default-rules)
set-board(default-board(RoundedRectangle(50.0, 50.0, 0.25)))
set-main-module(test-design)
view-board()
view-schematic()

```

--------------------------------

### Define Layer Stackup with add-symmetric

Source: https://context7.com/jitx-inc/jsl/llms.txt

Constructs a symmetric PCB layer stackup using the `add-symmetric` function for more granular control over layer placement. Requires manual definition of each layer pair.

```Stanza
#use-added-syntax(jitx)
; Using add-symmetric for more control
val stack6 = LayerStack(name = "6-Layer Symmetric")
val cu-35  = Copper(0.035)
val core-fr4 = FR4(1.0)
val pp-fr4   = FR4(0.5)
add-symmetric(cu-35, core-fr4,
  add-symmetric(cu-35, pp-fr4,
    add-symmetric(cu-35, core-fr4, stack6)))
```

--------------------------------

### create-circuit

Source: https://context7.com/jitx-inc/jsl/llms.txt

Builds a `pcb-module` from an Abstract Network Tree (ANT). Networks are composed using `+` (series), `|` (parallel), `Tap` (expose an internal node as a port), `ShuntTo` (connect a node to an external port through a component), and `~` (invert polarity).

```APIDOC
## create-circuit

### Description
Builds a `pcb-module` from an Abstract Network Tree (ANT). Networks are composed using `+` (series), `|` (parallel), `Tap` (expose an internal node as a port), `ShuntTo` (connect a node to an external port through a component), and `~` (invert polarity).

### Method
Stanza DSL function call

### Parameters
- **network_tree** (ANT) - Required - The Abstract Network Tree defining the circuit.

### Request Example
```stanza
val R1 = create-resistor(resistance = 10.0e3)
val R2 = create-resistor(resistance = 10.0e3)

val divider = create-circuit(
  Elem(R1) + Tap(`divOut, R2)
)

pc b-module my-filter:
  inst div  : divider
```
```

--------------------------------

### Define Layer Stackup with make-layer-stack

Source: https://context7.com/jitx-inc/jsl/llms.txt

Builds a 4-layer symmetric PCB stackup using the `make-layer-stack` helper function. Specify copper and dielectric layers for core and prepreg.

```Stanza
#use-added-syntax(jitx)
; Build a 4-layer symmetric stackup with soldermask
val copper-35um   = Copper(0.035, name = "signal")
val copper-17um   = Copper(0.0175, name = "plane")
val prepreg       = FR4(0.1, name = "prepreg")
val core          = FR4(1.265, name = "core")
val sm            = Soldermask(0.019)

; Using make-layer-stack (convenient 4-layer API)
val jlcpcb-4L = make-layer-stack(
  "JLCPCB 4-layer 1.6mm",
  [
    [copper-35um, prepreg],
    [copper-17um, core]
  ],
  soldermask = sm
)
; Resulting stackup (top to bottom):
;   soldermask / copper-35um / prepreg / copper-17um /
;   core / copper-17um / prepreg / copper-35um / soldermask
```

--------------------------------

### Run JSL Unit Tests with Tag

Source: https://github.com/jitx-inc/jsl/blob/main/README.md

Execute all unit tests associated with a specific tag, such as 'SOIC'. This command filters out skipped tests and formats the output for readability.

```bash
$> make test-SOIC
/Users/callendorph/.jitx/current/jstanza run-test jsl/tests/landpatterns/numbering ...  -tagged SOIC | grep -v "SKIP" | awk NF
[Test 21] test-lead
[PASS]
[Test 22] test-body
[PASS]
[Test 23] test-SOIC-N
[PASS]
[Test 24] test-SOIC-W
[PASS]
[Test 25] test-fine-pitch
[PASS]
[Test 26] test-thermal-lead
[PASS]
[Test 27] test-pad-numbering
[PASS]
[Test 28] test-error-handling
[PASS]
[Test 29] test-SOIC-with-pose
[PASS]
[Test 30] test-SOIC-with-rotation
[PASS]
[Test 31] test-thermal-lead-with-pose
[PASS]
Tests Finished: 11/111 tests passed. 100 tests skipped. 0 tests failed.
Longest Running Tests:
[PASS] test-SOIC-N (36 ms)
[PASS] test-fine-pitch (26 ms)
[PASS] test-SOIC-W (10 ms)
[PASS] test-thermal-lead (6181 us)
[PASS] test-thermal-lead-with-pose (5226 us)
[PASS] test-SOIC-with-pose (4847 us)
[PASS] test-pad-numbering (4547 us)
[PASS] test-error-handling (3561 us)
[PASS] test-SOIC-with-rotation (3531 us)
[PASS] test-lead (3124 us)
[PASS] test-body (561 us)

```

--------------------------------

### Generate PCB Module for IC Configuration Straps

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `ConfigStrap` to create a PCB module for IC configuration strap resistors. The `set-straps-config` function controls BOM population based on a binary integer value.

```stanza
#use-added-syntax(jitx)
; Create a 3-bit hardware revision strap using 0402 resistors
val strap-R = create-resistor(resistance = 0.0, precision = (1 %))

val hw-rev-straps = ConfigStrap(
  num-elems = 3,
  comp      = strap-R,
  name?     = "HW-Rev-Straps"
)

pc b-module top-level-module:
  port vdd : power

  inst straps : hw-rev-straps
  net (vdd.V+, straps.hi)
  net (vdd.V-, straps.lo)

  ; Set hardware revision to binary 5 (0b101):
  ;   channel 0: high (InBOM hi, DNP lo)
  ;   channel 1: low  (DNP hi, InBOM lo)
  ;   channel 2: high (InBOM hi, DNP lo)
  set-straps-config(straps, 5)

  ; Access config pins via pin assignment
  require cfg : config-strap-bus(3) from straps
  ; cfg.config[0], cfg.config[1], cfg.config[2] are now available
```

--------------------------------

### insert-pullup / insert-pulldown

Source: https://context7.com/jitx-inc/jsl/llms.txt

Instantiates a resistor and connects it between a signal and a power rail. Accepts either a direct Instantiable component or a resistance value in ohms, using the JITX parts query API for auto-selection.

```APIDOC
## insert-pullup / insert-pulldown

### Description
Instantiate a resistor and connect it between a signal and a power rail. They accept either a direct `Instantiable` component or a resistance value in ohms, using the JITX parts query API for auto-selection.

### Method
Stanza DSL function call

### Parameters
- **signal_port** (Port) - Required - The signal port to connect the resistor to.
- **power_port** (Port) - Required - The power rail port (e.g., 3.3V) to connect the resistor to.
- **elem-type** (Instantiable or Resistance) - Required - Either a specific resistor instance or a resistance value in ohms (e.g., 4.7e3).
- **inst-name** (string) - Optional - The name to assign to the instantiated resistor.

### Request Example
```stanza
insert-pullup(sda-line, rail-3v3, elem-type = pullup-4k7, inst-name = "R-SDA-PU")
insert-pulldown(sda-line, rail-3v3)
```
```

--------------------------------

### Convert Layer Stackup to PCB Definition

Source: https://context7.com/jitx-inc/jsl/llms.txt

Converts a JSL `LayerStack` object into a JITX `pcb-stackup` definition, ready to be used in board creation.

```Stanza
#use-added-syntax(jitx)
; Convert to JITX pcb-stackup definition
val stackup-def = create-pcb-stackup(jlcpcb-4L)
; Use in your board: set-board(jlcpcb-board(board-shape, stackup-def))
```

--------------------------------

### Generate QFN Land Pattern

Source: https://context7.com/jitx-inc/jsl/llms.txt

Generates land patterns for Quad Flat No-Lead packages. Supports thermal pads, custom pad planners, and adjustable courtyards.

```Stanza
#use-added-syntax(jitx)
public pcb-component my-qfn32:
  port p : pin[[1 through 32]]
  port gnd-pad

  pin-properties:
    [pin:Ref  | pads:Int ... ]
    [p[1]     | 1            ]
    ; ...
    [gnd-pad  | 33           ]   ; thermal pad

  val pkg = QFN(
    num-leads    = 32,
    lead-profile = QFN-Lead-Profile(
      span       = min-max(4.4, 4.6),
      pitch      = 0.5,
      lead-length = min-max(0.25, 0.35),
      lead-width  = min-max(0.15, 0.25)
    ),
    thermal-lead? = Rectangle(3.2, 3.2),   ; exposed pad shape
    package-body  = PackageBody(
      width  = min-max(4.4, 4.6),
      length = min-max(4.4, 4.6),
      height = min-max(0.5, 0.8)
    ),
    pad-planner   = Corner-PadPlanner(     ; chamfered corners
      chamfered-corner-shaper(0.1),
      rect-shaper,
      8                                    ; chamfer every 8th pad at corner
    ),
    density-level = DensityLevelB
  )
  assign-landpattern $ create-landpattern(pkg)
```

--------------------------------

### Insert Pullup/Pulldown Resistors in JSL

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `insert-pullup` or `insert-pulldown` to instantiate and connect resistors. These functions accept either a direct `Instantiable` component or a resistance value in ohms, utilizing the JITX parts query API for auto-selection.

```Stanza
#use-added-syntax(jitx)
pcb-module i2c-bus-module:
  port sda-line
  port scl-line
  port rail-3v3 : power

  val pullup-4k7 = create-resistor(resistance = 4.7e3, precision = (1 %))

  ; Insert a 4.7k pullup resistor using a pre-created instantiable
  insert-pullup(sda-line, rail-3v3, elem-type = pullup-4k7, inst-name = "R-SDA-PU")
  insert-pullup(scl-line, rail-3v3, elem-type = pullup-4k7, inst-name = "R-SCL-PU")

  ; Insert a 10k pulldown using auto-query (default: 10k)
  insert-pulldown(sda-line, rail-3v3)

  ; Add connections to an already-instantiated resistor element
  inst R3 : pullup-4k7
  add-pullup(R3, sda-line, rail-3v3)
```

--------------------------------

### Generate Stanza Table from CSV

Source: https://github.com/jitx-inc/jsl/blob/main/tabgen/README.md

Use the 'tabgen generate' command to convert a CSV file to a Stanza table. The '-f' flag specifies the output file, '-pkg-name' sets the package name, and '-force' overwrites existing files.

```bash
$> tabgen generate src/landpatterns/two-pin.csv \
  -f src/landpattern/two-pin.stanza \
  -pkg-name "jsl/landpatterns/two-pin-table" \
  -force
Extraction Complete
File 'src/landpatterns/two-pin.stanza' Generated
```

--------------------------------

### Pin Assignment Support Generators

Source: https://context7.com/jitx-inc/jsl/llms.txt

Define flexible `supports` statements for component ports using `one-of`, `swappable-diff-pair`, and `add-pass-through`. Module-level helpers include `cross-bar`, `swizzle-bus`, `reversible-dual-pair`, and `connect-require-ports`.

```stanza
#use-added-syntax(jitx)
pc b-component multi-function-mcu:
  port A : pin[8]
  port B : pin[8]
  port TX-HS : diff-pair
  port RX-HS : diff-pair

  ; one-of: timer can be satisfied by A[1], B[3], or B[6]
  supports timer:
    timer.timer => one-of(self.A[1], self.B[3], self.B[6])

  ; swappable-diff-pair: P/N may be swapped (firmware-controlled)
  swappable-diff-pair(self.TX-HS.P, self.TX-HS.N)

  ; add-pass-through: bidirectional pass-through for ESD device
  add-pass-through(self.TX-HS.P, self.RX-HS.P)


pc b-module bus-fabric:
  inst mcu1 : multi-function-mcu
  inst mcu2 : multi-function-mcu

  ; cross-bar: any port in the set can satisfy any incoming connection of that bundle type
  cross-bar(mcu1.A[0], mcu1.A[1], mcu1.A[2], mcu1.A[3])

  ; swizzle-bus: rearrange a data bus with some lanes locked in place
  val swiz = swizzle-bus(mcu1.A, locked = [0, 7])
  require data-bus : swiz from mcu1

  ; reversible-dual-pair: A<=>B may swap direction
  reversible-dual-pair(mcu1.TX-HS, mcu1.RX-HS)

  ; connect-require-ports: auto-require gpio from MCU for a list of signals
  val sigs = [mcu2.A[0], mcu2.A[1], mcu2.A[2]]
  connect-require-ports(mcu1, sigs)
```

--------------------------------

### Generate SOIC Land Pattern

Source: https://context7.com/jitx-inc/jsl/llms.txt

Creates IPC-compliant land patterns for SOIC packages. Pad dimensions, courtyard, and silkscreen are derived from lead profile and density level.

```Stanza
#use-added-syntax(jitx)
public pcb-component LM324:
  manufacturer = "Texas Instruments"
  mpn = "LM324DR"
  port p : pin[[1 through 14]]
  port rail : power

  pin-properties:
    [pin:Ref | pads:Int ... | side:Dir]
    [p[1]    | 1            | Left    ]
    ; ... all 14 pins ...
    [rail.V- | 7            | Left    ]
    [rail.V+ | 14           | Right   ]

  ; Narrow SOIC-14, 1.27mm pitch, standard gull-wing leads
  val pkg = SOIC-N(
    num-leads      = 14,
    lead-span      = min-max(5.8, 6.2),
    package-length = min-max(8.55, 8.75),
    density-level  = DensityLevelB
  )
  val lp = create-landpattern(pkg)
  assign-landpattern(lp)

  ; Wide body SOIC example
  val wide-pkg = SOIC-W(
    num-leads      = 32,
    lead-span      = min-max(10.0, 10.65),
    package-length = min-max(20.9, 21.1)
  )
```

--------------------------------

### add-pullup

Source: https://context7.com/jitx-inc/jsl/llms.txt

Adds connections to an already-instantiated resistor element to function as a pullup.

```APIDOC
## add-pullup

### Description
Adds connections to an already-instantiated resistor element to function as a pullup.

### Method
Stanza DSL function call

### Parameters
- **resistor_instance** (Instantiable) - Required - The already instantiated resistor element.
- **signal_port** (Port) - Required - The signal port to connect the resistor to.
- **power_port** (Port) - Required - The power rail port (e.g., 3.3V) to connect the resistor to.

### Request Example
```stanza
inst R3 : pullup-4k7
add-pullup(R3, sda-line, rail-3v3)
```
```

--------------------------------

### Create Lumped Circuit Networks in JSL

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `create-circuit` to build a `pcb-module` from an Abstract Network Tree (ANT). Networks can be composed using series (`+`), parallel (`|`), `Tap`, `ShuntTo`, and polarity inversion (`~`).

```Stanza
#use-added-syntax(jitx)
; Voltage divider: R1 in series with R2, with a tapped midpoint output
val R1 = create-resistor(resistance = 10.0e3)
val R2 = create-resistor(resistance = 10.0e3)

; R1 + Tap(R2, `divOut) produces:
;   p[1] --R1-- O --R2-- p[2]
;                |
;                divOut
val divider = create-circuit(
  Elem(R1) + Tap(`divOut, R2)
)

; Pi filter: C1 to ground, then L, then C2 to ground
val C_filt = create-capacitor(capacitance = 100.0e-9)
val L_filt  = create-inductor(inductance  = 47.0e-9)

val pi-filter = create-circuit(
  (Elem(C_filt) | ShuntTo(Elem(C_filt), `GND1))
  + Elem(L_filt)
  + ShuntTo(Elem(C_filt), `GND2)
)

; Polarized cap in series (inverted orientation)
val C_polar = create-capacitor(capacitance = 10.0e-6)
val pi-polar = create-circuit(~Elem(C_polar) + Elem(L_filt))

pcb-module my-filter:
  inst filt : pi-filter
  inst div  : divider
  ; Access tapped node: div.divOut
```

--------------------------------

### Define a Quad AND Gate PCB Component in JSL

Source: https://context7.com/jitx-inc/jsl/llms.txt

Defines a complete PCB component for a Quad AND Gate, including manufacturer details, ports, pin properties, schematic symbols, and land pattern. Use this to create reusable component definitions.

```stanza
#use-added-syntax(jitx)
pc b-component QuadAND:
  manufacturer = "onsemi"
  mpn = "MC74HC08ADR2G"
  datasheet = "https://www.onsemi.com/pdf/datasheet/mc74hc08a-d.pdf"

  val num-circuits = 4
  port AND : gate(2)[num-circuits]   ; 4 AND gates, each with 2 inputs
  port rail : power

  pin-properties:
    [pin:Ref      | pads:Int ... | side:Dir | bank:Int]
    [AND[0].in[1] | 1            | Left     | 0       ]
    [AND[0].in[2] | 2            | Left     | 0       ]
    [AND[0].out   | 3            | Right    | 0       ]
    [AND[1].in[1] | 4            | Left     | 1       ]
    [AND[1].in[2] | 5            | Left     | 1       ]
    [AND[1].out   | 6            | Right    | 1       ]
    [AND[2].in[1] | 9            | Left     | 2       ]
    [AND[2].in[2] | 10           | Left     | 2       ]
    [AND[2].out   | 8            | Right    | 2       ]
    [AND[3].in[1] | 12           | Left     | 3       ]
    [AND[3].in[2] | 13           | Left     | 3       ]
    [AND[3].out   | 11           | Right    | 3       ]
    [rail.V-      | 7            | Left     | 4       ]
    [rail.V+      | 14           | Right    | 4       ]

  ; Per-gate AND gate schematic symbols + a box symbol for the power bank
  val gate-symbs = for i in 0 to num-circuits seq:
    i => create-symbol $ ANDGateSymbol(
      in-ref  = #R(AND[i].in)
      out-ref = #R(AND[i].out)
    )
  assign-symbols(to-tuple(cat(gate-symbs, [4 => BoxSymbol(self)])))

  ; SOIC-14N land pattern via JSL
  val pkg = SOIC-N(
    num-leads      = 14,
    lead-span      = min-max(5.8, 6.2),
    package-length = min-max(8.55, 8.75),
    density-level  = DensityLevelB
  )
  assign-landpattern(create-landpattern(pkg))

  ; Gate supports for pin assignment (gates are interchangeable)
  for i in 0 to num-circuits do:
    make-gate-supports(self.AND[i].out, self.AND[i].in[1], self.AND[i].in[2])

```

--------------------------------

### Create RC Parallel Shield Termination Module

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `shield-termination` to create an RC parallel termination module for cable shield connections. This is useful for prototype designs where the final termination strategy is not yet determined. Custom resistor and capacitor queries can be provided.

```stanza
#use-added-syntax(jitx)
; Default RC parallel termination: 0-ohm resistor + 4.7nF capacitor rated ≥50V
val term = shield-termination()

; Custom: supply your own resistor and capacitor queries
val my-R-query = set(get-default-resistor-query(), resistance = 0.0)
val my-C-query = set(get-default-capacitor-query(), rated-voltage = AtLeast(100.0))
val custom-term = shield-termination(R-query = my-R-query, C-query = my-C-query)

pc b-module connector-module:
  port SHIELD
  port GND

  inst T1 : term
  net (SHIELD, T1.SHIELD)
  net (GND,    T1.GND)
```

--------------------------------

### PCIe Transport and Constraint Bundles

Source: https://context7.com/jitx-inc/jsl/llms.txt

Define PCIe bundles for various versions and widths, including optional pins like PRSNT#. Use `PCIe-Constraint` for SI routing and `reverse-pcie-lanes` for null-modem connections.

```stanza
#use-added-syntax(jitx)
; PCIe x4 bundle with PRSNT# hot-plug detection pin
val pcie-x4 = pcie(4, PCIe-PRSNT#)
; ports: control (PEWAKE#, PERST#, CLKREQ#, PRSNT#) + data (lane[4] + refclk)

; PCIe x1 bundle, no optional pins
val pcie-x1 = pcie(1)

; Get SI skew/loss specs for PCIe Gen 3 (8 GT/s)
val [skew-g3, loss-g3] = pcie-get-skew-loss-vals(PCIE-V3)
; skew-g3 = 0.0 +/- 1.0e-12 (seconds), loss-g3 = 10.3 (dB)

; Trace impedance for Gen 4 (85Ω ±5%)
val z0-g4 = pcie-get-trace-impedance(PCIE-V4)  ; => 85.0 +/- (5%)

; Constrain a PCIe Gen 3 x4 link
pcb-module pcie-gen3-x4-link:
  inst CPU  : my-cpu-component
  inst FPGA : my-fpga-component

  require cpu-pcie  : pcie(4) from CPU
  require fpga-pcie : pcie(4) from FPGA

  ; Reverse lanes for active-to-active connection (TX=>RX, RX=>TX)
  val cpu-reversed = reverse-pcie-lanes(cpu-pcie)

  val rs = pcb-differential-routing-structure my-diff-rs : ...
  val pcie-cst = PCIe-Constraint(PCIE-V3, rs)
  constrain(pcie-cst, cpu-reversed, fpga-pcie)
```

--------------------------------

### Generate Crystal Resonator PCB Module

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `create-crystal-resonator` to generate a PCB module with a crystal and matched load capacitors. Capacitor values are calculated based on crystal load capacitance and stray capacitance, then snapped to standard E-series values.

```stanza
#use-added-syntax(jitx)
val my-xtal = my-16MHz-crystal-component  ; user-defined pcb-component

; Generate a resonator circuit with load caps auto-selected to match C_load
val resonator = create-crystal-resonator(
  xtal-type = my-xtal,
  C-load    = 12.5e-12 +/- (10 %),  ; Crystal spec: 12.5pF load cap
  C-stray   = 3.0e-12 +/- (10 %),   ; Board stray capacitance estimate
  V-rating  = 3.3,                   ; Minimum cap voltage rating
  tc-code   = "C0G",                 ; Temperature coefficient
  prec      = (5 %)                  ; E24 series precision
)

pc b-module oscillator-block:
  port XTAL-IN
  port XTAL-OUT
  port GND

  inst xres : resonator
  net (XTAL-IN,  xres.p[1])
  net (XTAL-OUT, xres.p[2])
  net (GND,      xres.COMMON)
```

--------------------------------

### Define General Signal Type PCB Bundles

Source: https://context7.com/jitx-inc/jsl/llms.txt

JSL provides foundational signal bundle types such as `diff-pair`, `lane-pair`, `power`, `pass-through`, and `polarized-ca` for various signal configurations.

```stanza
#use-added-syntax(jitx)
; Differential pair (foundation for high-speed signals)
public pcb-bundle diff-pair:
  port P ; Positive
  port N ; Negative

; Lane pair: TX + RX diff-pairs (used in PCIe, USB, etc.)
public pcb-bundle lane-pair:
  port TX : diff-pair
  port RX : diff-pair

; Power bundle: V+ and V-
public pcb-bundle power:
  port V+
  port V-

; Pass-through bundle (ESD protection devices)
public pcb-bundle pass-through:
  port A
  port B

; Polarized two-pin (cathode/anode)
public pcb-bundle polarized-ca:
  port c   ; cathode
  port a   ; anode

; Example: connecting diff-pair signals
pc b-module esd-protection-block:
  port signal-in  : diff-pair
  port signal-out : diff-pair
  inst ESD : tpd2e05u06  ; user-defined ESD component

  require pt : pass-through from ESD
  net (signal-in.P, pt.A)
  net (signal-out.P, pt.B)
```

--------------------------------

### USB Transport and Constraint Bundles

Source: https://context7.com/jitx-inc/jsl/llms.txt

Define USB 2.0, SuperSpeed, and Type-C transport bundles. Use `USB-Constraint` to apply SI routing constraints for different USB versions.

```stanza
#use-added-syntax(jitx)
; USB 2.0 transport bundle
public pcb-bundle usb-data:
  port data : diff-pair

; USB SuperSpeed transport (1-lane by default)
val usb3-transport = usb-superspeed(1)   ; data:diff-pair + lane:lane-pair[1]

; USB Type-C transport (2-lane by default)
val usbc-transport = usb-c(2)            ; data + lane[2] + cc[2] + sbu[2]

; Constrain a USB 3 link between two components
pcb-module usb3-link:
  inst U1 : usb-src-component
  inst U2 : usb-dst-component

  require ep1 : usb-superspeed() from U1
  require ep2 : usb-superspeed() from U2

  ; USB 2.0 data pair constraint (90Ω ±15%)
  val ti2 = usb-get-trace-impedance(USB2)
  val usb2-cst = USB-Constraint(proto = USB2, route-struct = diff(ti2))
  constrain-topology(ep1.data => ep2.data, usb2-cst)

  ; USB 3 SuperSpeed lane constraint with blocking caps
  val b-cap = block-cap(100.0e-9)
  val ti3 = usb-get-trace-impedance(USB3)
  val usb3-cst = USB-Constraint(proto = USB3, route-struct = diff(ti3))
  val lane-cst = LaneConstraint(usb3-cst)

  within [src, dst] = constrain-topology(
      ep1.lane[0] => reverse-lane(ep2.lane[0]), lane-cst):
    topo-net(src.RX => dst.RX)
    inst tx-bcap : dp-coupler(b-cap)
    topo-pair(src.TX => tx-bcap => dst.TX)
```

--------------------------------

### Generate BGA Land Pattern

Source: https://context7.com/jitx-inc/jsl/llms.txt

Creates Ball Grid Array land patterns using a configurable grid planner, supporting full matrix, depopulated, and staggered configurations.

```Stanza
#use-added-syntax(jitx)
public pcb-component fpga-bga256:
  port p : pin[[1 through 256]]
  ; ...

  ; Full-matrix 256-ball BGA, 16x16, 0.8mm pitch
  val pkg = BGA(
    num-leads    = 256,
    rows         = 16,
    columns      = 16,
    lead-diam    = 0.45,
    pitch        = 0.8,
    package-body = PackageBody(
      width  = min-max(13.9, 14.1),
      length = min-max(13.9, 14.1),
      height = min-max(1.0, 1.2)
    ),
    density-level = DensityLevelB
  )
  assign-landpattern $ create-landpattern(pkg)
```

--------------------------------

### Map Component Values to Standard Series

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `closest-std-val` and `closest-std-tol` to find the nearest industry-standard preferred values for components. `find-in-range` and `find-nearest` can also be used with specific series like E12, E24, E48, E96.

```stanza
#use-added-syntax(jitx)
; Find the nearest E96 (1%) value to 4.64kΩ
val r-val = closest-std-val(4.64e3, (1 %))
; => 4640.0 (4.64k in E96)

; Find the nearest E24 (5%) value as a Toleranced
val r-tol = closest-std-tol(10.2e3, (5 %))
; => 10.0e3 +/- (5%)

; Find all E24 values between 1kΩ and 10kΩ
val e24 = E24()
val range-vals = find-in-range(e24, 1.0e3, 10.0e3)
; => Tuple of standard values: 1.0k, 1.1k, ..., 9.1k

; Find nearest in E12 series
val e12 = E12()
val nearest = find-nearest(e12, 4.5e3)
; => 4700.0 (4.7k)

; Use in crystal resonator cap calculation
val cap-val = 2.0 * (12.5e-12 - 3.0e-12)  ; = 19.0pF
val std-cap = closest-std-val(cap-val, (5 %))
; => 18.0e-12 (18pF, nearest E24 value)
```

--------------------------------

### Define Communication Interface PCB Bundles

Source: https://context7.com/jitx-inc/jsl/llms.txt

JSL defines `pcb-bundle` types for common serial communication protocols like I2C, SPI, and UART. These bundles integrate with JITX's `supports/require` pin assignment system.

```stanza
#use-added-syntax(jitx)
; I2C bundle: sda + scl
public pcb-bundle i2c:
  port sda
  port scl

; SPI with chip select
val spi-iface = spi-with-cs()   ; sck + cs + cipo + copi
val std-spi   = std-spi()       ; sck + cipo + copi (no CS)
val qspi      = quad-spi(SPI-CS) ; sck + cs + data[4]

; UART: configurable pin set
val full-uart = uart-fc()        ; tx + rx + rts + cts
val minimal   = minimal-uart()   ; tx + rx only

; CAN physical + logical
public pcb-bundle can-phy:      ; H + L differential pair
  port H ; port L

public pcb-bundle can-logical:  ; rx + tx
  port rx ; port tx

; Usage in a pcb-component supports statement
pc b-component my-mcu:
  port I2C-A : i2c
  ; ...
  supports i2c:
    i2c.sda => self.I2C-A.sda
    i2c.scl => self.I2C-A.scl

; Usage in a pcb-module require statement
pc b-module sensor-subsystem:
  inst mcu : my-mcu
  require sensor-bus : i2c from mcu
  ; sensor-bus.sda and sensor-bus.scl are now netted
```

--------------------------------

### Insert Bypass Capacitors in JSL

Source: https://context7.com/jitx-inc/jsl/llms.txt

Use `insert-bypass` to place a capacitor between voltage and ground ports. It can auto-query the parts database for a suitable capacitor by capacitance value.

```Stanza
#use-added-syntax(jitx)
; Example: bypass a 3.3V rail on a component with a 100nF capacitor
pcb-module power-supply-module:
  port rail-3v3 : power
  inst reg : my-ldo-component

  ; Bypass using a specific capacitor instance
  inst C1 : ceramic-cap-100nF
  bypass(C1, reg.OUT, reg.GND)

  ; OR: auto-query a 100nF capacitor and insert it; instance named "OUT-byp"
  insert-bypass(reg.OUT, reg.GND, elem-type = 100.0e-9)

  ; OR: bypass across a power bundle port directly
  insert-bypass(rail-3v3, elem-type = 4.7e-6, inst-name = "bulk-cap")
```

--------------------------------

### insert-bypass

Source: https://context7.com/jitx-inc/jsl/llms.txt

Places a bypass capacitor between a positive voltage rail port and a negative (ground) port. It can optionally query the JITX parts database for a suitable capacitor by capacitance value.

```APIDOC
## insert-bypass

### Description
Places a bypass capacitor between a positive voltage rail port and a negative (ground) port, optionally querying the JITX parts database for a suitable capacitor by capacitance value.

### Method
Stanza DSL function call

### Parameters
- **positive_port** (Port) - Required - The positive voltage rail port.
- **negative_port** (Port) - Required - The negative (ground) port.
- **elem-type** (Instantiable or Capacitance) - Required - Either a specific capacitor instance or a capacitance value (e.g., 100.0e-9).
- **inst-name** (string) - Optional - The name to assign to the inserted capacitor instance.

### Request Example
```stanza
insert-bypass(reg.OUT, reg.GND, elem-type = 100.0e-9)
insert-bypass(rail-3v3, elem-type = 4.7e-6, inst-name = "bulk-cap")
```
```

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