### Run Unit Tests with setup.py

Source: https://github.com/enjoy-digital/liteeth/blob/master/README.md

This command executes all available unit tests for the LiteEth project using the setup.py script. Ensure Python 3.6+ is installed.

```shell
./setup.py test
```

--------------------------------

### Define Standalone Core Configuration

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Example YAML configuration for generating a standalone Verilog core for Xilinx 7-Series FPGAs.

```yaml
phy       : LiteEthS7PHYRGMII
vendor    : xilinx
toolchain : vivado
```

--------------------------------

### Setup LiteEth ARP and Cache

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configures the ARP module for MAC address resolution and manages the ARP cache table for network communication.

```python
from liteeth.core.arp import LiteEthARP, LiteEthARPTable, LiteEthARPCache

arp = LiteEthARP(
    mac         = mac,
    mac_address = 0x10e2d5000001,
    ip_address  = 0xC0A80132,
    clk_freq    = 125e6,
    entries     = 1,
    dw          = 8
)

cache = LiteEthARPCache(entries=4, clk_freq=125e6)
```

--------------------------------

### LiteEth PHY Layer Implementations

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Demonstrates the initialization of different PHY layer interfaces supported by LiteEth, including MII, RMII, GMII, RGMII, and 1000BASE-X.

```APIDOC
## LiteEth PHY Layer - Physical Interface Selection

LiteEth provides multiple PHY implementations for different Ethernet standards and FPGA families. The PHY layer handles clock domain crossing, signal timing, and physical interface requirements for each standard.

### MII PHY (10/100 Mbps)

```python
from litex.gen import *
from liteeth.phy.mii import LiteEthPHYMII

# MII PHY (10/100 Mbps) - All platforms
ethphy = LiteEthPHYMII(
    clock_pads = platform.request("mii_clocks"),
    pads       = platform.request("mii")
)
```

### RMII PHY (10/100 Mbps)

```python
from litex.gen import *
from liteeth.phy.rmii import LiteEthPHYRMII

# RMII PHY (10/100 Mbps) - All platforms
ethphy = LiteEthPHYRMII(
    refclk_cd  = None,
    clock_pads = platform.request("rmii_clocks"),
    pads       = platform.request("rmii")
)
```

### GMII PHY (1 Gbps)

```python
from litex.gen import *
from liteeth.phy.gmii import LiteEthPHYGMII

# GMII PHY (1 Gbps) - Spartan-6, 7-Series, Ultrascale
ethphy = LiteEthPHYGMII(
    clock_pads = platform.request("gmii_clocks"),
    pads       = platform.request("gmii")
)
```

### RGMII PHY (1 Gbps) - Xilinx 7-Series

```python
from litex.gen import *
from liteeth.phy.s7rgmii import LiteEthPHYRGMII as LiteEthS7PHYRGMII

# RGMII PHY (1 Gbps) - Xilinx 7-Series
ethphy = LiteEthS7PHYRGMII(
    clock_pads         = platform.request("rgmii_clocks"),
    pads               = platform.request("rgmii"),
    tx_delay           = 2e-9,  # TX clock delay in seconds
    rx_delay           = 2e-9,  # RX clock delay in seconds
    with_hw_init_reset = True
)
```

### RGMII PHY (1 Gbps) - Lattice ECP5

```python
from litex.gen import *
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII

# RGMII PHY (1 Gbps) - Lattice ECP5
ethphy = LiteEthECP5PHYRGMII(
    clock_pads         = platform.request("rgmii_clocks"),
    pads               = platform.request("rgmii"),
    tx_delay           = 2e-9,
    rx_delay           = 2e-9,
    with_hw_init_reset = True
)
```

### 1000BASE-X PHY (1 Gbps over fiber/SerDes) - Artix-7 with GTP

```python
from litex.gen import *
from liteeth.phy.a7_gtp import QPLLSettings, QPLL
from liteeth.phy.a7_1000basex import A7_1000BASEX

# QPLL Settings for 1000BASE-X
qpll_settings = QPLLSettings(
    refclksel  = 0b001,
    fbdiv      = 4,
    fbdiv_45   = 5,
    refclk_div = 1
)
qpll = QPLL(ethphy_pads.refclk, qpll_settings)

# 1000BASE-X PHY
ethphy = A7_1000BASEX(
    data_pads    = platform.request("sgmii"),
    sys_clk_freq = sys_clk_freq,
    qpll_channel = qpll.channels[0],
    with_csr     = False
)
```
```

--------------------------------

### LiteEth PHY Layer Implementations (Python)

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Demonstrates the selection and instantiation of different PHY layer interfaces for LiteEth, including MII, RMII, GMII, RGMII, and 1000BASE-X. Each PHY type is configured based on the target FPGA platform and Ethernet standard.

```python
from migen import *
from litex.gen import *
from liteeth.phy.mii import LiteEthPHYMII
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.phy.gmii import LiteEthPHYGMII
from liteeth.phy.s7rgmii import LiteEthPHYRGMII as LiteEthS7PHYRGMII
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII as LiteEthECP5PHYRGMII
from liteeth.phy.a7_1000basex import A7_1000BASEX, A7_2500BASEX
from liteeth.phy.usp_gth_1000basex import USP_GTH_1000BASEX

# MII PHY (10/100 Mbps) - All platforms
ethphy = LiteEthPHYMII(
    clock_pads = platform.request("mii_clocks"),
    pads       = platform.request("mii")
)

# RMII PHY (10/100 Mbps) - All platforms
ethphy = LiteEthPHYRMII(
    refclk_cd  = None,
    clock_pads = platform.request("rmii_clocks"),
    pads       = platform.request("rmii")
)

# GMII PHY (1 Gbps) - Spartan-6, 7-Series, Ultrascale
ethphy = LiteEthPHYGMII(
    clock_pads = platform.request("gmii_clocks"),
    pads       = platform.request("gmii")
)

# RGMII PHY (1 Gbps) - Xilinx 7-Series
ethphy = LiteEthS7PHYRGMII(
    clock_pads         = platform.request("rgmii_clocks"),
    pads               = platform.request("rgmii"),
    tx_delay           = 2e-9,  # TX clock delay in seconds
    rx_delay           = 2e-9,  # RX clock delay in seconds
    with_hw_init_reset = True
)

# RGMII PHY (1 Gbps) - Lattice ECP5
ethphy = LiteEthECP5PHYRGMII(
    clock_pads         = platform.request("rgmii_clocks"),
    pads               = platform.request("rgmii"),
    tx_delay           = 2e-9,
    rx_delay           = 2e-9,
    with_hw_init_reset = True
)

# 1000BASE-X PHY (1 Gbps over fiber/SerDes) - Artix-7 with GTP
from liteeth.phy.a7_gtp import QPLLSettings, QPLL
qpll_settings = QPLLSettings(
    refclksel  = 0b001,
    fbdiv      = 4,
    fbdiv_45   = 5,
    refclk_div = 1
)
qpll = QPLL(ethphy_pads.refclk, qpll_settings)
ethphy = A7_1000BASEX(
    data_pads    = platform.request("sgmii"),
    sys_clk_freq = sys_clk_freq,
    qpll_channel = qpll.channels[0],
    with_csr     = False
)
```

--------------------------------

### Configure LiteEth UDP TX and RX Modules

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Instantiates low-level UDP transmission and reception modules. These modules include FIFO buffers and optional CSR registers for runtime configuration.

```python
udp_tx = LiteEthStream2UDPTX(
    ip_address  = "192.168.1.100",
    udp_port    = 2000,
    data_width  = 32,
    fifo_depth  = 64,
    with_csr    = True
)

udp_rx = LiteEthUDP2StreamRX(
    ip_address     = "192.168.1.100",
    udp_port       = 2000,
    data_width     = 32,
    fifo_depth     = 64,
    with_broadcast = True,
    with_csr       = True
)
```

--------------------------------

### LiteEthIPCore Configuration

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Initializes the LiteEthIPCore, which integrates MAC, ARP, and IP layers with optional ICMP support. It requires system clock frequency, MAC and IP addresses, and configuration for ARP cache and data width.

```python
from liteeth.core import LiteEthIPCore

# IP Core (MAC + ARP + IP + optional ICMP)
ip_core = LiteEthIPCore(
    phy               = ethphy,
    mac_address       = 0x10e2d5000001,       # 48-bit MAC address
    ip_address        = "192.168.1.50",       # IP address (string or integer)
    clk_freq          = 125e6,                # System clock frequency
    arp_entries       = 1,                    # ARP cache entries
    dw                = 8,                    # Data width
    with_icmp         = True,                 # Enable ICMP (ping) responder
    icmp_fifo_depth   = 128,                  # ICMP FIFO depth
    with_ip_broadcast = True,                 # Accept broadcast packets
    with_sys_datapath = False,
    tx_cdc_depth      = 32,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 32,
    rx_cdc_buffered   = True,
    interface         = "crossbar",
    endianness        = "big"
)
```

--------------------------------

### LiteEthIPCore and LiteEthUDPIPCore

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration for IP Core (MAC, ARP, IP, ICMP) and UDP/IP Core (adds UDP support).

```APIDOC
## LiteEthIPCore and LiteEthUDPIPCore - Network Protocol Stack

### Description
The IP Core combines MAC, ARP, and IP layers with optional ICMP support. The UDP/IP Core extends this with UDP protocol support and a crossbar for multiple UDP ports.

### IP Core Configuration
```python
# IP Core (MAC + ARP + IP + optional ICMP)
ip_core = LiteEthIPCore(
    phy               = ethphy,
    mac_address       = 0x10e2d5000001,       # 48-bit MAC address
    ip_address        = "192.168.1.50",       # IP address (string or integer)
    clk_freq          = 125e6,                # System clock frequency
    arp_entries       = 1,                    # ARP cache entries
    dw                = 8,                    # Data width
    with_icmp         = True,                 # Enable ICMP (ping) responder
    icmp_fifo_depth   = 128,                  # ICMP FIFO depth
    with_ip_broadcast = True,                 # Accept broadcast packets
    with_sys_datapath = False,
    tx_cdc_depth      = 32,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 32,
    rx_cdc_buffered   = True,
    interface         = "crossbar",
    endianness        = "big"
)
```

### UDP/IP Core Configuration
```python
# UDP/IP Core (MAC + ARP + IP + ICMP + UDP)
udp_ip_core = LiteEthUDPIPCore(
    phy               = ethphy,
    mac_address       = 0x10e2d5000001,
    ip_address        = "192.168.1.50",
    clk_freq          = 125e6,
    arp_entries       = 1,
    dw                = 8,
    with_icmp         = True,
    icmp_fifo_depth   = 128,
    with_ip_broadcast = True,
    with_sys_datapath = False,
    tx_cdc_depth      = 32,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 32,
    rx_cdc_buffered   = True
)

# Get UDP port for application use
udp_port = udp_ip_core.udp.crossbar.get_port(
    udp_port = 1234,      # UDP port number
    dw       = 32,        # Data width
    cd       = "sys"      # Clock domain
)
# udp_port.sink.valid, .ready, .last, .data - TX stream
# udp_port.sink.src_port, .dst_port, .ip_address, .length - TX parameters
# udp_port.source.valid, .ready, .last, .data - RX stream
# udp_port.source.src_port, .dst_port, .ip_address, .length - RX parameters
```
```

--------------------------------

### LiteEth Core Configuration (YAML)

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration file for LiteEth, specifying core type, MAC address, IP address, and UDP port settings. Supports UDP, Wishbone, and AXI-Lite interfaces.

```yaml
# Core Configuration
clk_freq    : 125e6
core        : udp                             # "wishbone", "axi-lite", or "udp"
mac_address : 0x10e2d5000000
ip_address  : 192.168.1.50
data_width  : 8

# UDP Ports Configuration
udp_ports:
  udp0:
    udp_port      : 2000                      # Static port number
    ip_address    : "192.168.1.100"           # Static target IP
    data_width    : 32
    tx_fifo_depth : 64
    rx_fifo_depth : 64
  udp1:
    # Dynamic params - IP/port set via IOs
    data_width    : 32
    tx_fifo_depth : 64
    rx_fifo_depth : 64
```

```yaml
# wishbone_config.yml - MAC Core with Wishbone interface
phy        : LiteEthPHYMII
vendor     : xilinx
toolchain  : vivado

clk_freq   : 100e6
core       : wishbone                         # or "axi-lite"
endianness : big

soc:
    mem_map:
        ethmac: 0x50000000
```

--------------------------------

### LiteEth Core Generation (Bash)

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Command to generate a standalone Verilog core for LiteEth using a configuration YAML file. Outputs Verilog RTL, CSR map, and timing constraints.

```bash
# Generate standalone Verilog core
python -m liteeth.gen config.yml --name my_ethernet_core

# Output files in build/ directory:
# - my_ethernet_core.v      : Verilog RTL
# - csr.csv                 : CSR register map
# - my_ethernet_core.xdc    : Timing constraints (Xilinx)
```

--------------------------------

### Run Individual Unit Tests

Source: https://github.com/enjoy-digital/liteeth/blob/master/README.md

This command allows running a specific unit test by specifying its module path. It requires Python 3.6+ and the unittest module.

```python
python3 -m unittest test.test_name
```

--------------------------------

### Configure LiteEth DHCP Module

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configures the DHCP module to obtain an IP address automatically. Requires a system clock frequency and a defined UDP port.

```python
from liteeth.core.dhcp import LiteEthDHCP

dhcp_port = udp_ip_core.udp.crossbar.get_port(68, dw=32, cd="sys")
dhcp = LiteEthDHCP(
    udp_port     = dhcp_port,
    sys_clk_freq = 125e6,
    timeout      = 1.0
)

self.comb += [
    dhcp.mac_address.eq(0x10e2d5000001),
    dhcp.start.eq(dhcp_start),
    dhcp_done.eq(dhcp.done),
    dhcp_timeout.eq(dhcp.timeout),
    obtained_ip.eq(dhcp.ip_address)
]
```

--------------------------------

### Implement Etherbone for Wishbone over UDP

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Sets up Etherbone to bridge Wishbone bus transactions over Ethernet. Supports both master and slave modes for remote register access.

```python
from liteeth.frontend.etherbone import LiteEthEtherbone

etherbone = LiteEthEtherbone(
    udp          = udp_ip_core.udp,
    udp_port     = 1234,
    mode         = "master",
    buffer_depth = 4,
    cd           = "sys"
)

self.bus.add_master(name="etherbone", master=etherbone.wishbone.bus)

etherbone_slave = LiteEthEtherbone(
    udp      = udp_ip_core.udp,
    udp_port = 1234,
    mode     = "slave"
)
```

--------------------------------

### LiteEthMAC - Media Access Controller (Python)

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration of the LiteEth MAC module, handling Ethernet frame processing. It supports different interface types (crossbar, wishbone, hybrid) and options for preamble/CRC handling and clocking.

```python
from liteeth.mac import LiteEthMAC

# MAC with Crossbar interface (for hardware protocol stack)
mac = LiteEthMAC(
    phy               = ethphy,
    dw                = 8,                    # Data width (8, 16, 32, 64)
    interface         = "crossbar",           # "crossbar", "wishbone", or "hybrid"
    endianness        = "big",                # "big" or "little"
    with_preamble_crc = True,                 # Enable preamble and CRC handling
    with_sys_datapath = False,                # Use system clock for datapath
    tx_cdc_depth      = 32,                   # TX CDC FIFO depth
    tx_cdc_buffered   = False,                # Buffer TX CDC
    rx_cdc_depth      = 32,                   # RX CDC FIFO depth
    rx_cdc_buffered   = False                 # Buffer RX CDC
)
```

--------------------------------

### LiteEthUDPIPCore Configuration and Port Access

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Sets up the LiteEthUDPIPCore, extending the IP Core with UDP protocol support. It allows obtaining a specific UDP port via a crossbar for application-level communication, defining data width and clock domain.

```python
from liteeth.core import LiteEthUDPIPCore

# UDP/IP Core (MAC + ARP + IP + ICMP + UDP)
udp_ip_core = LiteEthUDPIPCore(
    phy               = ethphy,
    mac_address       = 0x10e2d5000001,
    ip_address        = "192.168.1.50",
    clk_freq          = 125e6,
    arp_entries       = 1,
    dw                = 8,
    with_icmp         = True,
    icmp_fifo_depth   = 128,
    with_ip_broadcast = True,
    with_sys_datapath = False,
    tx_cdc_depth      = 32,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 32,
    rx_cdc_buffered   = True
)

# Get UDP port for application use
udp_port = udp_ip_core.udp.crossbar.get_port(
    udp_port = 1234,      # UDP port number
    dw       = 32,        # Data width
    cd       = "sys"      # Clock domain
)
# udp_port.sink.valid, .ready, .last, .data - TX stream
# udp_port.sink.src_port, .dst_port, .ip_address, .length - TX parameters
# udp_port.source.valid, .ready, .last, .data - RX stream
# udp_port.source.src_port, .dst_port, .ip_address, .length - RX parameters
```

--------------------------------

### LiteEthEtherbone - Wishbone over UDP

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Etherbone implements CERN's protocol for accessing Wishbone bus over Ethernet/UDP, enabling remote FPGA register access and debugging.

```APIDOC
## POST /etherbone/master

### Description
Initializes an Etherbone Master to provide Wishbone bus access from network requests.

### Method
POST

### Endpoint
/etherbone/master

### Parameters
#### Request Body
- **udp** (object) - Required - UDP module instance
- **udp_port** (int) - Required - UDP port for Etherbone traffic
- **mode** (string) - Required - 'master' or 'slave'
- **buffer_depth** (int) - Optional - Record buffer depth (max 256)
- **cd** (string) - Required - Clock domain

### Response
#### Success Response (200)
- **wishbone.bus** (object) - Wishbone bus interface for SoC integration
```

--------------------------------

### LiteEthDHCP - Dynamic Host Configuration Protocol

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

The DHCP module provides automatic IP address configuration from a DHCP server.

```APIDOC
## POST /dhcp/configure

### Description
Configures the DHCP module to initiate an IP discovery sequence.

### Method
POST

### Endpoint
/dhcp/configure

### Parameters
#### Request Body
- **udp_port** (object) - Required - 32-bit UDP port
- **sys_clk_freq** (float) - Required - System clock frequency in Hz
- **timeout** (float) - Optional - DHCP timeout in seconds

### Response
#### Success Response (200)
- **ip_address** (int) - Obtained IP address upon completion
- **done** (bool) - DHCP completion flag
```

--------------------------------

### LiteEthMAC - Media Access Controller Configuration

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration of the LiteEthMAC module, detailing options for data width, interface type, endianness, and preamble/CRC handling.

```APIDOC
## LiteEthMAC - Media Access Controller

The MAC module handles Ethernet frame processing including preamble, CRC, and provides configurable interfaces (crossbar for protocol stack, wishbone for CPU access, or hybrid for both).

### MAC with Crossbar Interface

```python
from liteeth.mac import LiteEthMAC

# MAC with Crossbar interface (for hardware protocol stack)
mac = LiteEthMAC(
    phy               = ethphy,               # Attached PHY object
    dw                = 8,                    # Data width (8, 16, 32, 64)
    interface         = "crossbar",           # "crossbar", "wishbone", or "hybrid"
    endianness        = "big",                # "big" or "little"
    with_preamble_crc = True,                 # Enable preamble and CRC handling
    with_sys_datapath = False,                # Use system clock for datapath
    tx_cdc_depth      = 32,                   # TX CDC FIFO depth
    tx_cdc_buffered   = False,                # Buffer TX CDC
    rx_cdc_depth      = 32,                   # RX CDC FIFO depth
    rx_cdc_buffered   = False                 # Buffer RX CDC
)
```

### MAC with Wishbone Interface

```python
from liteeth.mac import LiteEthMAC

# MAC with Wishbone interface (for CPU access)
mac = LiteEthMAC(
    phy               = ethphy,
    dw                = 32,                   # Data width
    interface         = "wishbone",           # Wishbone interface
    endianness        = "little",             # Endianness
    with_preamble_crc = True,
    with_sys_datapath = True,                 # Use system clock for datapath
    tx_cdc_depth      = 64,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 64,
    rx_cdc_buffered   = True
)
```

### MAC with Hybrid Interface

```python
from liteeth.mac import LiteEthMAC

# MAC with Hybrid interface (for both hardware stack and CPU access)
mac = LiteEthMAC(
    phy               = ethphy,
    dw                = 64,                   # Data width
    interface         = "hybrid",             # Hybrid interface
    endianness        = "big",                # Endianness
    with_preamble_     = True,
    with_sys_datapath = False,
    tx_cdc_depth      = 128,
    tx_cdc_buffered   = True,
    rx_cdc_depth      = 128,
    rx_cdc_buffered   = True
)
```
```

--------------------------------

### LiteEth Protocol Constants and Helpers (Python)

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Python module providing Ethernet protocol constants (MTU, frame lengths, types, protocols) and helper functions like IP address conversion. Also defines stream endpoint descriptions for PHY, MAC, and UDP interfaces.

```python
from liteeth.common import (
    # Ethernet Constants
    eth_mtu,                    # 1530 - Maximum transmission unit
    eth_min_frame_length,       # 64 - Minimum frame length
    eth_fcs_length,             # 4 - Frame check sequence length
    eth_interpacket_gap,        # 12 - Inter-packet gap bytes
    eth_preamble,               # 0xd555555555555555

    # Ethernet Types
    ethernet_type_ip,           # 0x800 - IPv4
    ethernet_type_arp,          # 0x806 - ARP

    # Protocol Numbers
    icmp_protocol,              # 0x01
    udp_protocol,               # 0x11

    # ARP Constants
    arp_hwtype_ethernet,        # 0x0001
    arp_proto_ip,               # 0x0800
    arp_opcode_request,         # 0x0001
    arp_opcode_reply,           # 0x0002

    # Helper Functions
    convert_ip,                 # Convert IP string to integer

    # Stream Descriptions
    eth_phy_description,        # PHY-level stream layout
    eth_mac_description,        # MAC-level stream layout
    eth_udp_user_description,   # UDP user interface layout
)

# IP address conversion
ip_int = convert_ip("192.168.1.50")    # Returns 0xC0A80132
ip_int = convert_ip(0xC0A80132)        # Pass-through for integers

# Stream endpoint descriptions for custom modules
from litex.soc.interconnect.stream import Endpoint

# PHY-level: raw data with error indication
phy_sink = Endpoint(eth_phy_description(dw=8))
# Fields: data, last_be, error

# MAC-level: includes MAC header fields
mac_sink = Endpoint(eth_mac_description(dw=8))
# Fields: target_mac, sender_mac, ethernet_type, data, last_be, error

# UDP user interface: simplified for applications
udp_sink = Endpoint(eth_udp_user_description(dw=32))
# Fields: src_port, dst_port, ip_address, length, data, last_be, error
```

--------------------------------

### LiteEthMAC Configuration

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration options for the LiteEthMAC module with Wishbone and Hybrid interfaces.

```APIDOC
## LiteEthMAC

### Description
Provides Media Access Control (MAC) functionality with Wishbone or Hybrid interfaces for CPU/software access and protocol implementation.

### Wishbone Interface Configuration
```python
mac = LiteEthMAC(
    phy               = ethphy,
    dw                = 32,
    interface         = "wishbone",
    endianness        = "big",
    nrxslots          = 2,                    # Number of RX buffer slots
    rxslots_read_only = True,                 # RX slots are read-only
    ntxslots          = 2,                    # Number of TX buffer slots
    txslots_write_only= False,                # TX slots are write-only
    hw_mac            = None,                 # Hardware MAC filtering address
    timestamp         = None,                 # Timestamp signal for PTP
    full_memory_we    = False                 # Full memory write enable (for ECP5)
)

# Access MAC ports for protocol implementation
mac_port = mac.crossbar.get_port(ethernet_type=0x0800, dw=8)  # Get port for IPv4
# mac_port.sink   - Stream endpoint to send frames
# mac_port.source - Stream endpoint to receive frames
```

### Hybrid Interface Configuration
```python
mac = LiteEthMAC(
    phy       = ethphy,
    dw        = 32,
    interface = "hybrid",
    hw_mac    = 0x10e2d5000001  # Filter packets by MAC address
)
```
```

--------------------------------

### LiteEthUDPStreamer

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configuration for LiteEthUDPStreamer for simplified UDP data streaming.

```APIDOC
## LiteEthUDPStreamer - Simple UDP Data Streaming

### Description
The UDP Streamer provides a simplified interface for streaming data over UDP with built-in FIFOs and optional CSR control.

### Complete UDP Streamer Configuration
```python
# Complete UDP Streamer (TX + RX with FIFOs)
udp_streamer = LiteEthUDPStreamer(
    udp            = udp_ip_core.udp,         # UDP module from core
    ip_address     = "192.168.1.100",         # Target IP address
    udp_port       = 2000,                    # UDP port number
    data_width     = 8,                       # Data width (8, 16, 32, 64)
    rx_fifo_depth  = 64,                      # RX FIFO depth
    tx_fifo_depth  = 64,                      # TX FIFO depth
    with_broadcast = True,                    # Accept broadcast packets
    cd             = "sys"                    # Clock domain
)

# Connect to streamer endpoints
# TX: Send data
self.comb += [
    udp_streamer.sink.valid.eq(tx_valid),
    udp_streamer.sink.last.eq(tx_last),
    udp_streamer.sink.data.eq(tx_data),
    tx_ready.eq(udp_streamer.sink.ready)
]

# RX: Receive data
self.comb += [
    rx_valid.eq(udp_streamer.source.valid),
    rx_last.eq(udp_streamer.source.last),
    rx_data.eq(udp_streamer.source.data),
    rx_error.eq(udp_streamer.source.error),
    udp_streamer.source.ready.eq(rx_ready)
]
```
```

--------------------------------

### LiteEthMAC Wishbone and Hybrid Interfaces

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configures the LiteEthMAC for different interface types. The Wishbone interface allows CPU/software access to MAC ports, while the Hybrid interface supports both hardware and software access with MAC address filtering.

```python
mac = LiteEthMAC(
    phy               = ethphy,
    dw                = 32,
    interface         = "wishbone",
    endianness        = "big",
    nrxslots          = 2,                    # Number of RX buffer slots
    rxslots_read_only = True,                 # RX slots are read-only
    ntxslots          = 2,                    # Number of TX buffer slots
    txslots_write_only= False,                # TX slots are write-only
    hw_mac            = None,                 # Hardware MAC filtering address
    timestamp         = None,                 # Timestamp signal for PTP
    full_memory_we    = False                 # Full memory write enable (for ECP5)
)

# Access MAC ports for protocol implementation
mac_port = mac.crossbar.get_port(ethernet_type=0x0800, dw=8)  # Get port for IPv4
# mac_port.sink   - Stream endpoint to send frames
# mac_port.source - Stream endpoint to receive frames

# Hybrid mode - both hardware and software access
mac = LiteEthMAC(
    phy       = ethphy,
    dw        = 32,
    interface = "hybrid",
    hw_mac    = 0x10e2d5000001  # Filter packets by MAC address
)
```

--------------------------------

### LiteEthUDPStreamer for UDP Data Streaming

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

Configures the LiteEthUDPStreamer for simplified UDP data transmission and reception. It includes built-in FIFOs for TX and RX, and can be connected to application logic for streaming data to a specified IP address and UDP port.

```python
from liteeth.frontend.stream import LiteEthUDPStreamer

# Complete UDP Streamer (TX + RX with FIFOs)
udp_streamer = LiteEthUDPStreamer(
    udp            = udp_ip_core.udp,         # UDP module from core
    ip_address     = "192.168.1.100",         # Target IP address
    udp_port       = 2000,                    # UDP port number
    data_width     = 8,                       # Data width (8, 16, 32, 64)
    rx_fifo_depth  = 64,                      # RX FIFO depth
    tx_fifo_depth  = 64,                      # TX FIFO depth
    with_broadcast = True,                    # Accept broadcast packets
    cd             = "sys"                    # Clock domain
)

# Connect to streamer endpoints
# TX: Send data
self.comb += [
    udp_streamer.sink.valid.eq(tx_valid),
    udp_streamer.sink.last.eq(tx_last),
    udp_streamer.sink.data.eq(tx_data),
    tx_ready.eq(udp_streamer.sink.ready)
]

# RX: Receive data
self.comb += [
    rx_valid.eq(udp_streamer.source.valid),
    rx_last.eq(udp_streamer.source.last),
    rx_data.eq(udp_streamer.source.data),
    rx_error.eq(udp_streamer.source.error),
    udp_streamer.source.ready.eq(rx_ready)
]
```

--------------------------------

### LiteEthARP - Address Resolution Protocol

Source: https://context7.com/enjoy-digital/liteeth/llms.txt

The ARP module handles MAC address resolution for IP addresses with a configurable cache.

```APIDOC
## GET /arp/lookup

### Description
Performs a MAC address lookup for a target IP address using the ARP table.

### Method
GET

### Endpoint
/arp/lookup

### Parameters
#### Query Parameters
- **ip_address** (int) - Required - Target IP address to resolve

### Response
#### Success Response (200)
- **mac_address** (int) - Resolved MAC address
- **failed** (bool) - Indicates if the lookup failed
```

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