### Install Surelog to Custom Prefix

Source: https://github.com/chipsalliance/surelog/blob/master/INSTALL.md

Install Surelog to a custom installation path by specifying the PREFIX variable. This example installs to the user's local directory.

```bash
make install PREFIX=~/.local
```

--------------------------------

### Prerequisites and Setup

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Ibex/dv/riscv_compliance/README.md

Installs necessary tools and clones the RISC-V compliance test suite.

```APIDOC
## Prerequisites and Setup

### Description
Installs required tools like Verilator, fusesoc, srecord, and a RV32 compiler. It also clones the RISC-V compliance test suite repository.

### Installation Commands

```sh
# Install srecord and fusesoc (Python package)
sudo apt-get install srecord python3-pip
pip3 install --user -U fusesoc

# Clone the RISC-V compliance test suite
git clone https://github.com/riscv/riscv-compliance.git
cd riscv-compliance
```

### Verilator Installation

It is recommended to install Verilator from source for the latest version. Refer to https://www.veripool.org/projects/verilator/wiki/Installing for instructions.
```

--------------------------------

### Install Surelog

Source: https://github.com/chipsalliance/surelog/blob/master/INSTALL.md

Install the Surelog executable and associated files to the system. The default installation path is /usr/local.

```bash
make install
```

--------------------------------

### Install Surelog

Source: https://github.com/chipsalliance/surelog/blob/master/CLAUDE.md

Installs Surelog to the system. The default installation prefix is /usr/local. A custom prefix can be specified.

```bash
# Install to system (default: /usr/local)
make install
# Custom prefix: PREFIX=/path/to/install make install
```

--------------------------------

### Install Verilator from Source

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/doc/ug/install_instructions/index.md

Fetch, build, and install a specific version of Verilator. This process involves cloning the repository, checking out a tagged version, and then configuring, building, and installing the tool. Remember to add the Verilator bin directory to your PATH after installation.

```bash
export VERILATOR_VERSION=4.010

$ git clone http://git.veripool.org/git/verilator
$ cd verilator
$ git checkout v$VERILATOR_VERSION

$ autoconf
$ ./configure --prefix=/tools/verilator/$VERILATOR_VERSION
$ make
$ make install
```

--------------------------------

### Run Vivado Web Installer

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/doc/ug/install_instructions/index.md

Execute the downloaded Vivado web installer script to begin the graphical installation process. Ensure you have registered for a Xilinx account.

```console
$ sh Xilinx_Vivado_SDK_Web_2018.3_1207_2324_Lin64.bin
```

--------------------------------

### Run all UVMC examples

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples_ovm/commands/README.txt

Executes all available command examples.

```bash
make -f Makefile.<tool> all
```

--------------------------------

### Build OpenTitan hello_world example for FPGA

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/sw/README.md

Use these commands to build the 'hello_world' example for FPGA. Ensure you are in the repository root and have initialized the build system.

```console
$ cd "$REPO_TOP"
$ ./meson_init.sh
$ ninja -C build-out/sw/fpga sw/device/examples/hello_world/hello_world_export
```

--------------------------------

### Get Start Offset

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Get the start offset of the region.

```APIDOC
## GET /api/start_offset

### Description
Get the start offset of the region.

### Method
GET

### Endpoint
/api/start_offset

### Response
#### Success Response (200)
- **start_offset** (bit [63:0]) - The start offset of the region.
```

--------------------------------

### Get Starting Phase

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Returns the 'starting phase'.

```APIDOC
## GET /api/starting_phase

### Description
Returns the ‘starting phase’.

### Method
GET

### Endpoint
/api/starting_phase

### Response
#### Success Response (200)
- **starting_phase** (uvm_phase) - The starting phase.
```

--------------------------------

### Build Hello World Software

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Ibex/examples/simple_system/README.md

Compile the hello world example software from the repository root.

```bash
make -C examples/sw/simple_system/hello_test
```

--------------------------------

### Get start offset

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/files/reg/uvm_mem_mam-svh.html

Retrieves the starting address offset of the memory region.

```SystemVerilog
function bit [63:0] get_start_offset()
```

--------------------------------

### Build Documentation

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/README.md

Compiles the project documentation and starts a local server for preview. The documentation will be available at http://127.0.0.1:1313.

```bash
$ ./util/build_docs.py --preview
```

--------------------------------

### Build and Flash Demo Software

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/doc/ug/getting_started_fpga.md

Compile the demo software and the loading tool, then flash the binary to the FPGA.

```console
$ cd ${REPO_TOP}
$ ./meson_init.sh
$ ninja -C build-out/sw/fpga sw/device/examples/hello_world/hello_world_export
$ ninja -C build-out/sw/fpga sw/host/spiflash/spiflash_export
$ build-bin/sw/host/spiflash/spiflash \
    --input build-bin/sw/device/fpga/examples/hello_world/hello_world.bin
```

--------------------------------

### Get Initiator

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Returns the component that produced or started the transaction.

```APIDOC
## Get Initiator

### Description
Returns the component that produced or started the transaction, as set by a previous call to set_initiator.

### Method
Not applicable (function definition)

### Endpoint
Not applicable (function definition)

### Parameters
#### Path Parameters
None

#### Query Parameters
None

#### Request Body
None

### Request Example
None

### Response
#### Success Response (200)
- **uvm_component** - The initiator component.

#### Response Example
None
```

--------------------------------

### Execute OVM Example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/ovm-2.1.2/README-Questa.txt

Navigate to the example directory and run the provided execution script.

```bash
% cd ovm/examples/tlm/tlm_fifo
% ./run_questa
```

--------------------------------

### Get Initiator Component

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/ovm-2.1.2/docs/html/index/General.html

Returns the component that produced or started the transaction.

```APIDOC
## GET /api/initiator

### Description
Returns the component that produced or started the transaction, as set by a previous call to set_initiator.

### Method
GET

### Endpoint
/api/initiator
```

--------------------------------

### Build configuration examples

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/hw/dv/tools/README.md

Commands for building simulation executables with specific compile keys or preprocessor flags.

```console
$ make build
```

```console
$ make build COMPILE_KEY=foo
```

```console
$ make build CL_BUILD_OPTS+=+define+FOO
```

--------------------------------

### General Make Command for Examples

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples/connections/README.txt

When running examples, you may need to specify the paths to UVM and UVMC home directories. Use 'make [UVM_HOME=path] [UVMC_HOME=path] <example>' for this purpose. Command line options override environment variables.

```makefile
make [UVM_HOME=path] [UVMC_HOME=path] <example>
```

--------------------------------

### Get UVM Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Retrieves all UVM arguments used to start the simulation.

```APIDOC
## GET /api/uvm-arguments

### Description
Returns a queue with all of the UVM arguments that were used to start the simulation.

### Method
GET

### Endpoint
/api/uvm-arguments

### Response
#### Success Response (200)
- **uvm_args** (queue) - A queue containing UVM arguments.
```

--------------------------------

### Typical Create Method Implementation

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/files/base/uvm_object-svh.html

Example implementation of the create method, instantiating a new object of the derived class.

```SystemVerilog
class mytype extends uvm_object;
  ... 
  virtual function uvm_object create(string name="");
    mytype t = new(name);
    return t;
  endfunction
```

--------------------------------

### Get plusargs

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Returns a queue with all of the plus arguments that were used to start the simulation.

```SystemVerilog
function void get_plusargs (

   
output 

string 

args[$]

)
```

--------------------------------

### Get UVM Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_cmdline_processor-svh.html

Retrieves all arguments that start with '-UVM' or '+UVM' (case-insensitive).

```APIDOC
## GET UVMARGS

### Description
This function returns a queue with all arguments identified as UVM arguments. UVM arguments are defined as any argument starting with a '-' or '+' followed by 'UVM' (case-insensitive) as the first three characters.

### Method
`function void get_uvmargs(output string args[$])`
```

--------------------------------

### Run Example Conversion

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/black-parrot/external/bsg_sv2v/README.md

Execute the conversion flow using the provided GCD example.

```bash
$ make convert_sv2v DESIGN_NAME=gcd DESIGN_FILELIST=examples/gcd/gcd.flist
```

```bash
$ cat ./results/gcd.sv2v.v
```

--------------------------------

### Run UVM Example with Makefile

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/README.txt

Execute UVM examples by navigating to the example directory and running a make command. Specify the appropriate Makefile for your simulator vendor (ius, vcs, or questa).

```bash
make -f Makefile.ius
```

```bash
make -f Makefile.vcs
```

```bash
make -f Makefile.questa
```

--------------------------------

### Get All Plus Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_cmdline_processor-svh.html

Retrieves all plus arguments used to start the simulation.

```APIDOC
## GET PLUSARGS

### Description
This function returns a queue with all of the plus arguments that were used to start the simulation. Plusarguments are arguments prefixed with a '+' and are distinct from vendor-specific dash arguments.

### Method
`function void get_plusargs(output string args[$])`
```

--------------------------------

### OUT Endpoint Packet Control

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/UhdmCoverage/chk83.html

Sequential logic for controlling OUT endpoint packet signals. Sets new packet start, current endpoint, and setup transfer flags when a transfer starts.

```SystemVerilog
always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
    if (!rst_ni) begin
      out_ep_newpkt_o       <= 1'b0;
      out_ep_current_o      <= '0;
      current_xfer_setup_q  <= 1'b0;
    end else begin
      if (out_xfr_start) begin
        out_ep_newpkt_o      <= 1'b1;
        out_ep_current_o     <= rx_endp_i;
        current_xfer_setup_q <= setup_token_received;
      end else begin
        out_ep_newpkt_o <= 1'b0;
      end
    end
  end
```

--------------------------------

### Get Simulation Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Returns a queue with all of the uvm arguments that were used to start the simulation.

```SystemVerilog
This function returns a queue with all of the uvm arguments that were used to start the simulation.
```

--------------------------------

### Build boot ROM and hello_world

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/sw/host/spiflash/README.md

Compilation commands for the boot ROM and the hello_world example program.

```console
$ cd ${REPO_TOP}
$ ./meson_init.sh
$ ninja -C build-out/sw/fpga sw/device/boot_rom/boot_rom_export
```

```console
$ cd ${REPO_TOP}
$ ninja -C build-out/sw/fpga sw/device/examples/hello_world/hello_world_export
```

--------------------------------

### Get All Command Line Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_cmdline_processor-svh.html

Retrieves all command line arguments used to start the simulation.

```APIDOC
## GET ARGS

### Description
This function returns a queue with all of the command line arguments that were used to start the simulation. The first element (index 0) is always the name of the executable.

### Method
`function void get_args(output string args[$])`
```

--------------------------------

### ELINK Testbench Example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/oh/elink/README.md

Example content for a .memh test file demonstrating 32-bit write and read operations.

```sh
AAAAAAAA_11111111_80800000_05_0010 //32 bit write
AAAAAAAA_22222222_80800004_05_0010 //
AAAAAAAA_33333333_80800008_05_0010 //
AAAAAAAA_44444444_8080000c_05_0010 //
AAAAAAAA_55555555_80800010_05_0010 //
810D0000_DEADBEEF_80800000_04_0010 //32 bit read
810D0004_DEADBEEF_80800004_04_0010 //
810D0008_DEADBEEF_80800008_04_0010 //
810D000c_DEADBEEF_8080000c_04_0010 //
810D0010_DEADBEEF_80800010_04_0010 //
```

--------------------------------

### Get Initiator

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/files/base/uvm_transaction-svh.html

Returns the component that produced or started the transaction, as set by a previous call to set_initiator.

```SystemVerilog
function uvm_component get_initiator ()
```

--------------------------------

### Run the AES example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/hw/ip/aes/model/README.md

Execute the compiled binary with an optional key length argument in bytes (16, 24, or 32).

```bash
./aes_example KEY_LEN_BYTES
```

--------------------------------

### Get Command Line Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/index/General3.html

Returns a queue with all command line arguments used to start the simulation.

```APIDOC
## function void get_args(output string args[$])

### Description
This function returns a queue with all of the command line arguments that were used to start the simulation.

### Method
`function`

### Endpoint
N/A (Function within a class)

### Parameters
#### Path Parameters
None

#### Query Parameters
None

#### Request Body
None

### Request Example
```json
{
  "example": "// No request body"
}
```

### Response
#### Success Response (200)
- **output string args[$]** - Output queue populated with command line arguments.

#### Response Example
```json
{
  "example": "// 'args' queue will be populated with simulation arguments"
}
```
```

--------------------------------

### Setup Synthesis Environment

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Ibex/syn/README.md

Source this script to set up environment variables for the synthesis flow and specify the directory containing synthesis outputs.

```bash
$ source syn_setup.sh syn_out_06_01_2020_11_19_15/
```

--------------------------------

### Get Command Line Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/index/Methods2.html

Returns a queue with all command line arguments used to start the simulation.

```SystemVerilog
function void get_args (
	output string args[$]
)
```

--------------------------------

### Run example with custom paths

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples_ovm/converters/README.txt

Executes a specific example while overriding OVM source and library paths via command line arguments.

```makefile
make OVM_HOME=<path> OVM_LIB=<path> ex10
```

--------------------------------

### Size and Offset Information

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/General4.html

Functions to get the size of memory locations or register arrays, and the start offset of a region.

```APIDOC
## GET /api/size

### Description
Returns the number of unique memory locations in this memory or the size of the virtual register array.

### Method
GET

### Endpoint
/api/size

### Response
#### Success Response (200)
- **size** (longint unsigned | int unsigned) - The size value.

## GET /api/start_offset

### Description
Get the start offset of the region.

### Method
GET

### Endpoint
/api/start_offset

### Response
#### Success Response (200)
- **offset** (bit [63:0]) - The start offset.
```

--------------------------------

### Execute Surelog on Chapter 11 Simple Examples

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Google/batch.txt

Commands for parsing simple SystemVerilog operator and addressing examples in Chapter 11.

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.4.11--simple_cond_op-sim.sv -l 11.4.11--simple_cond_op-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.4.12--simple_concat_op-sim.sv -l 11.4.12--simple_concat_op-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.5.2--simple_array_addressing-sim.sv -l 11.5.2--simple_array_addressing-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.4.13--simple_set_member-sim.sv -l 11.4.13--simple_set_member-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.4.12.1--simple_repl_op-sim.sv -l 11.4.12.1--simple_repl_op-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.4.14.3--simple_unpack_stream-sim.sv -l 11.4.14.3--simple_unpack_stream-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.5.1--simple_idx_neg_part_select-sim.sv -l 11.5.1--simple_idx_neg_part_select-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.5.1--simple_idx_pos_part_select-sim.sv -l 11.5.1--simple_idx_pos_part_select-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.5.1--simple_idx_select-sim.sv -l 11.5.1--simple_idx_select-sim.sv.log
```

```bash
-cd chapter-11/simple -I../../../../UVM/1800.2-2017-1.0/src/  -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 11.5.1--simple_non_idx_part_select-sim.sv -l 11.5.1--simple_non_idx_part_select-sim.sv.log
```

--------------------------------

### Run a Specific Example: sv2sc

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples/connections/README.txt

To run a single example, specify its name as a target for the 'make' command. For instance, 'make sv2sc' will execute the SystemVerilog producer to SystemC consumer example.

```makefile
make sv2sc
```

--------------------------------

### Get All Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/Methods3.html

Returns a queue containing all command-line arguments used to start the simulation. Useful for introspection or logging.

```SystemVerilog
function void get_args (
    output string args[$]
)
```

--------------------------------

### SystemVerilog Package Example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/hw/dv/doc/dv_plan_template.md

Illustrates common types, parameters, and methods defined at the package level in SystemVerilog. This is a placeholder and should be updated with actual examples.

```systemverilog
[
list a few parameters, types & methods; no need to mention all
]
```

--------------------------------

### Get All Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/General4.html

Returns a queue containing all command-line arguments used to start the simulation. Useful for general argument inspection.

```SystemVerilog
function void get_args (
    output 
    string 
    args[$]
)
```

--------------------------------

### Get All Command Line Arguments

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_cmdline_processor-svh.html

Retrieve all command line arguments used to start the simulation. This function returns a queue of strings.

```SystemVerilog
function void get_args (
                                        
                                        output 
                                        string 
                                        args[$]
                                        )
```

--------------------------------

### Repository Cloning and Updating

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/ariane/tb/dromajo/doc/GitHub-use.md

Basic commands for initial repository setup and keeping the local copy synchronized with the remote.

```bash
git clone https://github.com/chipsalliance/dromajo.git
```

```bash
git pull
```

--------------------------------

### ROM Boot Message Example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/doc/ug/quickstart.md

Observe the terminal output for the ROM boot message after resetting the FPGA. This confirms the bootloader has started.

```text
Commit ID:  1d0d927693c2ef60d7880ab306beb25115a53dcb
Build Date: 2019-11-01, 15:57:43
Jump!

```

--------------------------------

### Get Coverage Command Reference

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Ibex/vendor/google_riscv-dv/docs/source/coverage_model.rst

Execute this command to access the reference guide for the 'cov' tool, detailing available options and their usage.

```bash
cov --help
```

--------------------------------

### Create a Verilog 'Hello World' Module

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/oh/docs/verilog_faq.md

A basic Verilog module that displays 'Hello World!' during simulation. No special setup is required.

```verilog
module hello();

   initial
     begin
        $display ("Hello World!");
     end
   
endmodule
```

--------------------------------

### Get Automatic Phase Objection

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/index/General4.html

Returns the status of the 'automatically object to starting phase' bit and locks its value. Controls phase progression behavior.

```SystemVerilog
function bit get_automatic_phase_objection()
```

--------------------------------

### Get Previous Enabled Callback

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/files/base/uvm_callback-svh.html

Returns the previous enabled callback of type CB from the queue for a given object, starting from a specified iterator position.

```SystemVerilog
static function CB get_prev (
 ref int itr,
 input T obj
)
```

--------------------------------

### Install Header Files

Source: https://github.com/chipsalliance/surelog/blob/master/CMakeLists.txt

Organizes the installation of various Surelog header files into their respective include directories.

```cmake
install(
  FILES ${GENDIR}/include/Surelog/config.h
        ${GENDIR}/include/Surelog/surelog-version.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/CommandLine/CommandLineParser.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/CommandLine)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/SourceCompile/SymbolTable.h
        ${GENDIR}/include/Surelog/SourceCompile/ParseTreeListener.h
        ${GENDIR}/include/Surelog/SourceCompile/ParseTreeTraceListener.h
        ${GENDIR}/include/Surelog/SourceCompile/VObjectTypes.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/SourceCompile)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/Location.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/Error.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/ErrorDefinition.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/ErrorContainer.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/LogListener.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/Report.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/ErrorReporting/Waiver.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/ErrorReporting)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/API/PythonAPI.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/API/SLAPI.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/API/Surelog.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/API)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/Common/ClockingBlockHolder.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/Containers.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/FileSystem.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/NodeId.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/PathId.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/PlatformFileSystem.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/PortNetHolder.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/RTTI.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Common/SymbolId.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/Common)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/DesignCompile/CompileHelper.h
  DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/Surelog/DesignCompile)
install(
  FILES ${PROJECT_SOURCE_DIR}/include/Surelog/Design/ClockingBlock.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Design.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/BindStmt.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Instance.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Signal.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/ValuedComponentI.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/DataType.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Enum.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Struct.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/ModuleDefinition.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Statement.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/VObject.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/DefParam.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/FileCNodeId.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/ModuleInstance.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Task.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/LetStmt.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/DesignComponent.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/FileContent.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/Parameter.h
        ${PROJECT_SOURCE_DIR}/include/Surelog/Design/ParamAssign.h
```

--------------------------------

### Compare packing approaches

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples/converters/README.txt

Demonstrates the difference between using convenience macros and the packer API.

```SystemVerilog
virtual function void do_pack(uvm_packer packer);

   `uvm_pack_int(addr)  -or-
    packer.pack_field(addr,$bits(addr)); //more overhead

endfunction
```

--------------------------------

### Instantiate Read-Only Subregister (p27)

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Earlgrey_0_1/UhdmCoverage/chk42.html

Instantiates a read-only subregister (`prim_subreg`) for field p27. This example demonstrates the standard setup for a single-bit read-only register.

```SystemVerilog
.DW      (1),
    .SWACCESS("RO"),
    .RESVAL  (1'h0)
  ) u_ip0_p27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),
    .we     (1'b0),
    .wd     ('0  ),
    .de     (hw2reg.ip[27].de),
    .d      (hw2reg.ip[27].d ),
    .qe     (),
    .q      (),
    .qs     (ip0_p27_qs)
  );
```

--------------------------------

### Write Binary with spiflash Tool

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/doc/ug/quickstart.md

Use the `spiflash` tool to write the `hello_world` binary to the FPGA. Ensure you are in the correct directory and provide the input binary path.

```console
$ cd $OT_TOP
$ ./sw/host/spiflash/spiflash --input=sw/device/fpga/examples/hello_world/sw.bin
```

--------------------------------

### Get Next Callback

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_callback-svh.html

Retrieves the next enabled callback of a specified type (CB) from the callback queue associated with an object, starting from the position indicated by 'itr'.

```SystemVerilog
static function CB get_next (
    ref int itr,
    input T obj
)
```

--------------------------------

### Get Previous Callback

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/base/uvm_callback-svh.html

Retrieves the previous enabled callback of a specified type (CB) from the callback queue associated with an object, using 'itr' as the starting point for the search.

```SystemVerilog
static function CB get_prev (
    ref int itr,
    input T obj
)
```

--------------------------------

### Install Dependencies and Run Script

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Ibex/vendor/google_riscv-dv/README.md

Install Python dependencies and run the main script with help option. This is recommended for developers working on multiple clones.

```bash
pip3 install -r requirements.txt    # install dependencies (only once)
python3 run.py --help
```

--------------------------------

### Start default phase sequence using uvm_resource_db

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/seq/uvm_sequencer_base-svh.html

Configures the default sequence for a phase using the uvm_resource_db. This example shows setting a sequence instance. The path is constructed dynamically.

```SystemVerilog
myseq_t myseq = new("myseq");
myseq.randomize() with { ... };
uvm_resource_db #(uvm_sequence_base)::set({get_full_name(), ".myseqr.main_phase",
                                          "default_sequence",
                                          myseq, this);
```

--------------------------------

### Get Configuration Value

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.1d/docs/html/files/base/uvm_config_db-svh.html

Retrieves a configuration value for a given field name and instance name, starting the search from a specified context component. The basic get_config_* methods from uvm_component are mapped to this function.

```SystemVerilog
static function bit get(
    uvm_component  cntxt,
    string  inst_name,
    string  field_name,
    inout  T  value
)
```

```SystemVerilog
get_config_int(...) => uvm_config_db#(uvm_bitstream_t)::get(cntxt,...)
```

```SystemVerilog
get_config_string(...) => uvm_config_db#(string)::get(cntxt,...)
```

```SystemVerilog
get_config_object(...) => uvm_config_db#(uvm_object)::get(cntxt,...)
```

--------------------------------

### Run a single simulation example

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/AmiqEth/uvmc-2.2/examples_ovm/converters/README.txt

Executes a specific example by target name.

```makefile
make ex01
```

--------------------------------

### Start default phase sequence using uvm_config_db

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/uvm-1.2/docs/html/files/seq/uvm_sequencer_base-svh.html

Configures the default sequence for a phase using the uvm_config_db. This example shows setting a sequence instance. The path must include the phase name with a '_phase' suffix.

```SystemVerilog
myseq_t myseq = new("myseq");
myseq.randomize() with { ... };
uvm_config_db #(uvm_sequence_base)::set(null, "top.agent.myseqr.main_phase",
                                        "default_sequence",
                                        myseq);
```

--------------------------------

### Get Count of Randomly Generated Sub-sequences

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/UVM/ovm-2.1.2/docs/html/files/methodology/sequences/ovm_sequence_builtin-svh.html

Returns the count of randomly generated sub-sequences. Defaults to the sequencer's count, or a random value if the sequencer's count is -1. Call before sequence start for sequencer.count value.

```SystemVerilog
function int unsigned get_count()

```

--------------------------------

### Define rxenable_setup subregister (7:7)

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/Opentitan/UhdmCoverage/chk82.html

Instantiates a prim_subreg for rxenable_setup with specific parameters for data width, access type, and reset value. This is used for the 7th bit of the setup.

```SystemVerilog
prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (rxenable_setup_setup7_we),
    .wd     (rxenable_setup_setup7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[7].q ),

    // to register interface (read)
    .qs     (rxenable_setup_setup7_qs)
  );
```

--------------------------------

### Start OpenOCD

Source: https://github.com/chipsalliance/surelog/blob/master/third_party/tests/ariane/README.md

Launch OpenOCD using the provided configuration file.

```bash
$ openocd -f fpga/ariane.cfg
Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : clock speed 1000 kHz
Info : TAP riscv.cpu does not have IDCODE
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=64, misa=0x8000000000141105
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
```