### Example Address Space Setup

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

This example demonstrates setting up an address space with RAM, a DUT control interface, and a DMA interface. It shows how to register regions, create windows, and allocate memory blocks.

```python
from cocotbext.axi import AddressSpace, SparseMemoryRegion
from cocotbext.axi import AxiBus, AxiLiteMaster, AxiSlave

# system address space
address_space = AddressSpace(2**32)

# RAM
ram = SparseMemoryRegion(2**24)
address_space.register_region(ram, 0x0000_0000)
ram_pool = address_space.create_window_pool(0x0000_0000, 2**20)

# DUT control register interface
axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk, dut.rst)
address_space.register_region(axil_master, 0x8000_0000)
ctrl_regs = address_space.create_window(0x8000_0000, axil_master.size)

# DMA from DUT
axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi_dma"), dut.clk, dut.rst, target=address_space)
```

```python
# exercise DUT DMA functionality
src_block = ram_pool.alloc_window(1024)
dst_block = ram_pool.alloc_window(1024)

test_data = b'test data'
await src_block.write(0, test_data)

await ctrl_regs.write_dword(DMA_SRC_ADDR, src_block.get_absolute_address(0))
await ctrl_regs.write_dword(DMA_DST_ADDR, dst_block.get_absolute_address(0))
await ctrl_regs.write_dword(DMA_LEN, len(test_data))
await ctrl_regs.write_dword(DMA_CONTROL, 1)

while await ctrl_regs.read_dword(DMA_STATUS) == 0:
    pass

assert await dst_block.read(0, len(test_data)) == test_data
```

--------------------------------

### Install cocotbext-axi from Git

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Install the latest development version directly from the GitHub repository.

```bash
pip install https://github.com/alexforencich/cocotbext-axi/archive/master.zip
```

--------------------------------

### Install cocotbext-axi for Development

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Clone the repository and install the library in editable mode for active development.

```bash
git clone https://github.com/alexforencich/cocotbext-axi
pip install -e cocotbext-axi
```

--------------------------------

### Install cocotbext-axi from PyPI

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Install the latest stable release of the cocotbext-axi library using pip.

```bash
pip install cocotbext-axi
```

--------------------------------

### APB Master and Slave Example

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Shows how to use ApbMaster for register access and ApbRam for memory simulation in APB interfaces.

```Python
import cocotb
from cocotbext.axi import ApbBus, ApbMaster, ApbRam

@cocotb.test()
async def test_apb_interface(dut):
    # APB Master for register access
    apb_master = ApbMaster(
        ApbBus.from_prefix(dut, "s_apb"),
        dut.clk,
        dut.rst
    )

    # Write to peripheral register
    await apb_master.write(0x00, b'\x01\x00\x00\x00')

    # Read peripheral register
    resp = await apb_master.read(0x04, 4)
    value = int.from_bytes(resp.data, 'little')

    # APB RAM for memory simulation
    apb_ram = ApbRam(
        ApbBus.from_prefix(dut, "m_apb"),
        dut.clk,
        dut.rst,
        size=4096
    )

    # Direct memory initialization
    apb_ram.write(0x100, b'test pattern')
```

--------------------------------

### AXI Stream Source and Sink Example

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Demonstrates sending and receiving data using AxiStreamSource and AxiStreamSink, including sideband signals and backpressure.

```Python
import cocotb
from cocotb.triggers import Timer
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
from cocotb.triggers import Event

@cocotb.test()
async def test_axis_loopback(dut):
    # Create source and sink
    axis_source = AxiStreamSource(
        AxiStreamBus.from_prefix(dut, "s_axis"),
        dut.clk,
        dut.rst
    )
    axis_sink = AxiStreamSink(
        AxiStreamBus.from_prefix(dut, "m_axis"),
        dut.clk,
        dut.rst
    )

    # Send simple data
    await axis_source.send(b'Hello AXI Stream!')
    await axis_source.wait()  # Wait for transmission

    # Receive data
    rx_frame = await axis_sink.recv()
    assert bytes(rx_frame) == b'Hello AXI Stream!'

    # Send frame with sideband signals
    frame = AxiStreamFrame(
        tdata=b'packet data',
        tid=5,
        tdest=2,
        tuser=1
    )
    await axis_source.send(frame)

    # Track transmission completion with event
    tx_complete = Event()
    frame = AxiStreamFrame(b'tracked packet', tx_complete=tx_complete)
    await axis_source.send(frame)
    await tx_complete.wait()
    print(f"TX completed at sim time: {frame.sim_time_end}")

    # Apply backpressure with pause
    axis_sink.pause = True
    await Timer(100, 'ns')
    axis_sink.pause = False

    # Use pause generator for random backpressure
    def pause_pattern():
        while True:
            yield False  # Ready
            yield False
            yield True   # Stall

    axis_sink.set_pause_generator(pause_pattern())
```

--------------------------------

### Address Space Abstraction for DMA

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Illustrates building a memory-mapped system using AddressSpace, MemoryRegion, and connecting AXI interfaces for DMA testing.

```Python
import cocotb
from cocotbext.axi import (
    AddressSpace, MemoryRegion, SparseMemoryRegion,
    AxiBus, AxiLiteBus, AxiLiteMaster, AxiSlave
)

@cocotb.test()
async def test_dma_system(dut):
    # Create system address space (32-bit)
    address_space = AddressSpace(2**32)

    # Add RAM at 0x0000_0000
    ram = SparseMemoryRegion(2**24)  # 16MB
    address_space.register_region(ram, 0x0000_0000)

    # Create window pool for dynamic allocation
    ram_pool = address_space.create_window_pool(0x0000_0000, 2**20)

    # Add DUT control registers at 0x8000_0000
    axil_master = AxiLiteMaster(
        AxiLiteBus.from_prefix(dut, "s_axil_ctrl"),
        dut.clk,
        dut.rst
    )
    address_space.register_region(axil_master, 0x8000_0000)

    # Create control register window
    ctrl_regs = address_space.create_window(0x8000_0000, axil_master.size)

    # Connect DUT's DMA master to address space
    axi_slave = AxiSlave(
        AxiBus.from_prefix(dut, "m_axi_dma"),
        dut.clk,
        dut.rst,
        target=address_space
    )

    # Allocate memory blocks for DMA test
    src_block = ram_pool.alloc_window(1024)
    dst_block = ram_pool.alloc_window(1024)

    # Initialize source data
    test_data = b'DMA test payload data'
    await src_block.write(0, test_data)

    # Configure DMA via control registers
    await ctrl_regs.write_dword(0x00, src_block.get_absolute_address(0))  # SRC_ADDR
    await ctrl_regs.write_dword(0x04, dst_block.get_absolute_address(0))  # DST_ADDR
    await ctrl_regs.write_dword(0x08, len(test_data))                     # LENGTH
    await ctrl_regs.write_dword(0x0C, 1)                                  # START

    # Poll for completion
    while await ctrl_regs.read_dword(0x10) == 0:  # STATUS
        await cocotb.triggers.Timer(10, 'ns')

    # Verify DMA result
    result = await dst_block.read(0, len(test_data))
    assert result == test_data
```

--------------------------------

### Bus Object Initialization

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Information on how to initialize and use AXI, AXI-Lite, and APB bus objects for signal management.

```APIDOC
### `AxiBus`, `AxiLiteBus`, and `ApbBus` objects

The `AxiBus`, `AxiLiteBus`, `ApbBus`, and related objects are containers for the interface signals. These hold instances of bus objects for the individual channels, which are currently extensions of `cocotb_bus.bus.Bus`. Class methods `from_entity` and `from_prefix` are provided to facilitate signal name matching.

- For AXI interfaces, use `AxiBus`, `AxiReadBus`, or `AxiWriteBus`, as appropriate.
- For AXI lite interfaces, use `AxiLiteBus`, `AxiLiteReadBus`, or `AxiLiteWriteBus`, as appropriate.
- For APB interfaces, use `ApbBus`.
```

--------------------------------

### Instantiate AxiMaster

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Import and instantiate the AxiMaster class, connecting it to the DUT's AXI bus signals and clock/reset.

```python
from cocotbext.axi import AxiBus, AxiMaster

axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
```

--------------------------------

### Instantiate AXI Bus Objects

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Instantiate various AXI bus objects using `from_prefix` to automatically connect signals based on common naming conventions. Custom signal mapping is also supported.

```python
import cocotb
from cocotbext.axi import (
    AxiBus, AxiReadBus, AxiWriteBus,
    AxiLiteBus, AxiStreamBus, ApbBus
)

@cocotb.test()
async def test_bus_connections(dut):
    # Full AXI bus from prefix (signals: s_axi_awaddr, s_axi_awvalid, etc.)
    axi_bus = AxiBus.from_prefix(dut, "s_axi")

    # Read-only or write-only interfaces
    axi_read_bus = AxiReadBus.from_prefix(dut, "s_axi")
    axi_write_bus = AxiWriteBus.from_prefix(dut, "s_axi")

    # AXI-Lite bus
    axil_bus = AxiLiteBus.from_prefix(dut, "s_axil")

    # AXI Stream bus
    axis_bus = AxiStreamBus.from_prefix(dut, "s_axis")

    # APB bus
    apb_bus = ApbBus.from_prefix(dut, "s_apb")

    # Entity-level connection (no prefix)
    axi_bus_direct = AxiBus.from_entity(dut)

    # Custom signal mapping via keyword arguments
    axis_custom = AxiStreamBus(
        dut,
        prefix="custom",
        suffix="_i"  # custom_tdata_i, custom_tvalid_i, etc.
    )
```

--------------------------------

### Instantiate AxiRam

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Import AxiRam and connect it to the DUT's AXI interface. Specify the memory size during instantiation. The 'mem' attribute can be used to access the underlying memory object.

```python
from cocotbext.axi import AxiBus, AxiRam

axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**32)
```

--------------------------------

### Create Multi-Port AxiRam

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Construct a multi-port RAM by sharing the 'mem' object among multiple AxiRam instances. This allows different ports to access the same memory space.

```python
axi_ram_p1 = AxiRam(AxiBus.from_prefix(dut, "m00_axi"), dut.clk, dut.rst, size=2**32)
axi_ram_p2 = AxiRam(AxiBus.from_prefix(dut, "m01_axi"), dut.clk, dut.rst, mem=axi_ram_p1.mem)
axi_ram_p3 = AxiRam(AxiBus.from_prefix(dut, "m02_axi"), dut.clk, dut.rst, mem=axi_ram_p1.mem)
axi_ram_p4 = AxiRam(AxiBus.from_prefix(dut, "m03_axi"), dut.clk, dut.rst, mem=axi_ram_p1.mem)
```

--------------------------------

### Instantiate AxiSlave

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Import AxiSlave and connect it to the DUT's AXI interface. The target attribute can be set to a MemoryRegion for memory operations.

```python
from cocotbext.axi import AxiBus, AxiSlave, MemoryRegion

axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst)
region = MemoryRegion(2**axi_slave.read_if.address_width)
axi_slave.target = region
```

--------------------------------

### Instantiate AxiStreamSource

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Create an AxiStreamSource instance to drive AXI stream traffic into a design. Connect it to the DUT's clock and reset signals.

```python
axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)
```

--------------------------------

### AXI-Lite and APB Master Optional Arguments

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Details the additional optional arguments available for AxiLiteMaster and ApbMaster, primarily for protection and event handling.

```APIDOC
### Additional optional arguments for `AxiLiteMaster` and `ApbMaster`

- **prot**: AXI protection flags. Defaults to `AxiProt.NONSECURE`.
- **event**: An `Event` object used to wait on and retrieve the result for a specific operation. If `None`, the operation is blocking. The event will be triggered when the operation completes and the result returned via `Event.data`. This is applicable for `init_read()` and `init_write()` methods.
```

--------------------------------

### Instantiate AxiStreamSink

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Create an AxiStreamSink instance to receive AXI stream traffic from a design. It drives the tready line and can exert backpressure.

```python
axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst)
```

--------------------------------

### AXI Stream Constructor Parameters

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Parameters used when initializing an AXI Stream interface object.

```APIDOC
## Constructor Parameters

* `_bus_`: `AxiStreamBus` object containing AXI stream interface signals
* `_clock_`: clock signal
* `_reset_`: reset signal (optional)
* `_reset_active_level_`: reset active level (optional, default `True`)
* `_byte_size_`: byte size (optional)
* `_byte_lanes_`: byte lane count (optional)

Note: _byte_size_, _byte_lanes_, `len(tdata)`, and `len(tkeep)` are all related, in that _byte_lanes_ is set from `tkeep` if it is connected, and `byte_size*byte_lanes == len(tdata)`. So, if `tkeep` is connected, both _byte_size_ and _byte_lanes_ will be computed internally and cannot be overridden. If `tkeep` is not connected, then either _byte_size_ or _byte_lanes_ can be specified, and the other will be computed such that `byte_size*byte_lanes == len(tdata)`.
```

--------------------------------

### Import AXI Stream Classes

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Import necessary classes for AXI stream communication. These are used to drive, receive, or monitor AXI stream interfaces.

```python
from cocotbext.axi import (
    AxiStreamBus,
    AxiStreamSource,
    AxiStreamSink,
    AxiStreamMonitor
)
```

--------------------------------

### Instantiate AxiStreamMonitor

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Create an AxiStreamMonitor instance to passively monitor AXI stream traffic within a design. It does not drive any signals.

```python
axis_mon= AxiStreamMonitor(AxiStreamBus.from_prefix(dut.inst, "int_axis"), dut.clk, dut.rst)
```

--------------------------------

### Perform Non-Blocking AXI Read and Write

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Initiate non-blocking read and write operations using AxiMaster. Use Event objects to wait for completion and retrieve results.

```python
write_op = axi_master.init_write(0x0000, b'test')
await write_op.wait()
resp = write_op.data
read_op = axi_master.init_read(0x0000, 4)
await read_op.wait()
resp = read_op.data
```

--------------------------------

### AXI Master Optional Arguments

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Details the comprehensive list of optional arguments for AxiMaster, covering burst, size, lock, cache, protection, QoS, region, user signals, and event handling.

```APIDOC
### Additional optional arguments for `AxiMaster`

- **arid**: AXI ID for bursts. Defaults to automatically assigned.
- **awid**: AXI ID for bursts. Defaults to automatically assigned.
- **burst**: AXI burst type. Defaults to `AxiBurstType.INCR`.
- **size**: AXI burst size. Defaults to the maximum supported by the interface.
- **lock**: AXI lock type. Defaults to `AxiLockType.NORMAL`.
- **cache**: AXI cache field. Defaults to `0b0011`.
- **prot**: AXI protection flags. Defaults to `AxiProt.NONSECURE`.
- **qos**: AXI QOS field. Defaults to `0`.
- **region**: AXI region field. Defaults to `0`.
- **user**: AXI user signal (aruser). Defaults to `0`.
- **wuser**: AXI wuser signal. Defaults to `0` (write-related methods only).
- **event**: An `Event` object used to wait on and retrieve the result for a specific operation. If `None`, the operation is blocking. The event will be triggered when the operation completes and the result returned via `Event.data`. This is applicable for `init_read()` and `init_write()` methods.
```

--------------------------------

### Perform Blocking AXI Read and Write

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Initiate blocking read and write operations using the AxiMaster. Results are returned upon completion.

```python
await axi_master.write(0x0000, b'test')
data = await axi_master.read(0x0000, 4)
```

--------------------------------

### AXI Stream Interface Classes

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Introduction to AxiStreamSource, AxiStreamSink, and AxiStreamMonitor for managing AXI stream traffic.

```APIDOC
## AXI Stream Interface Classes

### Description
The `AxiStreamSource`, `AxiStreamSink`, and `AxiStreamMonitor` classes facilitate driving, receiving, and monitoring AXI stream interfaces.

- `AxiStreamSource`: Drives all AXI stream signals except `tready`, used for sending traffic into a design.
- `AxiStreamSink`: Drives only the `tready` signal, used for receiving AXI stream traffic and exerting backpressure.
- `AxiStreamMonitor`: Drives no signals, used for passively monitoring traffic anywhere within a design.

### Usage

Import the desired class and connect it to the DUT:

```python
from cocotbext.axi import (
    AxiStreamBus,
    AxiStreamSource,
    AxiStreamSink,
    AxiStreamMonitor
)

# Example instantiation
axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)
axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst)
axis_mon= AxiStreamMonitor(AxiStreamBus.from_prefix(dut.inst, "int_axis"), dut.clk, dut.rst)
```

The first argument to the constructor is an `AxiStreamBus` object, which encapsulates interface signals and provides helper methods for connections.
```

--------------------------------

### AXI RAM Memory Simulation

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Utilize AxiRam to simulate AXI slave memory, supporting sparse memory for large address spaces. It offers direct memory access and word-level operations.

```python
import cocotb
from cocotbext.axi import AxiBus, AxiRam

@cocotb.test()
async def test_axi_ram(dut):
    # Create AXI RAM connected to DUT's master interface
    axi_ram = AxiRam(
        AxiBus.from_prefix(dut, "m_axi"),
        dut.clk,
        dut.rst,
        size=2**20  # 1MB address space
    )

    # Direct memory access (synchronous, no bus transaction)
    axi_ram.write(0x0000, b'test data')
    data = axi_ram.read(0x0000, 9)
    assert data == b'test data'

    # Word-level access
    axi_ram.write_dword(0x100, 0xCAFEBABE)
    value = axi_ram.read_dword(0x100)

    # Debug with hex dump
    axi_ram.hexdump(0x0000, 64, prefix="RAM")

    # Multi-port RAM (shared memory between interfaces)
    axi_ram_p1 = AxiRam(AxiBus.from_prefix(dut, "m00_axi"), dut.clk, dut.rst, size=2**20)
    axi_ram_p2 = AxiRam(AxiBus.from_prefix(dut, "m01_axi"), dut.clk, dut.rst, mem=axi_ram_p1.mem)

    # Both ports share the same memory
    axi_ram_p1.write(0x0000, b'shared')
    assert axi_ram_p2.read(0x0000, 6) == b'shared'
```

--------------------------------

### AXI Master Read and Write Operations

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Use AxiMaster for full AXI4 master capabilities, including burst splitting at 4KB boundaries and managing concurrent operations. It supports blocking and non-blocking read/write transactions.

```python
import cocotb
from cocotb.triggers import Timer
from cocotbext.axi import AxiBus, AxiMaster

@cocotb.test()
async def test_axi_master(dut):
    # Create AXI master connected to DUT's slave interface
    axi_master = AxiMaster(
        AxiBus.from_prefix(dut, "s_axi"),
        dut.clk,
        dut.rst
    )

    # Blocking write - waits for completion
    await axi_master.write(0x0000, b'Hello World!')

    # Blocking read - returns AxiReadResp namedtuple
    resp = await axi_master.read(0x0000, 12)
    assert resp.data == b'Hello World!'
    assert resp.resp == 0  # OKAY

    # Non-blocking write with Event
    write_event = axi_master.init_write(0x1000, b'async data')
    # Do other work...
    await write_event.wait()
    write_resp = write_event.data

    # Non-blocking read
    read_event = axi_master.init_read(0x1000, 10)
    await read_event.wait()
    read_resp = read_event.data

    # Word-access helpers (inherited from Region)
    await axi_master.write_dword(0x2000, 0xDEADBEEF)
    value = await axi_master.read_dword(0x2000)
    assert value == 0xDEADBEEF

    # Wait for all operations to complete
    await axi_master.wait()
```

--------------------------------

### AXI-Lite Master Register Access

Source: https://context7.com/alexforencich/cocotbext-axi/llms.txt

Use AxiLiteMaster for simplified AXI-Lite master operations, ideal for control/status register access. It handles multi-cycle transfers for data wider than the bus.

```python
import cocotb
from cocotbext.axi import AxiLiteBus, AxiLiteMaster

@cocotb.test()
async def test_axil_registers(dut):
    axil_master = AxiLiteMaster(
        AxiLiteBus.from_prefix(dut, "s_axil"),
        dut.clk,
        dut.rst
    )

    # Write control register
    await axil_master.write(0x00, b'\x01\x00\x00\x00')  # Enable bit

    # Read status register
    resp = await axil_master.read(0x04, 4)
    status = int.from_bytes(resp.data, 'little')

    # Word-level access helpers
    await axil_master.write_dword(0x10, 0x12345678)
    config = await axil_master.read_dword(0x10)

    # Check response status
    write_resp = await axil_master.write(0x20, b'\xFF' * 4)
    if write_resp.resp != 0:
        print(f"Write error: {write_resp.resp}")
```

--------------------------------

### AXI Master Operations

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Methods for initiating and managing AXI read and write operations, as well as checking bus status.

```APIDOC
## POST /api/axi/init_read

### Description
Initiates reading a specified number of bytes from a given address.

### Method
POST

### Endpoint
/api/axi/init_read

### Parameters
#### Path Parameters
- None

#### Query Parameters
- **address** (int) - Required - The starting address for the read operation.
- **length** (int) - Required - The number of bytes to read.
- **arid** (int) - Optional - AXI ID for bursts.
- **awid** (int) - Optional - AXI ID for bursts.
- **burst** (string) - Optional - AXI burst type.
- **size** (int) - Optional - AXI burst size.
- **lock** (string) - Optional - AXI lock type.
- **cache** (int) - Optional - AXI cache field.
- **prot** (string) - Optional - AXI protection flags.
- **qos** (int) - Optional - AXI QOS field.
- **region** (int) - Optional - AXI region field.
- **user** (int) - Optional - AXI user signal.
- **event** (object) - Optional - Event object for operation completion.

### Request Body
```json
{
  "address": 0,
  "length": 16,
  "arid": 0,
  "awid": 0,
  "burst": "INCR",
  "size": 4,
  "lock": "NORMAL",
  "cache": 3,
  "prot": "NONSECURE",
  "qos": 0,
  "region": 0,
  "user": 0,
  "event": null
}
```

### Response
#### Success Response (200)
- **event_object** (object) - An Event object that can be used to wait for the operation to complete.

#### Response Example
```json
{
  "event_object": "<event_instance>"
}
```

## POST /api/axi/init_write

### Description
Initiates writing data bytes to a given address.

### Method
POST

### Endpoint
/api/axi/init_write

### Parameters
#### Path Parameters
- None

#### Query Parameters
- **address** (int) - Required - The starting address for the write operation.
- **data** (bytes) - Required - The data to write.
- **arid** (int) - Optional - AXI ID for bursts.
- **awid** (int) - Optional - AXI ID for bursts.
- **burst** (string) - Optional - AXI burst type.
- **size** (int) - Optional - AXI burst size.
- **lock** (string) - Optional - AXI lock type.
- **cache** (int) - Optional - AXI cache field.
- **prot** (string) - Optional - AXI protection flags.
- **qos** (int) - Optional - AXI QOS field.
- **region** (int) - Optional - AXI region field.
- **user** (int) - Optional - AXI user signal.
- **wuser** (int) - Optional - AXI wuser signal.
- **event** (object) - Optional - Event object for operation completion.

### Request Body
```json
{
  "address": 0,
  "data": "0x01020304",
  "arid": 0,
  "awid": 0,
  "burst": "INCR",
  "size": 4,
  "lock": "NORMAL",
  "cache": 3,
  "prot": "NONSECURE",
  "qos": 0,
  "region": 0,
  "user": 0,
  "wuser": 0,
  "event": null
}
```

### Response
#### Success Response (200)
- **event_object** (object) - An Event object that can be used to wait for the operation to complete.

#### Response Example
```json
{
  "event_object": "<event_instance>"
}
```

## GET /api/axi/idle

### Description
Checks if there are any outstanding operations in progress.

### Method
GET

### Endpoint
/api/axi/idle

### Parameters
#### Path Parameters
- None

#### Query Parameters
- None

### Response
#### Success Response (200)
- **is_idle** (boolean) - True if no operations are in progress, False otherwise.

#### Response Example
```json
{
  "is_idle": true
}
```

## POST /api/axi/wait

### Description
Blocks until all outstanding operations complete.

### Method
POST

### Endpoint
/api/axi/wait

### Parameters
#### Path Parameters
- None

#### Query Parameters
- None

### Request Body
```json
{
  "timeout": null
}
```

### Response
#### Success Response (200)
- **status** (string) - Indicates the completion status.

#### Response Example
```json
{
  "status": "completed"
}
```

## POST /api/axi/wait_read

### Description
Blocks until all outstanding read operations complete.

### Method
POST

### Endpoint
/api/axi/wait_read

### Parameters
#### Path Parameters
- None

#### Query Parameters
- None

### Request Body
```json
{
  "timeout": null
}
```

### Response
#### Success Response (200)
- **status** (string) - Indicates the completion status.

#### Response Example
```json
{
  "status": "completed"
}
```

## POST /api/axi/wait_write

### Description
Blocks until all outstanding write operations complete.

### Method
POST

### Endpoint
/api/axi/wait_write

### Parameters
#### Path Parameters
- None

#### Query Parameters
- None

### Request Body
```json
{
  "timeout": null
}
```

### Response
#### Success Response (200)
- **status** (string) - Indicates the completion status.

#### Response Example
```json
{
  "status": "completed"
}
```
```

--------------------------------

### Send Data with AxiStreamFrame and Event

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Send an AxiStreamFrame and wait for its transmission to complete using an event. The frame's simulation time is set upon completion.

```python
frame = AxiStreamFrame(b'test data', tx_complete=Event())
await axis_source.send(frame)
await frame.tx_complete.wait()
print(frame.tx_complete.data.sim_time_start)
```

--------------------------------

### AXI Stream Methods

Source: https://github.com/alexforencich/cocotbext-axi/blob/master/README.md

Methods for interacting with the AXI Stream interface, including sending, receiving, and status checks.

```APIDOC
## Methods

* `send(frame)`: send _frame_ (blocking) (source)
* `send_nowait(frame)`: send _frame_ (non-blocking) (source)
* `write(data)`: send _data_ (alias of send) (blocking) (source)
* `write_nowait(data)`: send _data_ (alias of send_nowait) (non-blocking) (source)
* `recv(compact=True)`: receive a frame as a `GmiiFrame` (blocking) (sink)
* `recv_nowait(compact=True)`: receive a frame as a `GmiiFrame` (non-blocking) (sink)
* `read(count)`: read _count_ bytes from buffer (blocking) (sink/monitor)
* `read_nowait(count)`: read _count_ bytes from buffer (non-blocking) (sink/monitor)
* `count()`: returns the number of items in the queue (all)
* `empty()`: returns _True_ if the queue is empty (all)
* `full()`: returns _True_ if the queue occupancy limits are met (source/sink)
* `idle()`: returns _True_ if no transfer is in progress (all) or if the queue is not empty (source)
* `clear()`: drop all data in queue (all)
* `wait()`: wait for idle (source)
* `wait(timeout=0, timeout_unit='ns')`: wait for frame received (sink)
* `set_pause_generator(generator)`: set generator for pause signal, generator will be advanced on every clock cycle (source/sink)
* `clear_pause_generator()`: remove generator for pause signal (source/sink)
```